JPH08147397A - Linear multiplier and divider - Google Patents

Abstract

PURPOSE: To improve the accuracy of multiplication and division and to reduce power consumption by making an FET a variable resistance. CONSTITUTION: As for the input X from an input terminal 8, the AC voltage XAC is separated by a capacitor 4 and the voltage is supplied as an input to be calculated to the source S of an FET 1 via a fixed resistor 3. Also the voltage E of a DC voltage source 5 is supplied as a division input to the source S of the FET 1 via an inductor 6 and the fixed resistor 3. The drain D of the FET 1 is grounded, the source S is connected with an output terminal 7 and the DC voltage ZDC of the output Z obtained at this output terminal 7 is supplied to an integrator 2. The DC multiplication input YDC as the reference voltage is supplied to the integrator 2 from an input terminal 9, the output of the integrator 2 is supplied as gain control voltage to the gate G of the FET 1, and servo is applied so that the DC voltage ZDC of the output Z may be equal to the multiplication input YDC. Thus, the AC voltage ZAC of the output Z becomes the voltage that the product of the input XAC to be calculated and the multiplication input YDC is divided by the division input E.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear multiplier / divider which uses an FET (field effect transistor) as a variable resistance element and which multiplies an input to be multiplied by a multiplication input or divides by a division input.

[0002]

2. Description of the Related Art Conventional linear multipliers / dividers generally use a logarithmic conversion system. Here, assuming that analog multiplicands and multipliers are respectively X and Y, logarithmic conversion of these is performed, Log (XY) = LogX + LogY is calculated, and the obtained Log (XY) is inversely logarithmically converted. Gives the product XY of X, Y.

FIG. 9 is a diagram showing the basic configuration of a linear multiplier based on such a principle. 100 and 101 are logarithmic amplifiers, 102 is an adder, and 103 is an antilogarithmic amplifier.

In the figure, the operand input X and the multiplication input Y are converted into logarithms by logarithmic amplifiers 100 and 101, respectively, and added by an adder 102. The adder 102 is composed of an operational amplifier, a resistor, an inverting circuit and the like. The output of the adder 102 is antilogarithmically converted by the antilogarithmic amplifier 103, and as described above, the product X of the operand input X and the multiplication input Y is obtained.
Y is obtained.

By using a subtractor instead of the adder 102, the ratio X / Y of X and Y can be obtained from the antilogarithmic amplifier 103 with Y as a division input.

As the logarithmic amplifiers 100 and 101 and the antilogarithmic amplifier 103, the relationship between the base-emitter voltage V _{BE of} the transistor and the collector current I _C is usually used. That is, in an ideal transistor, between these,

[0007]

[Equation 1]

However, k: Boltzmann's constant T: Absolute temperature q: Electron charge amount I _C : Transistor collector current I _ES : Emitter junction short-circuit saturation current holds, and if the collector current I _C is changed linearly,
A base-emitter voltage V _BE proportional to the logarithm of the collector current I _C is obtained between the base and the emitter.

As another example of the linear multiplier / divider,
A Gilbert cell as shown in FIG. 10 is known. This is a typical linear multiplier / divider suitable for a monolithic IC, and most linear multiplier / dividers currently employ this method. This system also utilizes the logarithmic characteristic of V _BE -I _C of the transistor, but is characterized in that it can perform multiplication / division of four phenomena and the core simultaneously performs logarithmic conversion and current addition. .

[0010]

By the way, in the above linear multiplier / divider shown in FIG. 9, logarithmic amplifiers 100 and 10 are used.
1 or a transistor V _BE -I as the antilogarithmic amplifier 103
_{When the C} characteristic is used, this characteristic depends on the absolute temperature T, as shown in the above mathematical expression 1, so that it is easily affected by the temperature and temperature compensation is difficult. Moreover, if there is a difference in characteristics between the logarithmic amplifiers 100 and 101 and the antilogarithmic amplifier 103, or if there is a difference in temperature between the logarithmic amplifiers 100 and 101 and the antilogarithmic amplifier 103 that are located apart from each other. However, there is a problem that an error occurs in the output of the antilogarithmic amplifier 103.

Further, in the Gilbert cell shown in FIG. 10, as shown in the figure, when a constant current source is included, three stages of transistors operating in the active region are connected in series. Is required, a power supply voltage of at least 9 V is required, which makes it difficult to reduce the voltage. In addition, a plurality of circuits that configure the differential amplifier are connected in parallel when viewed from the power source, and therefore,
The current consumption also increases. As a result, there is also a problem that it is difficult to reduce power consumption.

An object of the present invention is to provide a linear multiplier / divider which solves such a problem, improves the calculation accuracy, and can significantly reduce the power consumption.

[0013]

In order to achieve the above object, the present invention provides an FE which operates in a variable resistance region in which a source is supplied with an operated input of an AC voltage and a divided input of a DC voltage.
T and an integrator which is supplied with a DC voltage multiplication input as a reference voltage and integrates the difference between the DC voltage obtained at the source of the FET and the multiplication input, and the output of the integrator is used as a control voltage for the FET. Is supplied to the gate of the FET and the servo is applied so that the DC voltage obtained between the source and drain of the FET becomes equal to the multiplication input, and the multiplication / division calculation force is obtained from the source of the FET.

[0014]

As a gain control circuit, one using a variable resistance characteristic of FET is known. FIG. 11 is a diagram showing the basic configuration thereof, in which the first input X is supplied to the source S of the FET 104 via the fixed resistor 105, and the second input Y is supplied to the gate G of the FET 104. The drain D of the FET 104 is grounded.

In this configuration, the output Z is obtained from the source S of the FET 104, but since the FET 104 acts as a variable resistor, this FET is now used.
When the resistance value between the source and drain of 104 is R ₁ and the resistance value of the fixed resistor 105 is R ₀ ,

[0016]

[Equation 2]

The resistance value R ₁ between the source and the drain of the FET 104 changes according to the input Y supplied to the gate G of the FET 104.

Here, when the resistance value R ₁ is sufficiently smaller than the resistance value R ₀ , the output Z is the FET 10 according to the above _{equation (} 2).
4 is proportional to the resistance value R ₁ between the source and drain, and
If this resistance value R ₁ is proportional to the input Y, the output Z will be the product XY of the inputs X and Y. Therefore, the gain control circuit shown in FIG. 11 has a function as a linear multiplier.

However, in reality, the resistance value R ₁ between the source and drain of the FET 104 and the impedance with respect to the voltage value (gain control voltage) of the input Y supplied to the gate G of the FET 104 are as shown in FIG. It will exhibit non-linear characteristics (as an FET,
2SJ105GR as an example). In FIG. 11, when the input X is kept constant and the input Y is changed, the degree of direct current amplification shows a non-linear characteristic as shown in FIG.
Therefore, the gain control circuit as shown in FIG. 11 cannot be used as it is as a linear multiplier / divider.

The present invention basically has a structure having a part of the circuit shown in FIG. 11, but as described above, the above-mentioned AC input is input to the FET source through the fixed resistor. X is supplied with X and DC input E, and an integrator is provided, and the FET is connected to the output of the integrator so that the DC voltage obtained between the source and drain of the FET matches the multiplication input. By controlling, the AC voltage obtained between the source and drain of the FET becomes equal to the product of the input X and the input Y divided by the input E. Therefore, by setting the input X as the operated input, the input Y as the multiplication input, and the input E as the division input, the AC voltage obtained between the source and drain of the FET multiplies the operated input by the multiplication input Y and the division input E. It will be the sum.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a linear multiplier / divider according to the present invention, in which 1 is an FET, 2 is an integrator, 2a is an operational amplifier, 2b is a capacitor, 2c and 3 are fixed resistors,
4 is a capacitor, 5 is a DC voltage source, 6 is an inductor, 7
Is an output terminal, and 8 and 9 are input terminals.

In the figure, the input X from the input terminal 8 is supplied to the capacitor 4, the AC voltage X _AC of the input X is extracted, and is supplied to the source S of the FET 1 via the fixed resistor 3. The drain D of this FET 1 is grounded. Further, the DC voltage E of the DC voltage source 5 is supplied to the source S of the FET 1 via the inductor 6 and the fixed resistor 3. F
The source S of ET1 is connected to the output terminal 7 and also to the integrator 2, and the output terminal of the integrator 2 is connected to the gate G of the FET1.

In the integrator 2, the output terminal 7 (hence the FE
The DC voltage Z _{DC of the} output Z obtained at the source S) of T1 is supplied as an inverting input to the operational amplifier 2a via the fixed resistor 2c, and as a non-inverting input of the operational amplifier 2a, the reference from the input terminal 9 is used. Input of DC voltage as voltage Y
Is supplied. The output of the operational amplifier 2a, which is the integrated value of the difference between the DC voltage Z _DC and the input Y _DC , is supplied to the gate G of the FET 1 as a gain control voltage. A capacitor 2b is provided between the input and output terminals of the operational amplifier 2a.

The inductor 6 is for preventing the AC voltage X _AC from the capacitor 4 from leaking to the DC power source 5 side.

The FET1 operates in the variable resistance region, not in the active region, so that almost no voltage is applied between the drain and the source. And the output of the integrator 2 is FET
By being applied to the gate G of 1 as a gain control voltage, the difference between the DC voltage Z _DC of the output Z, which is the voltage between the source and drain of the FET 1, and the input Y, which is the reference voltage, becomes 0, that is, Servo is applied so that the DC voltage Z _DC and the input Y become equal.

Therefore, assuming that the resistance value between the source and drain of the FET ₁ is r ₁ and the resistance value of the fixed resistor 3 is r ₀ , the DC voltage is as follows.

[0027]

(Equation 3)

[0028]

[Equation 4]

Is satisfied. Therefore, from Equations 3 and 4,

[0030]

(Equation 5)

It is Regarding the AC voltage, FE
Assuming that the impedance between the source and drain of T1 is equal to r ₁ ,

[0032]

(Equation 6)

Substituting the above equation 5 into

[0034]

(Equation 7)

[0035]

According to the above equation 7, when the AC voltage Z _AC of the output Z obtained at the output terminal 7 is the operated input of the AC voltage X _AC of the input X, the multiplication input of the input Y, and the division input of the DC voltage E, This is the product of the calculated input X _AC and the multiplication input Y divided by the division input E. Therefore, this example
If the DC voltage E is constant, the AC voltage Z _AC of the output Z is the operated input X _AC multiplied by the multiplication input Y. If the input Y is fixed, the AC voltage Z _AC is the divided input X _{AC. AC} divided by input E, and input Y
Is a multiplication input, and the DC voltage E is a division input, the AC voltage Z _AC is the product input X _AC multiplied by the multiplication input Y and divided by the division input E, which is a linear multiplication / division circuit.

In this way, FET1 is used as a variable resistor,
By controlling the resistance and impedance between the source and drain of the FET 1 by the integrator 2 and performing servo control so that the DC voltage Z _DC of the output Z becomes equal to the input Y, the non-synchronization as shown in FIGS. It can improve the characteristics of the straight line and function as a linear multiplier / divider.

By the way, as the power consumed in this embodiment, in FIG. 1, it is considered that the power is consumed by the direct current flowing through the resistance between the source and the drain of the FET 1 and the power consumed by the integrator 2. However, the former one is F
The current flowing through the resistance between the source and drain of ET1 is set to 0.
Since the resistance is about 2 mA and the resistance is sufficiently small, the voltage generated in the resistance can be reduced to about 50 mV. Therefore, the power consumption of the resistance is 0.01 mW.
It can be a degree. Regarding the latter, for example, if the operational amplifier 2a has a single power supply of 3V and has a power of 0.3 mA, the power consumption is 0.9 mW. And even if these are summed up, power consumption is very low. Incidentally, for example, JP-A-64-82815, JP-A-2-11014, and JP-A-2-193402.
In a commercially available divider using a logarithmic method as described in Japanese Patent Publication No. JP-A-2003-242, the power consumption is 128 mW, which is 1/100 or less of this divider in this embodiment.

Further, in this embodiment, since the output Z _AC shown in the above equation 7 is obtained, the precision of multiplication / division is very high. An error factor that is considered to deteriorate this accuracy is that the offset of the operational amplifier 2a does not match the DC resistance value between the source and drain of the FET1 and the AC impedance in FIG. 1 (in FIG. 12, the control DC voltage is almost the same). It is shown that these disagreements occur at 2 V or more). However, regarding the latter, FETs with which they are sufficiently matched are commercially available, and the deviation of the gain between DC and AC is within 5%, as will be explained below. I understood from. Therefore, high accuracy can be obtained.

In FIG. 1, the FET 1 is a P-channel type, but it is possible to use an N-channel type by reversing the polarity of the power source.

Further, instead of the voltage source 5 and the inductor 6, a current source and a semiconductor inductor may be used as shown in FIG.

FIG. 2 is a circuit diagram showing a more specific structure when the linear multiplier / divider shown in FIG. 1 is used as a linear multiplier. 1a, 1b and 1c are FETs, and FIG.
The same reference numerals are given to the portions corresponding to, and the overlapping description will be omitted.

In this figure, three FETs 2SJ105 (FET1, FET2, FET3) are provided in parallel as the FET1 so that the variable range of the resistance value of the FET is widened. An AD820 is used as the operational amplifier 2a, and the cutoff frequency of the integrator 2 is 16 Hz. The signal frequency is 3 kHz, and the inductance of the inductor 6 is about 1.2H. The resistance value of the fixed resistor 2c of the integrator 2 is 100 kΩ, and the capacitance of the capacitor 2c is 0.1 μF.

In such a configuration, when the input X _AC and E are kept constant and the input Y is changed, a change in gain (Z _AC / X _AC ) as shown in FIG. 3 is obtained, and the plot in FIG. 3 is obtained. Gain (Z _AC / X
_If we ask for _AC ), we get:

[0045]

(Equation 8)

Therefore, the constant on the right-hand side of this equation 8 is very small, so if this is regarded as 0, this specific example

[0047]

[Equation 9]

The multiplication process is performed. Here, the reason why the gain does not become 1 as in Expression 8 is that the DC resistance and the impedance in the FETs 1a, 1b, and 1c do not completely match, as shown in FIG. FET1a, which cannot be set to 0,
This is because the ON resistances at 1b and 1c are about 300Ω, respectively.

Next, from the graph of FIG. 3, the gain deviation D {G
(Y)} was calculated to find the linearity of the multiplication characteristics. The gain deviation here is, instead of the differential gain deviation,
Each plotted data of FIG. 3 was calculated by the following method.

[0050]

[Equation 10]

However, G (Y): gain at the input Y F (Y): gain at the input Y according to the above equation 9 The result of this calculation is shown in FIG. According to this, even if the gain was changed from 0.04 to 0.88 by 20 times, the gain deviation was within ± 5%.

FIG. 5 is a circuit diagram showing a more specific structure when the linear multiplier / divider shown in FIG. 1 is used as a linear divider, and the portions corresponding to those in FIG. A duplicate description will be omitted.

In the figure, a fixed resistor of 10 kΩ is provided between the two input terminals of the operational amplifier 2a, and a fixed resistor of 100 kΩ and a capacitor of 47 pF are provided between the operational amplifier 2a and the fixed resistor 2c. Is provided with a noise filter. The other configuration is the same as that of the linear multiplier shown in FIG.

In this structure, when the input Y was kept constant at 5 mV and the division input E was changed within the range of 5 to 100 mV, the division characteristic as shown in FIG. 6 was obtained. Here, in FIG. 6, the horizontal axis is the normalized divisor, which is
/ Y. Further, when the divisor coefficient is calculated from FIG. 6,
As shown in FIG. 7, it was found to be approximately 1.057. As a result, the linear divider shown in FIG.

[0055]

[Equation 11]

It can be seen that the calculation of is performed.

Further, when the division gain deviation when the gain is changed over 20 times is obtained, it becomes as shown in FIG. 8, and this deviation is within ± 3%.

[0058]

As described above, according to the present invention,
The FET can be used as a variable resistor, and its resistance value and impedance can be changed in proportion to the constant input. Multiplication and division can be performed with high accuracy, and power consumption can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a linear multiplier / divider according to the present invention.

FIG. 2 is a circuit diagram showing a more specific configuration when the embodiment shown in FIG. 1 is used as a linear multiplier.

FIG. 3 is a diagram showing multiplication characteristics in the specific example shown in FIG.

FIG. 4 is a diagram showing a gain deviation characteristic in the specific example shown in FIG.

5 is a circuit diagram showing a more specific configuration when the embodiment shown in FIG. 1 is used as a linear divider.

6 is a diagram showing a division characteristic of the specific example shown in FIG.

7 is a diagram showing changes in the division coefficient of the specific example shown in FIG.

8 is a diagram showing a division gain deviation of the specific example shown in FIG.

FIG. 9 is a circuit diagram showing an example of a conventional multiplier / divider.

FIG. 10 is a circuit diagram showing another example of a conventional multiplier / divider.

FIG. 11 is a circuit diagram showing a gain control circuit using an FET, which is a basic configuration of the present invention.

FIG. 12 is a diagram showing characteristics of resistance and impedance with respect to the gate voltage of the FET.

13 is a diagram showing the characteristics of the DC amplification degree with respect to the gate voltage of the FET in the gain control circuit shown in FIG.

FIG. 14 is a diagram showing a main part of a modified example of the embodiment shown in FIG.

[Explanation of symbols]

 1 FET 2 integrator 2a operational amplifier 2b capacitor 2c, 3 fixed resistor 4 capacitor 5 DC voltage source 6 inductor 7 output terminal 8, 9 input terminal

Claims (2)

[Claims] 1. A source is supplied with an AC voltage operated input and a DC voltage divided input, and a field effect transistor operating in a variable resistance region and a DC voltage multiplied input are supplied as a reference voltage. A source of the field effect transistor is provided with an integrator that integrates the difference between the DC voltage obtained at the source of the transistor and the multiplication input, and supplies the output of the integrator as a control voltage to the gate of the field effect transistor. A linear multiplier / divider characterized in that a servo is applied so that a direct current voltage obtained between the drains and the multiplication input are equalized to obtain a multiplication / division calculation force from the source of the field effect transistor. 2. A direct current resistance value and an impedance with respect to a control voltage supplied to a gate, the source of which is supplied with an operated input of an alternating voltage and the input of division of a direct current voltage via a fixed resistor, the drain of which is grounded. A field effect transistor that operates in a variable resistance region so that the values substantially match, and a multiplication input of a DC voltage is supplied as a reference voltage, and a difference between the DC voltage obtained at the source of the field effect transistor and the multiplication input is calculated. An integrator for integrating the output of the integrator as the control voltage, and applying a servo so that the direct current voltage obtained between the source and drain of the field effect transistor and the multiplication input are equalized, A linear multiplier / divider configured to obtain a multiplication / division calculation force from the source of an effect transistor.