JPH08140287A - Memory backup control - Google Patents

Abstract

PURPOSE: To back up a memory surely with less circuits without using another power supply for charging. CONSTITUTION: A memory back-up control has a memory, at least two secondary batteries 2, 3, and a supply voltage detecting means 1. It also has a connection switching means 4 which connects the secondary batteries 2, 3 in parallel and then charges the memory when the supply voltage detected by the supply voltage detecting means 1 is a specified level or above and which connects the secondary batteries 2, 3 in series and then supplies backup power to the memory through a step-down circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory backup control device for backing up data stored in a volatile memory.

[0002]

2. Description of the Related Art The following is known as a memory backup control device of this type.

(1) When a DRAM (dynamic RAM) is backed up using a lithium secondary battery having a nominal voltage of 3.0 V, the guaranteed operation voltage of the DRAM is higher than the output voltage of the secondary battery. A plurality of secondary batteries are connected in series and a backup power supply is supplied via a step-down circuit. When the power is on, charging is performed using a voltage higher than the total voltage of the secondary batteries connected in series.

(2) When one of the lithium batteries is connected or used in parallel, a backup power source is supplied via a booster circuit composed of a DC-DC converter or the like.

(3) When switching to the backup power supply using the detection signal from the power supply voltage detection circuit for detecting the power supply voltage, the detection signal is monitored by the control circuit or the CPU, and the data is processed by hardware or software. The write or read signal is controlled to switch to the data holding state.

[0006]

However, each of the above conventional examples has the following drawbacks.

In the case of the device (1) described above, if the device controls the memory backup with a configuration in which secondary batteries are connected in series, a power source having a voltage higher than the series voltage of the secondary battery is used when the power is turned on. Therefore, it is necessary to provide a charging power source separately from the main power source of the device circuit including the memory.

In the case of the device (2) described above, if the booster circuit is connected to the output of the secondary battery, the circuit scale of the booster circuit becomes large and the energy loss in the booster circuit is large. Therefore, there is a problem that the discharge life of the secondary battery is shortened.

In the case of the above-mentioned device (3), since the backup signal is switched by using the detection signal from the power supply voltage detection circuit, the memory is accessed and the detection signal is generated asynchronously, so that the memory is written or read. If a detection signal is output during the operation, the data to be written or read may be destroyed in order to switch to the data holding state without normally ending the writing or reading operation.

Further, in the case of this apparatus, the detection signal is C
When monitoring the operation with a PU, etc., and switching the operation of the memory by program processing, the switching of the operation is normally performed within the time when the power supply voltage drops to the operation guarantee voltage value of the device circuit after detecting the detection signal. It is necessary to terminate it, considering the overhead associated with the execution of programs such as CPU,
It is necessary to increase the time constant for the output voltage to drop when the power is turned off, and a power supply with a large capacity must be used.

The present invention has been made in view of the above circumstances, and does not require a separate power source for charging, requires a small circuit configuration, and does not cause troubles such as data destruction and can reliably perform memory. It is an object of the present invention to provide a memory backup control device capable of performing backup of the above.

[0012]

A memory backup control device according to claim 1, wherein a memory, at least two secondary batteries, a power supply voltage detecting means for detecting a power supply voltage of the device, and a power supply voltage detecting means. When the power supply voltage detected by the means is equal to or higher than a predetermined voltage, the secondary batteries are connected in parallel to perform charging, and when the power supply voltage is equal to or lower than the predetermined voltage, the secondary batteries are connected in series to the memory via a step-down circuit. And a connection switching means for supplying backup power.

A memory backup control device according to a second aspect of the present invention detects a volatile memory having a self-refresh function for holding data by self-refreshing, at least two secondary batteries, and a power supply voltage of this device. Power supply voltage detecting means and charging is performed by connecting the secondary batteries in parallel when the power supply voltage detected by the power supply voltage detecting means is equal to or higher than a predetermined voltage, and is connected in series when the power supply voltage is equal to or lower than the predetermined voltage. Connection switching means for supplying backup power to the volatile memory through a step-down circuit, and self-refresh for starting self-refresh at backup when the power supply voltage detected by the power supply voltage detection means falls below a predetermined voltage. Refresh cycle request means for sending a refresh request, and cells from this refresh cycle request means In response to a refresh request, the access request to the volatile memory is prohibited from a plurality of processing units, and the volatile memory self-refresh is activated at the end of the memory cycle being executed by arbitrating with the access request. It has a control means for controlling.

A memory backup control device according to a third aspect of the present invention detects a volatile memory having a self-refresh function for holding data by self-refreshing, at least two secondary batteries, and a power supply voltage of this device. Power supply voltage detecting means and charging is performed by connecting the secondary batteries in parallel when the power supply voltage detected by the power supply voltage detecting means is equal to or higher than a predetermined voltage, and is connected in series when the power supply voltage is equal to or lower than the predetermined voltage. Connection switching means for supplying backup power to the volatile memory through a step-down circuit, and self-refresh for starting self-refresh at backup when the power supply voltage detected by the power supply voltage detection means falls below a predetermined voltage. A power supply voltage detected by the power supply voltage detection means has risen above a predetermined voltage while sending a refresh request. And a refresh cycle requesting means for canceling the self-refresh request, and access to the volatile memory from a plurality of processing units at the end of a self-refresh memory cycle accompanying cancellation of the self-refresh request by the refresh cycle requesting means. And a control means for permitting the request.

[0015]

According to the memory backup control device of the present invention, when the power supply voltage detecting means detects the power supply voltage of the device and the connection switching means detects the power supply voltage detected by the power supply voltage detecting means is equal to or higher than a predetermined voltage. The secondary batteries are connected in parallel for charging, and when the voltage is lower than a predetermined voltage, the secondary batteries are connected in series and backup power is supplied to the memory through a step-down circuit. With this, it becomes possible to charge the secondary battery, and it is not necessary to separately provide a power source for charging, and when the power supply voltage drops below a predetermined voltage, the secondary battery and the voltage step-down circuit are applied to the memory. Backup can be performed reliably.

According to another aspect of the memory backup control device of the present invention, when the power supply voltage detecting means detects the power supply voltage of the device and the connection switching means detects the power supply voltage detected by the power supply voltage detecting means is equal to or higher than a predetermined voltage. The secondary batteries are connected in parallel for charging, and when the voltage is below a predetermined voltage, the secondary batteries are connected in series to supply backup power to the memory via a step-down circuit.

At this time, the refresh cycle request means is
A self-refresh request for activating self-refresh at the time of backup is sent when the power supply voltage detected by the power supply voltage detection means falls below a predetermined voltage.

The control means prohibits access requests to the volatile memory from a plurality of processing sections in response to the self-refresh request from the refresh cycle request means, and arbitrates with the access requests to execute a memo. At the end of recycling, activate volatile memory self-refresh.

As a result, even when the power supply voltage is lower than the predetermined voltage, the cycle sequence is not forcibly changed without normally ending the data write / read cycle, and the data destruction can be prevented.

According to another aspect of the memory backup control device of the present invention, the power supply voltage detecting means detects the power supply voltage of the device, and the connection switching means detects that the power supply voltage detected by the power supply voltage detecting means is equal to or higher than a predetermined voltage. The secondary batteries are connected in parallel for charging, and when the voltage is below a predetermined voltage, the secondary batteries are connected in series to supply backup power to the memory via a step-down circuit.

At this time, the refresh cycle request means is
A self-refresh request for activating self-refresh at the time of backup is sent when the power supply voltage detected by the power supply voltage detection means falls below a predetermined voltage. The refresh cycle requesting means cancels the self-refresh request when the power supply voltage detected by the power supply voltage detecting means rises above a predetermined voltage.

The control means permits the access request to the volatile memory from the plurality of processing units at the time when the self-refresh memory cycle is completed with the cancellation of the self-refresh request by the refresh cycle request means.

As a result, the overhead associated with the execution of the program mediated by the CPU is eliminated, and the volatile memory can be brought into the data holding state accurately and at high speed.

[0024]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing the configuration of the memory backup control device of this embodiment.

The memory backup control device shown in the figure has a power supply voltage detecting means 1 comprising a comparator for detecting a power supply voltage Vcc, secondary batteries 2 and 3, and an output signal from the power supply voltage detecting means 1 (high level or Low level P
OW DWN signal), connection switching means 4 including a relay circuit 14 for switching and connecting the secondary batteries 2 and 3 in series or in parallel, and the secondary batteries 2 and 3 are terminals B1 and B2 of the secondary battery connecting portion 16. , B3 and B4 are connected in parallel, the charging circuit 5 supplies a constant voltage from the power source to the secondary batteries 2 and 3, and the secondary batteries 2 and 3 are connected to the secondary battery connecting portion 17
A step-down circuit 6 for generating a backup voltage for the volatile memory 7 from the series voltage of the secondary batteries 2, 3 when connected in series to the terminals A1, A2, A3, A4 of the memory, and a memory with a self-refresh function. Volatile memory (D
A control means 15 for performing various controls on the RAM 7;
When the power supply voltage Vcc detected by the power supply voltage detection means 1 and the CPU processing section 8 connected to the control means 15 via an address bus and a data bus are lower than a predetermined voltage, self-refresh at the time of backup is activated. A refresh cycle generating circuit 9 as a refresh request means for sending out a self refresh request (REF) 9a and canceling the self refresh request 9a when the power supply voltage detected by the power supply voltage detecting means 1 rises above a predetermined voltage. It is equipped with.

The control means 15 is the system control unit 1
0, an arbitration circuit 11 and a memory control circuit 12. The system control unit 10 converts the address signal and data signal of the address bus and data bus of the CPU processing unit 8 into a multiplexed address and data of the volatile memory 7 according to a control signal from the memory control unit 12. .

The CPU processing section 8 sends a write / read signal (WR, RD) 8a to the arbitration circuit 11.

The arbitration circuit 11 prohibits access requests from the plurality of processing units to the volatile memory 7 in response to the self-refresh request 9a from the refresh cycle generation circuit 9 and arbitrates with the access request. The self-refresh of the volatile memory 7 is activated at the end of the memory cycle being executed.

The arbitration circuit 11 also sends a system identification signal 11a to the system controller 10. Further, the memory control circuit 12 has a function of the arbitration circuit 11
In accordance with the access identification signal 11a from the volatile memory 7
, The timing generation of the control signals (RAS, CAS) 12a specified in various access cycles is performed.

FIG. 2 is a state diagram showing the switching operation of the secondary batteries 2 and 3 of the memory backup control device of FIG.

The left and right columns in FIG. 2 are the relay circuit 1
4 shows an example in which the secondary batteries 2 and 3 are connected to the terminals B1 and B2 and the terminals B3 and B4, respectively. The middle column of FIG. 2 indicates that the secondary batteries 2 and 3 are connected to the terminals A1, A2 and A3, respectively. It shows an example of connection to A4.

Next, the operation of the memory backup controller will be described with reference to FIGS.

As shown in FIG. 3, since + 5V is stably supplied as the power supply voltage Vcc from the power supply during the normal operation, the output signal (POWDWN) of the power supply voltage detecting means 1 is obtained.
1a is a high level. The relay circuit 14 in the connection switching means 4 is driven to the B side by the input of the output signal 1a, and the secondary batteries 2 and 3 are in the states shown in the left column or the right column of FIG. It is connected in parallel with the charging circuit 5 in the section 16.

At this time, the secondary batteries 2 and 3 are charged from the power source through the charging circuit 5.

Next, when the power supply voltage Vcc drops from + 5V to a predetermined voltage (VCC1 shown in FIG. 3) when the power supply voltage is turned off, the output signal 1a of the power supply voltage detecting means 1 falls to a low level. The relay circuit 14 in the connection switching means 4 is driven to the A side by the input of the output signal 1a, the secondary batteries 2 and 3 are in the state shown in the middle column of FIG. And are connected in series. At this time, the series voltage of the secondary batteries 2 and 3 is supplied to the volatile memory 7 as a backup power source via the step-down circuit 6.

When the power supply voltage Vcc rises from 0V to a predetermined voltage (VCC2) at power-on, the output signal 1a of the power supply voltage detecting means 1 rises to a high level as shown in FIG. With the input of, the relay circuit 14 in the connection switching means 4 is driven to the B side, and the connection of the secondary batteries 2 and 3 is switched in parallel.

Therefore, the secondary batteries 2 and 3 are charged from the power source through the charging circuit 5 in the same manner as in the normal operation.

The output of the output signal 1a is VCC1 and VCC when the power supply voltage Vcc falls and rises.
2 is different because of the existence of the hysteresis characteristic of the comparator constituting the power supply voltage detecting means 1.

FIG. 4 is a timing chart showing access control of the volatile memory 7.

Referring to FIGS. 1 and 4, the volatile memory 7
The control of will be described.

The state 1 shown in FIG. 4 is the CPU processing unit 8
Data write / read signal (WR, RD) by 8
When only a occurs, the arbitration circuit 11 writes the
The read signal (WR, RD) 8a is received and the access identification signal 11a for instructing writing / reading to the volatile memory 7 is output to the memory control circuit 12. The memory control circuit 12 outputs a control signal 12a (RAS, CAS) at a timing defined by the write / read cycle of the volatile memory 7 according to the access identification signal 11a.

State 2 in FIG. 4 is a case where the refresh request signal (REF) 9a is generated, and the arbitration circuit 11 receives the refresh request signal 9a and receives the volatile memory 7 therein.
An access identification signal 11a for instructing refreshing is output to the memory control circuit 12. The memory control circuit 12 outputs a control signal (RAS, CAS) 12a at a timing defined by the refresh cycle of the volatile memory 7 according to the access identification signal 11a.

In the state 3 of FIG. 4, the power supply is turned off and the output signal 1a of the power supply voltage detecting means 1 is output at a low level while the data write / read signal (WR, RD) 8a is being generated. In this case, the arbitration circuit 11 determines the access identification signal 11 based on the signal generation order and the priority.
control a.

In this case, the arbitration circuit 11 first receives the data write / read signals (WR, RD) with priority. Further, in parallel, masking of the data write / read signals (WR, RD) is performed in response to the output signal 1a for preventing the write / read from being continuously performed. Then, after the data write / read cycle is executed as in the case of the state 1 in FIG. 4, the output signal 1a is accepted and the access identification signal 11a instructing the self-refresh of the memory is output to the memory control circuit 12. According to the access identification signal 11a, the memory control circuit 12 controls the volatile memory 7 at a timing defined by the self-refresh cycle of the control signal (RAS,
CAS) 12a is output.

State 4 in FIG. 4 is the case where the POWDWN signal 1a of the power supply voltage detecting means 1 is output at a high level at the rising edge when the power supply voltage is turned on, and the arbitration circuit 11 outputs the PO signal.
When the WDWN signal 1a is released, an access identification signal 11a for instructing the end of the self-refresh cycle of the volatile memory 7 is output to the memory control circuit 12. According to the access identification signal 11a, the memory control circuit 12 controls the control signals (RAS, CA) at the timing defined by the end of the self-refresh cycle of the volatile memory 7.
S) 12a is output.

According to the apparatus of the present embodiment described above, when the memory backup power is supplied and controlled by using the two secondary batteries 2 and 3, the secondary battery 2 is supplied when the power is on.
3 are connected in parallel, the charging circuit 5 can be charged from the same power source as the device including the volatile memory 7, and it is not necessary to separately provide a power source for charging.

Further, by connecting the secondary batteries 2 and 3 in series and supplying the backup power supply via the step-down circuit 6, the number of parts constituting the circuit is reduced and a low-loss memory backup control device is constructed. can do.

Furthermore, since the write / read timing of the volatile memory 7 is generated and the operation is switched under the control of the memory control circuit 12, even if the output signal 1a is generated during the data write / read cycle, the data write is performed. / It is possible to prevent data destruction without forcibly changing the cycle sequence without normally ending the read cycle. Moreover, since there is no overhead associated with the execution of the program due to the intervention of the CPU, the volatile memory 7 can be brought into the data holding state accurately and at high speed.

[0050]

According to the first aspect of the present invention, it is not necessary to separately provide a power source for charging, and when the power source voltage drops below a predetermined voltage, the secondary battery and the step-down circuit are used to access the memory. It is possible to provide a memory backup control device capable of surely performing backup of the above.

According to the second aspect of the present invention, even when the power supply voltage is lower than the predetermined voltage, the cycle sequence is not forcibly changed without normally ending the data write / read cycle, and the data is destroyed. It is possible to provide a memory backup control device that can prevent the above.

According to the third aspect of the present invention, there is provided a memory backup control device capable of accurately and rapidly putting a volatile memory into a data holding state without the overhead associated with program execution due to the intervention of a CPU. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment of a memory backup control device of the present invention.

FIG. 2 is a state diagram showing a switching state of the secondary battery of the present embodiment.

FIG. 3 is a timing chart showing the relationship between the change in the power supply voltage and the output signal of the power supply voltage detection means in this embodiment.

FIG. 4 is a timing chart showing access control of the volatile memory according to the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply voltage detection means 2, 3 Secondary battery 4 Connection switching means 5 Charging circuit 6 Step-down circuit 7 Volatile memory 9 Refresh cycle generation circuit 11 Arbitration circuit 12 Memory control circuit 15 Control means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H02J 9/06 503 A

Claims (3)

[Claims] 1. A memory, at least two secondary batteries, a power supply voltage detecting means for detecting a power supply voltage of the device, and a secondary battery when the power supply voltage detected by the power supply voltage detecting means is a predetermined voltage or more. A secondary battery is connected in parallel to perform charging, and when the voltage is lower than a predetermined voltage, the secondary battery is connected in series, and a connection switching unit that supplies backup power to the memory via a step-down circuit is provided. Memory backup controller. 2. A volatile memory having a self-refresh function for holding data by self-refreshing, at least two secondary batteries, a power supply voltage detecting means for detecting a power supply voltage of this device, and this power supply voltage. When the power supply voltage detected by the detection means is equal to or higher than a predetermined voltage, the secondary batteries are connected in parallel for charging, and when the power supply voltage is equal to or lower than the predetermined voltage, the secondary batteries are connected in series and the volatile voltage is supplied via a step-down circuit. Connection switching means for supplying backup power to the memory, and refresh cycle request means for sending a self-refresh request for activating self-refresh at backup when the power supply voltage detected by the power supply voltage detecting means falls below a predetermined voltage. In response to the self-refresh request from the refresh cycle requesting means, a plurality of processing units And a control means for prohibiting an access request to the volatile memory, arbitrating with the access request, and activating self-refresh of the volatile memory at the end of the memory cycle being executed. Memory backup controller. 3. A volatile memory having a self-refresh function for holding data by self-refreshing, at least two secondary batteries, a power supply voltage detecting means for detecting a power supply voltage of this device, and this power supply voltage. When the power supply voltage detected by the detection means is equal to or higher than a predetermined voltage, the secondary batteries are connected in parallel for charging, and when the power supply voltage is equal to or lower than the predetermined voltage, the secondary batteries are connected in series and the volatile voltage is supplied via a step-down circuit. Connection switching means for supplying backup power to the memory, and a self-refresh request for activating self-refresh at backup when the power supply voltage detected by the power supply voltage detection means falls below a predetermined voltage and power supply voltage detection A lift for canceling the self-refresh request when the power supply voltage detected by the means rises above a predetermined voltage. A refresh cycle requesting means, and a control means for permitting access requests to the volatile memory from a plurality of processing units at the end of the self-refreshing memory cycle accompanying release of the self-refresh request by the refresh cycle requesting means. A memory backup control device having.