JPH08139376A - Input coil for superconducting quantum interference device - Google Patents

Input coil for superconducting quantum interference device

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Publication number
JPH08139376A
JPH08139376A JP6307043A JP30704394A JPH08139376A JP H08139376 A JPH08139376 A JP H08139376A JP 6307043 A JP6307043 A JP 6307043A JP 30704394 A JP30704394 A JP 30704394A JP H08139376 A JPH08139376 A JP H08139376A
Authority
JP
Japan
Prior art keywords
thin film
superconducting thin
coil
superconducting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6307043A
Other languages
Japanese (ja)
Inventor
Isanori Sato
功紀 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP6307043A priority Critical patent/JPH08139376A/en
Publication of JPH08139376A publication Critical patent/JPH08139376A/en
Pending legal-status Critical Current

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  • Measuring Magnetic Variables (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE: To provide an input coil for a superconducting quantum interference device which has a multilayer structure with which the decline of a critical current caused by the existence of a local large slant angle grain boundary in a closed circuit composed of a superconducting thin films can be suppressed. CONSTITUTION: The turn part 22 of a superconducting thin film coil is buried under the surface of a substrate 11. An interlayer insulating film 24 is buried in a trench 14 which is formed under the surface of the coil 22 at the position where a superconducting thin film cross-connection wiring part 25 connected to the inner side coil end 25a crosses the coil 22. The superconducting thin film wiring part and the superconducting thin film cross-connection wiring part 25 are formed on the substrate surface of a region which is practically flat and which includes the surface of the interlayer insulating film 24.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、超電導量子干渉デバイ
ス用入力コイルに関するものであり、さらに詳しくは、
生体磁気測定、非破壊検査、鉱物資源探査などに利用さ
れる高感度磁界測定用の超電導量子干渉デバイス(SQ
UID)を構成するためのジョセフソン接合を含む超電
導リングに対して電磁結合されるように基板上に薄膜積
層構造として形成され、磁場検知用のピックアップコイ
ルと閉回路の磁束トランスを構成するように接続される
超電導薄膜コイルの構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input coil for a superconducting quantum interference device, and more specifically,
Superconducting quantum interference device (SQ) for high-sensitivity magnetic field measurement used for biomagnetic measurement, nondestructive inspection, mineral resource exploration, etc.
UID) is formed as a thin film laminated structure on a substrate so as to be electromagnetically coupled to a superconducting ring including a Josephson junction to form a magnetic field detecting pickup coil and a closed circuit magnetic flux transformer. The present invention relates to the structure of a superconducting thin film coil to be connected.

【0002】[0002]

【従来の技術】SQUIDは超電導リング配線の一部に
ジョセフソン接合を介在させて磁気信号を電気信号に変
換する素子であり、実用的には磁気信号のピックアップ
に磁束トランスが利用されている。磁束トランスは、全
て超電導体で構成された閉ループ内の磁束の総和が不変
であるという磁束保存の原理を利用したもので、ピック
アップコイルと入力コイルとの二つの超電導コイルで構
成された超電導閉回路を備え、入力コイルをSQUID
の主リングに近接配置して、前記閉回路を所定の相互イ
ンダクタンスでSQUIDに磁気結合している。この場
合、SQUID自体は感度の関係から大きさが限定さ
れ、通常その径は数十μmから大きくても百μmのオー
ダーである。
2. Description of the Related Art A SQUID is an element for converting a magnetic signal into an electric signal by interposing a Josephson junction in a part of a superconducting ring wiring, and a magnetic flux transformer is practically used for pickup of the magnetic signal. The magnetic flux transformer uses the principle of magnetic flux conservation that the total sum of magnetic flux in a closed loop composed of superconductors is invariable. A superconducting closed circuit composed of two superconducting coils, a pickup coil and an input coil. Equipped with a SQUID input coil
Is arranged close to the main ring of the SQUID and the closed circuit is magnetically coupled to the SQUID with a predetermined mutual inductance. In this case, the size of the SQUID itself is limited due to the sensitivity, and its diameter is usually several tens of μm to at most 100 μm.

【0003】それぞれ超電導コイルからなるピックアッ
プコイルと入力コイルのインダクタンスは互いに等しく
する必要があるが、ピックアップコイルは実際に磁気を
検知する部分であるから、通常約cm2 オーダーの比較
的大きな面積をもつ一方で、入力コイルは磁束伝達効率
の関係で前述のようなSQUID主リングと同じ程度の
比較的小さな面積としなければならず、従って入力コイ
ルは小さい面積で所要のインダクタンスを得るために必
然的に複数ターンの渦巻状コイルの形態を取らざるを得
ない。
It is necessary that the pickup coil and the input coil, each of which is a superconducting coil, have the same inductance, but since the pickup coil is the part that actually detects magnetism, it usually has a relatively large area of the order of about cm 2. On the other hand, the input coil must have a relatively small area of the same degree as the SQUID main ring described above in relation to the magnetic flux transmission efficiency, and therefore the input coil is inevitably required to obtain a required inductance in a small area. There is no choice but to take the form of a spiral coil with multiple turns.

【0004】従来の磁束トランスにおける入力コイルの
具体例を図3のA,B及び図4のA〜Cに示す。図3A
はIBM社で試作された7ターンの高温超電導体を用い
た入力コイル(B. Oh他; Applied Physics Letters, Vo
l.59(1), p.123-125; 1991)を示す拡大平面図であり、
図3BはそのB−B線矢視模式断面図である。また、図
4Aはカリフォルニア大学で試作された10ターンの高
温超電導体を用いた入力コイル(F.C.Wellstood他; Appl
ied Physics Letters, Vol.56(23), p.2336-2338;1990)
を示す拡大平面図であり、図4BおよびCはそれぞれ図
4AのB−BおよびC−C矢視模式断面図である。
Specific examples of the input coil in the conventional magnetic flux transformer are shown in A and B of FIG. 3 and A to C of FIG. Figure 3A
Is an input coil (B. Oh et al .; Applied Physics Letters, Vo) using a 7-turn high-temperature superconductor prototyped by IBM.
. l 59 (1), p.123-125 ; 1991) is an enlarged plan view showing a
FIG. 3B is a schematic sectional view taken along the line BB of FIG. In addition, FIG. 4A shows an input coil (FC Wellstood et al .; Appl;
ied Physics Letters, Vol. 56 (23), p.2336-2338; 1990)
4B and C are schematic cross-sectional views taken along arrows BB and CC in FIG. 4A, respectively.

【0005】図3に示す従来の入力コイルは高温超電導
体として YBa2Cu3OX(YBCO)を用いたものであり、図3に
おいて、基板31上に形成された渦巻状の超電導薄膜コ
イル32の内側コイル端32aは超電導薄膜クロス接続
配線35を介して一方の超電導薄膜配線33aに接続さ
れ、また外側コイル端32bはそれと一体形成された他
方の超電導薄膜配線33bに接続され、これら一対の超
電導薄膜配線33a,33bは図示しない1ターンの超
電導ピックアップコイルの両端に接続されて、これら二
つのコイルで閉回路の磁束トランスを形成することにな
る。
The conventional input coil shown in FIG. 3 uses YBa 2 Cu 3 O X (YBCO) as a high temperature superconductor. In FIG. 3, a spiral superconducting thin film coil 32 formed on a substrate 31 is used. Inner coil end 32a is connected to one superconducting thin film wiring 33a through a superconducting thin film cross connecting wiring 35, and outer coil end 32b is connected to the other superconducting thin film wiring 33b integrally formed therewith. The thin film wirings 33a and 33b are connected to both ends of a one-turn superconducting pickup coil (not shown), and these two coils form a closed-circuit magnetic flux transformer.

【0006】図4の場合も同様に、基板41上に形成さ
れた渦巻状の超電導薄膜コイル42の内側コイル端42
aは超電導薄膜クロス接続配線45を介して一方の超電
導薄膜配線43aに接続され、また外側コイル端42b
はそれと一体形成された他方の超電導薄膜配線43bに
接続され、これら一対の超電導薄膜配線43a,43b
は図示しない1ターンの超電導ピックアップコイルの両
端に接続されて、これら二つのコイルで閉回路の磁束ト
ランスを形成することになる。
Similarly in the case of FIG. 4, the inner coil end 42 of the spiral superconducting thin film coil 42 formed on the substrate 41 is also formed.
a is connected to one superconducting thin film wiring 43a through a superconducting thin film cross connection wiring 45, and also has an outer coil end 42b.
Is connected to the other superconducting thin film wiring 43b formed integrally with the superconducting thin film wiring 43b.
Is connected to both ends of a one-turn superconducting pickup coil (not shown), and these two coils form a closed-circuit magnetic flux transformer.

【0007】図3及び図4から明らかなように、コイル
32又は42が渦巻状である限り、一対の超電導薄膜配
線33a,33bまたは43a,43bの内の一方、即
ちコイル32または42の内側コイル端32aまたは4
2aと接続される超電導薄膜配線33aまたは43a
は、必ずコイルのターン部のパターンを径方向に交差す
る超電導薄膜クロス接続配線35または45によって内
側コイル端に接続されている。従って、ともに超電導薄
膜であるコイルターン部分と超電導薄膜クロス接続配線
との間を電気的に絶縁するために、これらの層間に絶縁
膜34または44を介在配置する必要がある。図3およ
び図4に示した入力コイルでは、この絶縁膜として形状
は異なるもののいずれもSrTiO3薄膜を用いている。
As is apparent from FIGS. 3 and 4, one of the pair of superconducting thin film wirings 33a, 33b or 43a, 43b, that is, the inner coil of the coil 32 or 42, as long as the coil 32 or 42 has a spiral shape. End 32a or 4
Superconducting thin film wiring 33a or 43a connected to 2a
Is always connected to the inner coil end by the superconducting thin film cross connection wiring 35 or 45 that crosses the turn pattern of the coil in the radial direction. Therefore, in order to electrically insulate the coil turn portion, which is a superconducting thin film, and the superconducting thin film cross connection wiring, it is necessary to interpose the insulating film 34 or 44 between these layers. In the input coils shown in FIGS. 3 and 4, SrTiO 3 thin films are used as the insulating film, although they have different shapes.

【0008】具体的な積層構造について述べると、図3
に示す入力コイルでは、基板31上に第1層目として形
成された超電導薄膜により、コイル32とその外側コイ
ル端32bに一体の一方の超電導薄膜配線33b,およ
び独立した他方の超電導薄膜配線33aが形成され、こ
の第1層目の上に積層される第2層目として絶縁膜34
が全面に形成され、更にこの第2層目の上に第3層目と
して形成された超電導薄膜により、コイル32の内側コ
イル端32aと超電導薄膜配線33aとの間を接続する
超電導薄膜クロス接続配線35が形成されている。
A specific laminated structure will be described with reference to FIG.
In the input coil shown in (1), the superconducting thin film formed as the first layer on the substrate 31 allows the coil 32 and the outer coil end 32b to be integrated into one superconducting thin film wiring 33b and the other independent superconducting thin film wiring 33a. The insulating film 34 is formed as a second layer to be laminated on the first layer.
Superconducting thin film cross connection wiring for connecting between the inner coil end 32a of the coil 32 and the superconducting thin film wiring 33a by a superconducting thin film formed as a third layer on the second layer. 35 is formed.

【0009】また、図4に示す入力コイルでは、上記と
逆に、基板41上に第1層目として形成された超電導薄
膜により、コイル42の内側コイル端42aと超電導薄
膜配線43aとの間を接続するための超電導薄膜クロス
接続配線45がまず先に形成され、この第1層目を上か
ら被覆するように限定された領域で基板41上に絶縁膜
44が形成される。従って絶縁膜44は第1層目の超電
導薄膜クロス接続配線45の上では第2層目となり、上
記限定領域内のそれ以外の基板面上では第1層目とな
る。そして更にこの絶縁膜44で覆われた限定領域を含
む基板の全面に形成された超電導薄膜により、前記超電
導薄膜クロス接続配線45と接続された一方の超電導薄
膜配線43a、内側コイル端42aを前記超電導薄膜ク
ロス接続配線45と接続した渦巻状のコイル42、及び
コイル42の外側コイル端42bと一体の他方の超電導
薄膜配線43bが形成されており、従って前記超電導薄
膜クロス接続配線45と交差する部分におけるコイル4
2のターン部分は第3層目となっている。
In the input coil shown in FIG. 4, contrary to the above, the superconducting thin film formed as the first layer on the substrate 41 causes the inner coil end 42a of the coil 42 and the superconducting thin film wiring 43a to be separated from each other. The superconducting thin film cross connection wiring 45 for connection is first formed, and then the insulating film 44 is formed on the substrate 41 in a limited region so as to cover the first layer from above. Therefore, the insulating film 44 becomes the second layer on the superconducting thin film cross connection wiring 45 of the first layer, and becomes the first layer on the other substrate surface in the limited region. Further, by the superconducting thin film formed on the entire surface of the substrate including the limited region covered with the insulating film 44, one superconducting thin film wiring 43a connected to the superconducting thin film cross connecting wiring 45 and the inner coil end 42a are connected to the superconducting thin film. The spiral coil 42 connected to the thin film cross connection wiring 45 and the other superconducting thin film wiring 43b integrated with the outer coil end 42b of the coil 42 are formed, and therefore, at the portion intersecting with the superconducting thin film cross connection wiring 45. Coil 4
The turn part of 2 is the third layer.

【0010】[0010]

【発明が解決しようとする課題】このような超電導薄膜
の積層構造では、いずれかの超電導薄膜が第1層目、第
2層目、第3層目などの互いに異なる高さレベルに亙っ
て延在する部分を含むことになるので、以下の通りの不
都合を生じる。
In such a laminated structure of superconducting thin films, any one of the superconducting thin films has different height levels such as the first layer, the second layer and the third layer. Since the extended portion is included, the following inconvenience occurs.

【0011】即ち、部分断面の積層構造に注目すると、
例えば図3に示す入力コイルでは、図3Bに示したよう
に第3層目の超電導薄膜クロス接続配線35が、第2層
目の絶縁膜34の表面上にコイルターンに応じて現れる
複数の凹凸に倣って、複数の段差をもつコルゲート状に
形成される。
That is, paying attention to the laminated structure of the partial cross section,
For example, in the input coil shown in FIG. 3, as shown in FIG. 3B, the third layer superconducting thin film cross-connecting wiring 35 has a plurality of irregularities appearing on the surface of the second layer insulating film 34 in accordance with coil turns. Following the above, it is formed in a corrugated shape having a plurality of steps.

【0012】また、図4に示す入力コイルでは、図4B
に示したようにコイル42を径方向に横切る絶縁膜44
の境界縁部分に現れる基板41と絶縁膜44との表面段
差をコイル42のターン部分が半周ごとに乗り越えるの
で、コイル42が全体でターン数の2倍だけ段差部分を
もつことになると共に、図4Cに示したように超電導薄
膜クロス接続配線45の部分で絶縁膜44の表面上に現
れる凸部の段差をコイル42のターン部分が毎ターンご
とに乗り越えるので、コイル42が全体でターン数だけ
同様の凸状段差部分をもつことになる。
In addition, in the input coil shown in FIG.
Insulating film 44 that crosses coil 42 in the radial direction as shown in FIG.
Since the turn portion of the coil 42 gets over the surface step between the substrate 41 and the insulating film 44 appearing at the boundary edge portion of the coil 42 every half turn, the coil 42 has a step portion as much as twice the number of turns, and As shown in FIG. 4C, the turn portion of the coil 42 overcomes the step difference of the convex portion appearing on the surface of the insulating film 44 at the portion of the superconducting thin film cross connection wiring 45, so that the coil 42 as a whole has the same number of turns. Will have a convex step.

【0013】ところで、上述のような入力コイルをペロ
ブスカイト構造の酸化物超電導体として知られる高温超
電導体によってスパッタリングなどの成膜技術で作成す
る場合、成膜された高温超電導体の薄膜が上述のような
段差を含んでいると、図5に模式的に示したように、超
電導薄膜52の段差部54においては、超電導薄膜の結
晶の成長方位が他の部分と異なってしまい、その結果、
大きな傾角の粒界が発生してしまうという問題が生じ
る。超電導薄膜による閉回路中にこのような部分的に傾
角の大きな粒界が介在すると、超電導状態で閉回路に流
れる臨界電流Icが減少してしまうことはよく知られた
ことであり、したがってSQUIDにおける磁束トラン
スを構成する入力トランスにおいては、閉回路形成のた
めの超電導薄膜中に局部的な大傾角粒界部分が介在する
とSQUIDの検出感度が低下する原因となる。
By the way, when the input coil as described above is formed by a film forming technique such as sputtering using a high temperature superconductor known as an oxide superconductor having a perovskite structure, the thin film of the formed high temperature superconductor is as described above. If such a step is included, as shown schematically in FIG. 5, in the step portion 54 of the superconducting thin film 52, the crystal growth direction of the superconducting thin film is different from other portions, and as a result,
There is a problem that grain boundaries with a large inclination angle are generated. It is well known that the presence of such a grain boundary having a large inclination angle in the closed circuit of the superconducting thin film reduces the critical current Ic flowing in the closed circuit in the superconducting state, and thus in SQUID. In the input transformer that constitutes the magnetic flux transformer, if a local high-angle grain boundary portion is present in the superconducting thin film for forming a closed circuit, it may cause a decrease in SQUID detection sensitivity.

【0014】ちなみに、図3に示した入力コイルは高温
超電導体として YBa2Cu3OX(YBCO)を用い、層間絶縁膜に
SrTiO3を用いており、臨界温度Tcは84Kであるが、
臨界電流は77Kにおいて0.18mAと低く、また図
4に示した入力コイルも高温超電導体としてYBCOを用
い、層間絶縁膜にSrTiO3を用いており、臨界温度Tcは
82Kであるが、臨界電流は77Kにおいて1.4mA
と未だ不十分であるとされている。
By the way, the input coil shown in FIG. 3 uses YBa 2 Cu 3 O X (YBCO) as a high temperature superconductor and has an interlayer insulating film.
Although SrTiO 3 is used and the critical temperature Tc is 84K,
The critical current is as low as 0.18 mA at 77K, and the input coil shown in Fig. 4 also uses YBCO as the high temperature superconductor and SrTiO 3 for the interlayer insulating film, and the critical temperature Tc is 82K. 1.4 mA at 77K
And it is said that it is still insufficient.

【0015】したがって本発明の課題は、ペロブスカイ
ト構造の酸化物超電導体として知られる高温超電導体に
よってスパッタリングなどの成膜技術で作成する場合で
あっても超電導薄膜中に局部的な大傾角粒界部を形成す
ることを極力防止でき、従って超電導薄膜による閉回路
中に局部的な大傾角粒界が介在することによる臨界電流
の低下を抑止することのできる積層構造をもった超電導
量子干渉デバイス用入力コイルを提供することである。
Therefore, an object of the present invention is to provide a local high-angle grain boundary part in a superconducting thin film even when it is formed by a film-forming technique such as sputtering using a high-temperature superconductor known as an oxide superconductor having a perovskite structure. Input for a superconducting quantum interference device with a layered structure that can prevent the formation of grains as much as possible, and thus can suppress the reduction of the critical current due to the presence of a local high-angle grain boundary in the closed circuit of the superconducting thin film. Is to provide a coil.

【0016】[0016]

【課題を解決するための手段】請求項1の発明による超
電導量子干渉デバイス用入力コイルは、超電導量子干渉
デバイスを構成するためのジョセフソン接合を含む超電
導リングに対して磁気結合されるように基板上に薄膜積
層構造として形成され、磁場検知用のピックアップコイ
ルと超電導閉回路の磁束トランスを構成するように接続
される入力コイルであり、この入力コイルは、複数ター
ンの渦巻状の超電導薄膜コイルと、超電導薄膜コイルの
外側コイル端とピックアップコイルの一端との接続のた
めの超電導薄膜配線部と、超電導薄膜コイルの内側コイ
ル端とピックアップコイルの他端との接続のために超電
導薄膜コイルの内側コイル端から超電導薄膜コイルのタ
ーン部を径方向に横切っている超電導薄膜クロス接続配
線部と、この超電導薄膜クロス接続配線部と超電導薄膜
コイルのターン部との間を絶縁する層間絶縁膜とを備え
ている。
An input coil for a superconducting quantum interference device according to a first aspect of the present invention is a substrate to be magnetically coupled to a superconducting ring including a Josephson junction for forming a superconducting quantum interference device. An input coil that is formed as a thin film laminated structure on the top and is connected so as to form a magnetic field detection pickup coil and a magnetic flux transformer of a superconducting closed circuit. This input coil is a spiral superconducting thin film coil with a plurality of turns. , A superconducting thin film wiring part for connecting the outer coil end of the superconducting thin film coil and one end of the pickup coil, and an inner coil of the superconducting thin film coil for connecting the inner coil end of the superconducting thin film coil and the other end of the pickup coil The superconducting thin film cross connection wiring part that crosses the turn part of the superconducting thin film coil from the end in the radial direction, and And an interlayer insulating film for insulating between the thin film cross connection wiring portion and the turn portions of the superconducting thin film coil.

【0017】本発明による入力コイルでは、特に前述の
課題を解決するために、超電導薄膜コイルのターン部は
基板の表面下に形成された第1の溝内に埋設され、また
層間絶縁膜は、超電導クロス接続配線部と超電導薄膜コ
イルのターン部とが重なる部位において超電導薄膜コイ
ルのターン部の表面下に形成された第2の溝内に埋設さ
れ、前記超電導薄膜コイルのターン部の表面と層間絶縁
膜の表面とを含む領域の実質的に平坦な基板表面上に、
超電導薄膜配線部及び超電導薄膜クロス接続配線部とが
形成されている。
In the input coil according to the present invention, in order to solve the above-mentioned problems, the turn portion of the superconducting thin film coil is buried in the first groove formed below the surface of the substrate, and the interlayer insulating film is It is embedded in a second groove formed below the surface of the turn portion of the superconducting thin-film coil at a portion where the superconducting cross-connect wiring portion and the turn portion of the superconducting thin-film coil overlap, and the surface of the turn portion of the superconducting thin-film coil and the interlayer On the substantially flat substrate surface in the region including the surface of the insulating film,
A superconducting thin film wiring portion and a superconducting thin film cross connecting wiring portion are formed.

【0018】また請求項2の発明による超電導量子干渉
デバイス用入力コイルでは、請求項1の発明の特徴に加
えて、超電導薄膜コイルの内側コイル端と超電導薄膜ク
ロス接続配線部との接続部及び超電導薄膜コイルの外側
コイル端と超電導薄膜配線部との接続部の双方の接続部
の表面が層間絶縁膜の表面と共に基板の表面と同一位置
レベルの平面上にあり、この平面上に形成された単一の
平坦な超電導薄膜層から超電導薄膜配線部及び超電導薄
膜クロス接続配線部とが形成されている。
Further, in the input coil for a superconducting quantum interference device according to a second aspect of the present invention, in addition to the features of the first aspect of the invention, a connecting portion between the inner coil end of the superconducting thin film coil and the superconducting thin film cross connecting wiring portion and the superconducting The surfaces of both the outer coil end of the thin-film coil and the connection between the superconducting thin-film wiring part and the surface of the interlayer insulating film are on the same level as the surface of the substrate along with the surface of the interlayer insulating film. A superconducting thin film wiring portion and a superconducting thin film cross connecting wiring portion are formed from one flat superconducting thin film layer.

【0019】更に請求項3の発明による超電導量子干渉
デバイス用入力コイルは、超電導量子干渉デバイスを構
成するためのジョセフソン接合を含む超電導リングに対
して磁気結合されるように基板上に薄膜積層構造として
形成され、磁場検知用のピックアップコイルと超電導閉
回路の磁束トランスを構成するように接続される入力コ
イルであり、この入力コイルは、複数ターンの渦巻状の
超電導薄膜コイルと、超電導薄膜コイルの外側コイル端
とピックアップコイルの一端との接続のための第1の超
電導薄膜配線部と、超電導薄膜コイルの内側コイル端と
ピックアップコイルの他端との接続のための第2の超電
導薄膜配線部と、超電導薄膜コイルの内側コイル端から
超電導薄膜コイルのターン部を径方向に横切って第2の
超電導薄膜配線部に達する超電導薄膜クロス接続配線部
と、超電導薄膜クロス接続配線部と超電導薄膜コイルの
ターン部との間を絶縁する層間絶縁膜とを備えている。
Further, the input coil for a superconducting quantum interference device according to the invention of claim 3 is a thin film laminated structure on a substrate so as to be magnetically coupled to a superconducting ring including a Josephson junction for constructing the superconducting quantum interference device. Is an input coil connected to form a pickup coil for magnetic field detection and a magnetic flux transformer of a superconducting closed circuit, and the input coil is composed of a spiral superconducting thin film coil having a plurality of turns and a superconducting thin film coil. A first superconducting thin film wiring portion for connecting the outer coil end and one end of the pickup coil, and a second superconducting thin film wiring portion for connecting the inner coil end of the superconducting thin film coil and the other end of the pickup coil. A second superconducting thin-film wiring part that radially crosses the turn part of the superconducting thin-film coil from the inner coil end of the superconducting thin-film coil A superconducting thin cross connection wiring portion reaching, and an interlayer insulating film for insulating between the superconducting thin cross connection wiring portion and the turn portions of the superconducting thin film coil.

【0020】本発明による入力コイルでは、特に前述の
課題を解決するために、超電導薄膜クロス接続配線部は
超電導薄膜コイルのターン部を横切る部位において基板
の表面下に形成された第1の溝内に埋設され、また層間
絶縁膜は、超電導薄膜コイルの内側コイル端と第2の超
電導薄膜配線部とに対する超電導薄膜クロス接続配線部
の各接続部を除く部位において超電導薄膜クロス接続配
線部の表面下に形成された第2の溝内に埋設され、前記
各接続部の表面と層間絶縁膜の表面とを含む領域の実質
的に平坦な基板表面上に、超電導薄膜コイルと第1の超
電導薄膜配線部及び第2の超電導薄膜配線部とが形成さ
れている。
In the input coil according to the present invention, in order to solve the above-mentioned problems, the superconducting thin film cross connecting wiring portion is formed in the first groove formed below the surface of the substrate at the portion crossing the turn portion of the superconducting thin film coil. And the interlayer insulating film is under the surface of the superconducting thin film cross connecting wiring part at a portion except for each connecting part of the superconducting thin film cross connecting wiring part to the inner coil end of the superconducting thin film coil and the second superconducting thin film wiring part. A superconducting thin film coil and a first superconducting thin film wiring, which are buried in the second groove formed on the substrate, and are formed on the substantially flat substrate surface in the region including the surfaces of the connection portions and the surface of the interlayer insulating film. And a second superconducting thin film wiring portion are formed.

【0021】更にまた請求項4の発明による超電導量子
干渉デバイス用入力コイルでは、請求項3の発明に加え
て、超電導薄膜コイルの内側コイル端と第2の超電導薄
膜配線部とに対する超電導薄膜クロス接続配線部の各接
続部の表面が層間絶縁膜の表面と共に基板の表面と同一
位置レベルの平面上にあり、この平面上に形成された単
一の平坦な超電導薄膜層から超電導薄膜コイルと第1の
超電導薄膜配線部及び第2の超電導薄膜配線部とが形成
されている。
Further, in the input coil for a superconducting quantum interference device according to the invention of claim 4, in addition to the invention of claim 3, the superconducting thin film cross connection to the inner coil end of the superconducting thin film coil and the second superconducting thin film wiring part is provided. The surface of each connection part of the wiring part is on the same level as the surface of the substrate together with the surface of the interlayer insulating film, and from the single flat superconducting thin film layer formed on this plane to the superconducting thin film coil and the first superconducting thin film coil. A superconducting thin film wiring part and a second superconducting thin film wiring part.

【0022】[0022]

【作用】以上のような薄膜積層構造を持つ本願発明によ
る超電導量子干渉デバイス用入力コイルは、ペロブスカ
イト構造の酸化物超電導体として知られる高温超電導体
によってスパッタリング等の成膜技術で作成することが
でき、しかもその場合、高温超電導薄膜の成膜に際して
凹凸や段差のある表面上に成膜する工程を一切なくすこ
とができる。
The input coil for a superconducting quantum interference device according to the present invention having the above-described thin film laminated structure can be formed by a film forming technique such as sputtering using a high temperature superconductor known as an oxide superconductor having a perovskite structure. Moreover, in that case, it is possible to eliminate the step of forming a film on the surface having irregularities or steps when forming the high temperature superconducting thin film.

【0023】すなわち、請求項1の発明による薄膜積層
構造は、例えば次のような成膜プロセスによって形成す
ることができる。まず始めに、基板の表面に超電導薄膜
コイル部を埋設するための第1の溝がフォトリソグラフ
ィ手法によって設けられる。この第1の溝の開口形状
は、予め定められた超電導薄膜コイル部の輪郭形状に応
じてリソグラフィのマスク開口により画定され、また第
1の溝の深さは、予め定められた超電導薄膜コイル部の
厚さと層間絶縁膜の厚さの和に相当するようにエッチン
グにより定められ、このようにして、平坦な底面を持つ
第1の溝が形成される。
That is, the thin film laminated structure according to the invention of claim 1 can be formed by, for example, the following film forming process. First, a first groove for burying the superconducting thin film coil portion is provided on the surface of the substrate by a photolithography method. The opening shape of the first groove is defined by a mask opening of lithography according to a predetermined contour shape of the superconducting thin film coil portion, and the depth of the first groove is predetermined. Is determined by etching so as to correspond to the sum of the thickness and the thickness of the interlayer insulating film, and thus the first groove having a flat bottom surface is formed.

【0024】第1の溝が形成された後、第1の溝内を含
めて基板表面には第1層目の成膜として全面に高温超電
導薄膜が成膜される。この成膜の厚さは第1の溝の深さ
と同等であり、これにより第1の溝内が高温超電導薄膜
で埋められることになる。第1の溝内の高温超電導薄膜
を残して、その他の基板表面上の高温超電導薄膜は基板
表面と同じ位置レベルまでエッチングにより除去され
る。これにより第1の溝内を埋めて残された高温超電導
薄膜の粒界は、第1の溝の平坦な底面上に成膜されてい
るので溝底面に平行であり、その傾角は一様にほぼ零で
ある。
After forming the first groove, a high-temperature superconducting thin film is formed on the entire surface of the substrate including the inside of the first groove as a first layer. The thickness of this film formation is equivalent to the depth of the first groove, whereby the inside of the first groove is filled with the high temperature superconducting thin film. The high temperature superconducting thin film on the other substrate surface is etched away to the same level as the substrate surface, leaving the high temperature superconducting thin film in the first groove. As a result, the grain boundaries of the high-temperature superconducting thin film left in the first groove are parallel to the groove bottom because they are formed on the flat bottom surface of the first groove, and the inclination angle is uniform. It is almost zero.

【0025】次いで、第1の溝内を埋めて残された高温
超電導薄膜の表面に層間絶縁膜を形成するための第2の
溝がフォトリソグラフィ手法によって設けられる。この
第2の溝は、超電導薄膜コイルのターン部と超電導薄膜
クロス接続配線部とが交差する部位について、ターンの
周方向に多少余裕をもって広げた面積に相当する部分を
エッチングによって除去することにより形成され、その
エッチング深さは層間絶縁膜の設計深さと同等である。
これにより残された高温超電導薄膜が超電導薄膜コイル
のターン部を形成することになる。
Then, a second groove for forming an interlayer insulating film is provided on the surface of the high temperature superconducting thin film left in the first groove by photolithography. The second groove is formed by removing, by etching, a portion corresponding to an area of the turn portion of the superconducting thin-film coil and the superconducting thin-film cross-connecting wiring portion which are widened with some margin in the circumferential direction of the turn. The etching depth is equal to the design depth of the interlayer insulating film.
The high temperature superconducting thin film thus left forms the turn portion of the superconducting thin film coil.

【0026】このようにして形成された第2の溝内を含
めて基板表面には第2層目の成膜として全面に絶縁膜が
成膜される。この絶縁膜の成膜厚さは第2の溝の深さと
同等であり、これにより第2の溝内が絶縁膜で埋められ
ることになる。第2の溝内の絶縁膜を残して、その他の
基板表面上の絶縁膜は基板表面と同じ位置レベルまでエ
ッチングにより除去される。これにより残された絶縁膜
が層間絶縁膜を構成することになる。
An insulating film is formed on the entire surface of the substrate including the inside of the thus formed second groove as a second layer. The film thickness of this insulating film is equal to the depth of the second groove, and the inside of the second groove is thereby filled with the insulating film. The other insulating films on the substrate surface are removed by etching to the same level as the substrate surface, leaving the insulating film in the second groove. The insulating film thus left constitutes the interlayer insulating film.

【0027】以上のプロセスにより、層間絶縁膜の表面
と、超電導薄膜コイルの内側コイル端と超電導薄膜クロ
ス接続配線部との接続部及び超電導薄膜コイルの外側コ
イル端と超電導薄膜配線部との接続部の双方の接続部の
表面とが基板表面上に面一の状態で現れることになり、
従ってこの平坦な表面上の全面に第3層目の成膜として
高温超電導薄膜が成膜される。このときの成膜厚さは超
電導薄膜配線部及び超電導薄膜クロス接続配線部に必要
な設計厚さであり、また成膜面が平坦であるので高温超
電導薄膜の粒界は平坦な成膜面に平行であり、その傾角
は一様にほぼ零である。
By the above process, the surface of the interlayer insulating film, the connecting portion between the inner coil end of the superconducting thin film coil and the superconducting thin film cross connecting wiring portion, and the connecting portion between the outer coil end of the superconducting thin film coil and the superconducting thin film wiring portion. The surface of both connection parts of will appear flush with the surface of the substrate,
Therefore, a high-temperature superconducting thin film is formed as a third layer on the entire surface of this flat surface. The film thickness at this time is the design thickness required for the superconducting thin film wiring part and the superconducting thin film cross connecting wiring part, and since the film forming surface is flat, the grain boundaries of the high temperature superconducting thin film should be flat. They are parallel, and their tilt angles are almost zero.

【0028】最後に第3層目の高温超電導薄膜がリソグ
ラフィ手法によってパターニングされ、超電導薄膜クロ
ス接続配線部及び超電導薄膜配線部がそれぞれ所定の位
置及び形状に形成される。
Finally, the high-temperature superconducting thin film of the third layer is patterned by a lithographic method to form the superconducting thin film cross connecting wiring portion and the superconducting thin film wiring portion at predetermined positions and shapes.

【0029】また、請求項3の発明による薄膜積層構造
は、例えば次のような成膜プロセスによって形成するこ
とができる。まず始めに、基板の表面に超電導薄膜クロ
ス接続配線部を埋設するための第1の溝がフォトリソグ
ラフィ手法によって設けられる。この第1の溝の開口形
状は、予め定められた超電導薄膜クロス接続配線部の輪
郭形状に応じてリソグラフィのマスク開口により画定さ
れ、また第1の溝の深さは、予め定められた超電導薄膜
クロス接続配線部の厚さと層間絶縁膜の厚さの和に相当
するようにエッチングにより定められ、このようにして
平坦な底面を持つ第1の溝が形成される。
The thin film laminated structure according to the invention of claim 3 can be formed by, for example, the following film forming process. First, a first groove for embedding the superconducting thin film cross connecting wiring portion is provided on the surface of the substrate by a photolithography method. The opening shape of the first groove is defined by a mask opening of lithography according to a predetermined contour shape of the superconducting thin film cross connecting wiring portion, and the depth of the first groove is determined by the predetermined superconducting thin film. The first groove having a flat bottom surface is formed by etching so as to correspond to the sum of the thickness of the cross connection wiring portion and the thickness of the interlayer insulating film.

【0030】第1の溝が形成された後、第1の溝内を含
めて基板表面には第1層目の成膜として全面に高温超電
導薄膜が成膜される。この成膜の厚さは第1の溝の深さ
と同等であり、これにより第1の溝内が高温超電導薄膜
で埋められることになる。第1の溝内の高温超電導薄膜
を残して、その他の基板表面上の高温超電導薄膜は基板
表面と同じ位置レベルまでエッチングにより除去され
る。これにより第1の溝内を埋めて残された高温超電導
薄膜の粒界は、第1の溝の平坦な底面上に成膜されてい
るので溝底面に平行であり、その傾角は一様にほぼ零で
ある。
After the first groove is formed, a high temperature superconducting thin film is formed on the entire surface of the substrate including the inside of the first groove as a first layer. The thickness of this film formation is equivalent to the depth of the first groove, whereby the inside of the first groove is filled with the high temperature superconducting thin film. The high temperature superconducting thin film on the other substrate surface is etched away to the same level as the substrate surface, leaving the high temperature superconducting thin film in the first groove. As a result, the grain boundaries of the high-temperature superconducting thin film left in the first groove are parallel to the groove bottom because they are formed on the flat bottom surface of the first groove, and the inclination angle is uniform. It is almost zero.

【0031】次いで、第1の溝内を埋めて残された高温
超電導薄膜の表面に層間絶縁膜を形成するための第2の
溝がフォトリソグラフィ手法によって設けられる。この
第2の溝は、超電導薄膜コイルの内側コイル端と第2の
超電導薄膜配線部とに対する超電導薄膜クロス接続配線
部の各接続部を除く部位をエッチングによって除去する
ことにより形成され、そのエッチング深さは層間絶縁膜
の設計深さと同等である。これにより残された高温超電
導薄膜が超電導薄膜クロス接続配線部を構成することに
なる。
Then, a second groove for forming an interlayer insulating film is provided on the surface of the high temperature superconducting thin film left in the first groove by photolithography. The second groove is formed by removing a portion of the superconducting thin film cross connecting wiring portion other than each connection portion with respect to the inner coil end of the superconducting thin film coil and the second superconducting thin film wiring portion by etching, and the etching depth thereof. The thickness is equal to the design depth of the interlayer insulating film. The high temperature superconducting thin film left by this constitutes the superconducting thin film cross connecting wiring portion.

【0032】このようにして形成された第2の溝内を含
めて基板表面には第2層目の成膜として全面に絶縁膜が
成膜される。この絶縁膜の成膜厚さは第2の溝の深さと
同等であり、これにより第2の溝内が絶縁膜で埋められ
ることになる。第2の溝内の絶縁膜を残して、その他の
基板表面上の絶縁膜は基板表面と同じ位置レベルまでエ
ッチングにより除去される。これにより残された絶縁膜
が層間絶縁膜を構成することになる。
An insulating film is formed on the entire surface of the substrate, including the inside of the thus formed second groove, as the second layer. The film thickness of this insulating film is equal to the depth of the second groove, and the inside of the second groove is thereby filled with the insulating film. The other insulating films on the substrate surface are removed by etching to the same level as the substrate surface, leaving the insulating film in the second groove. The insulating film thus left constitutes the interlayer insulating film.

【0033】以上のプロセスにより、層間絶縁膜の表面
と、超電導薄膜コイルの内側コイル端と第2の超電導薄
膜配線部とに対する超電導薄膜クロス接続配線部の各接
続部の表面とが基板表面上に面一の状態で現れることに
なり、従ってこの平坦な表面上の全面に第3層目の成膜
として高温超電導薄膜が成膜される。このときの成膜厚
さは超電導薄膜コイルと第1及び第2の超電導薄膜配線
部に必要な設計厚さであり、また成膜面が平坦であるの
で高温超電導薄膜の粒界は平坦な成膜面に平行であり、
その傾角は一様にほぼ零である。
By the above process, the surface of the interlayer insulating film and the surface of each connecting portion of the superconducting thin film cross connecting wiring portion to the inner coil end of the superconducting thin film coil and the second superconducting thin film wiring portion are formed on the substrate surface. Therefore, a high temperature superconducting thin film is formed as a third layer on the entire surface of the flat surface. The film-forming thickness at this time is a design thickness required for the superconducting thin-film coil and the first and second superconducting thin-film wiring portions, and since the film-forming surface is flat, the grain boundaries of the high-temperature superconducting thin film are flat. Parallel to the membrane plane,
Its tilt angle is almost zero.

【0034】最後に第3層目の高温超電導薄膜がリソグ
ラフィ手法によってパターニングされ、超電導薄膜コイ
ルと第1及び第2の超電導薄膜配線部がそれぞれ所定の
位置及び形状に形成される。
Finally, the high-temperature superconducting thin film of the third layer is patterned by a lithographic method to form the superconducting thin-film coil and the first and second superconducting thin-film wiring portions at predetermined positions and shapes.

【0035】以上のように、請求項1または請求項3の
発明による入力コイルは、いずれも超電導薄膜の成膜を
全て実質的に平坦な面に対して行うことができる薄膜積
層構造を備えており、したがって一般的なスパッタリン
グ等の成膜技術を利用して酸化物超電導体などの高温超
電導体により成膜した場合であっても、超電導薄膜中に
局部的な大傾角粒界部が形成されることがない。
As described above, each of the input coils according to the invention of claim 1 or 3 has a thin film laminated structure capable of forming a superconducting thin film on a substantially flat surface. Therefore, even when a film is formed by a high-temperature superconductor such as an oxide superconductor using a general film forming technique such as sputtering, a local high-angle grain boundary is formed in the superconducting thin film. Never.

【0036】このため、本願発明による入力コイルで構
成した磁束トランスの閉回路には十分に大きな臨界電流
を流すことができ、SQUIDの感度を従来よりも飛躍
的に高めることが可能になる。
Therefore, a sufficiently large critical current can be passed through the closed circuit of the magnetic flux transformer constituted by the input coil according to the present invention, and the sensitivity of the SQUID can be remarkably increased as compared with the conventional case.

【0037】尚、請求項1または3の発明によれば、上
述の第3層目の成膜において高温超電導薄膜を形成すべ
き成膜面は厳密に面一の平坦面でなくてもよく、閉回路
に流れる臨界電流の低下に関して許容される程度の粒界
傾角を生じるに過ぎないような比較的小規模の凹凸や段
差を含んでいても実用上は差し支えない。
According to the invention of claim 1 or 3, the film-forming surface on which the high-temperature superconducting thin film is to be formed in the film formation of the above-mentioned third layer does not have to be exactly a flat surface. It may be practically acceptable to include a relatively small-scale unevenness or a level difference that only causes an allowable grain boundary tilt angle with respect to the reduction of the critical current flowing in the closed circuit.

【0038】但し、請求項2または4の発明によれば、
上述の第3層目の成膜において高温超電導薄膜を形成す
べき成膜面は厳密に面一の平坦面にすることができ、従
ってこの第3層目の成膜による高温超電導薄膜中には粒
界傾角が局部的に変化する部分はほとんど含まれること
がなく、入力コイルにおける臨界電流の低下は実質的に
発生しない。
However, according to the invention of claim 2 or 4,
The film-forming surface on which the high-temperature superconducting thin film should be formed in the above-mentioned third layer film formation can be made exactly flush with the flat surface. A portion where the grain boundary tilt angle locally changes is hardly included, and the reduction of the critical current in the input coil does not substantially occur.

【0039】本発明の薄膜積層構造における超電導薄膜
の形成に利用可能な高温超電導体としては、例えばYBa2
Cu3OX (YBCO)、Bi2Sr2Ca2Cu3OX、Bi2Sr2Ca1Cu2OX (BSCC
O)、Tl2Ba2Ca2Cu3OX (TBCCO)など、種々の酸化物超電導
材料を挙げることができ、また、基板および層間絶縁膜
の材料としては、例えば、 MgOや、SrTiO3、LaAlO3など
のペロブスカイト型構造を有する、酸化物超電導材料と
格子定数が類似して互いにエピタキシャル成長が可能な
材料を挙げることができる。
As a high temperature superconductor that can be used for forming a superconducting thin film in the thin film laminated structure of the present invention, for example, YBa 2
Cu 3 O X (YBCO), Bi 2 Sr 2 Ca 2 Cu 3 O X , Bi 2 Sr 2 Ca 1 Cu 2 O X (BSCC
O), Tl 2 Ba 2 Ca 2 Cu 3 O X (TBCCO), and other various oxide superconducting materials, and examples of the material of the substrate and the interlayer insulating film include MgO and SrTiO 3 , A material having a perovskite structure such as LaAlO 3 and having a lattice constant similar to that of the oxide superconducting material and capable of epitaxial growth with each other can be mentioned.

【0040】[0040]

【実施例】【Example】

=第1実施例= 本発明の第1実施例に係る超電導量子干渉デバイス用入
力コイルについて、その薄膜積層構造を成膜プロセスの
順を追って図1及び図2に示す。即ち、図1A〜Hは以
下に述べる成膜プロセスの工程A〜Hの順に示した模式
平面図、図2A〜Hは同様に図1に対応して工程A〜H
の順に示した模式断面図である。
= First Example = A thin film laminated structure of an input coil for a superconducting quantum interference device according to a first example of the present invention is shown in FIGS. 1 and 2 in the order of a film forming process. That is, FIGS. 1A to H are schematic plan views showing the steps A to H of the film forming process described below in order, and FIGS. 2A to H similarly correspond to FIG.
It is a schematic cross section shown in the order of.

【0041】(工程A)MgO(100)単結晶からなる基板1
1の表面にスピンコータによってフォトレジストを塗布
し、基板11の表面を厚さ0.5μmのフォトレジスト
層で全面被覆したのち、予め予定された超電導薄膜コイ
ルのターン部の平面形状に対応するマスクパターンのフ
ォトマスクを用いてレジストの露光を行い、アルカリ現
像液を用いてレジストを現像した。これにより超電導薄
膜コイルのターン部の平面形状と同じ形状の開口がレジ
スト層に形成された。次いでこの開口から露出する部分
の基板表面に対してアルゴンによるイオンビームエッチ
ングを行い、超電導薄膜コイルのターン部の平面形状と
同じ開口形状で平坦な底面をもつ深さ0.4μmの溝1
2を、基板11の所定位置に形成した(図1A及び図2
A)。
(Step A) Substrate 1 made of MgO (100) single crystal
A photoresist is applied to the surface of 1 by a spin coater and the surface of the substrate 11 is entirely covered with a photoresist layer having a thickness of 0.5 μm. Then, a mask pattern corresponding to a plan shape of a turn portion of a superconducting thin-film coil which is previously planned. The resist was exposed using the photomask of No. 1 and the resist was developed using an alkali developing solution. As a result, an opening having the same shape as the planar shape of the turn portion of the superconducting thin film coil was formed in the resist layer. Next, ion beam etching with argon is performed on the substrate surface of the portion exposed from this opening to form a groove 1 having a flat bottom surface with the same opening shape as that of the turn portion of the superconducting thin film coil and having a depth of 0.4 μm
2 is formed at a predetermined position on the substrate 11 (see FIGS. 1A and 2).
A).

【0042】(工程B)工程Aで溝12が形成された基
板11を高周波マグネトロンスパッタ装置にセットし、
第1層目の成膜としてYBCO薄膜13を全面に0.4μm
の厚さで成長させた。このときの成膜条件は、基板11
を700℃に加熱し、スパッタガスとしてアルゴンと酸
素の1:1の混合ガスを導入し、全ガス圧は150mTo
rr、ターゲットにはYBCO焼結体を用い、成膜時間は
4時間とした。これにより溝12がちょうど開口縁まで
YBCO薄膜で埋められ、溝12の周囲の基板表面には0.
4μm厚のYBCO薄膜が積層された(図1B及び図2
B)。
(Step B) The substrate 11 having the groove 12 formed in the step A is set in a high frequency magnetron sputtering apparatus,
A YBCO thin film 13 is formed on the entire surface to form a first layer of 0.4 μm.
Grown to a thickness of. The film forming conditions at this time are the substrate 11
Is heated to 700 ° C., a 1: 1 mixed gas of argon and oxygen is introduced as a sputtering gas, and the total gas pressure is 150 mTo.
rr, a YBCO sintered body was used as the target, and the film formation time was 4 hours. This allows the groove 12 to reach the opening edge.
It is filled with YBCO thin film.
A 4 μm thick YBCO thin film was laminated (FIGS. 1B and 2).
B).

【0043】(工程C)工程Bで得られた基板11のYB
CO薄膜13上にスピンコータによってフォトレジストを
塗布し、YBCO薄膜13の表面を厚さ0.5μmのフォト
レジスト層で全面被覆したのち、工程Aで使用したのと
相補的なマスクパターンのフォトマスクを用いてレジス
トの露光を行い、アルカリ現像液を用いてレジストを現
像した。これにより、YBCO薄膜13の下層にある溝12
に合致する部分を残してレジスト層が除去された。次い
でこの除去部分に露出する0.4μm厚のYBCO薄膜をア
ルゴンによるイオンビームエッチングで除去した。この
ときのエッチング時間は40分程度であった。その後、
剥離液を用いて残存レジストを除去したところ、溝12
内を埋めているYBCO薄膜13は超電導薄膜コイルのター
ン部22となり、また超電導薄膜コイルの内側コイル端
と超電導薄膜クロス接続配線部との接続部25a及び超
電導薄膜コイルの外側コイル端と超電導薄膜配線部との
接続部23aは、その周囲の基板11の表面と同一の位
置レベルとなり、面一の平坦な表面が形成された(図1
C及び図2C)。
(Step C) YB of the substrate 11 obtained in Step B
A photoresist is coated on the CO thin film 13 by a spin coater, and the surface of the YBCO thin film 13 is entirely covered with a photoresist layer having a thickness of 0.5 μm. Then, a photomask having a mask pattern complementary to that used in the step A is formed. Was used to expose the resist, and the resist was developed using an alkaline developer. As a result, the groove 12 under the YBCO thin film 13 is formed.
The resist layer was removed, leaving a portion corresponding to. Next, the 0.4 μm-thick YBCO thin film exposed at this removed portion was removed by ion beam etching with argon. The etching time at this time was about 40 minutes. afterwards,
When the residual resist was removed using a stripping solution, the groove 12
The YBCO thin film 13 filling the inside becomes the turn part 22 of the superconducting thin film coil, the connecting part 25a between the inner coil end of the superconducting thin film coil and the superconducting thin film cross connecting wiring part, and the outer coil end of the superconducting thin film coil and the superconducting thin film wiring. The connection portion 23a with the portion is at the same level as the surface of the substrate 11 around it, and a flush surface is formed (FIG. 1).
C and FIG. 2C).

【0044】(工程D)工程Cで溝12内を超電導薄膜
コイルのターン部22で埋めた基板11の表面にスピン
コータによってフォトレジストを塗布し、基板11の表
面を厚さ0.5μmのフォトレジスト層で全面被覆した
のち、予め予定された層間絶縁膜の平面形状に対応する
マスクパターンのフォトマスクを用いてレジストの露光
を行い、アルカリ現像液を用いてレジストを現像した。
これにより層間絶縁膜の平面形状と同じ形状の開口が溝
12内の超電導薄膜コイルのターン部22上のレジスト
層に形成された。次いでこの開口から露出する部分の超
電導薄膜コイルのターン部22の表面に対してアルゴン
によるイオンビームエッチングを約20分間に亘って行
った。その後、剥離液を用いて残存レジストを除去した
ところ、溝12内の超電導薄膜コイルのターン部22の
表面の所定位置に、層間絶縁膜の平面形状と同じ開口形
状をもつ深さ0.2μmの別の溝14が形成された(図
1D及び図2D)。
(Step D) A photoresist is applied by a spin coater to the surface of the substrate 11 in which the groove 12 is filled with the turn portions 22 of the superconducting thin film coil in step C, and the surface of the substrate 11 is 0.5 μm thick. After the entire surface was covered with a layer, the resist was exposed using a photomask having a mask pattern corresponding to the predetermined planar shape of the interlayer insulating film, and the resist was developed using an alkali developing solution.
As a result, an opening having the same shape as the planar shape of the interlayer insulating film was formed in the resist layer on the turn portion 22 of the superconducting thin film coil in the groove 12. Then, the surface of the turn portion 22 of the superconducting thin film coil in the portion exposed from this opening was subjected to ion beam etching with argon for about 20 minutes. After that, the residual resist was removed using a stripping solution. As a result, at a predetermined position on the surface of the turn portion 22 of the superconducting thin film coil in the groove 12, a depth of 0.2 μm having the same opening shape as that of the interlayer insulating film was formed. Another groove 14 was formed (FIGS. 1D and 2D).

【0045】(工程E)工程Dで層間絶縁膜用の溝14
が形成された基板11を高周波マグネトロンスパッタ装
置にセットし、第2層目の成膜として、 MgOからなる絶
縁膜15を全面に0.2μmの厚さで成長させた。この
ときの成膜条件は、基板11を500℃に加熱し、スパ
ッタガスとしてアルゴンガスを導入し、全ガス圧は1m
Torrとした。またターゲットには MgO焼結体を用い、成
膜時間は2時間とした。これにより、超電導薄膜コイル
のターン部22の表面の溝14が丁度開口縁まで MgO絶
縁膜で埋められ、溝14の周囲の基板表面には0.2μ
m厚の MgO絶縁膜が積層された(図1E及び図2E)。
(Step E) In Step D, the groove 14 for the interlayer insulating film is formed.
The substrate 11 on which was formed was set in a high frequency magnetron sputtering apparatus, and an insulating film 15 made of MgO was grown to a thickness of 0.2 μm on the entire surface as a second layer film formation. The film forming conditions at this time are that the substrate 11 is heated to 500 ° C., argon gas is introduced as a sputtering gas, and the total gas pressure is 1 m.
Torr. A MgO sintered body was used as the target, and the film formation time was 2 hours. As a result, the groove 14 on the surface of the turn portion 22 of the superconducting thin-film coil is filled with the MgO insulating film just up to the opening edge, and the substrate surface around the groove 14 is 0.2 μm.
An m-thick MgO insulating film was laminated (FIGS. 1E and 2E).

【0046】(工程F)工程Eで得られた基板11の絶
縁膜15上にスピンコータによってフォトレジストを塗
布し、絶縁膜15の表面を厚さ0.5μmのフォトレジ
スト層で全面被覆したのち、工程Dで使用したのと相補
的なマスクパターンのフォトマスクを用いてレジストの
露光を行い、アルカリ現像液を用いてレジストを現像し
た。これにより、絶縁膜15の下層にある溝14に合致
する部分を残してレジスト層が除去された。次いでこの
除去部分に露出する0.2μm厚の絶縁膜15をアルゴ
ンによるイオンビームエッチングで除去した。このとき
のエッチング時間は約60分であった。その後、剥離液
を用いて残存レジストを除去したところ、溝14内を埋
めている絶縁膜15によって層間絶縁膜24が形成さ
れ、しかもこの層間絶縁膜24の表面とその周囲の基板
11、及び超電導薄膜コイルの外側コイル端と超電導薄
膜配線部との接続部23a及び超電導薄膜コイルの内側
コイル端と超電導薄膜クロス接続配線部との接続部25
aの表面とが同一の位置レベルとなり、平坦な表面が形
成された(図1F及び図2F)。
(Step F) A photoresist is applied on the insulating film 15 of the substrate 11 obtained in the step E by a spin coater to cover the entire surface of the insulating film 15 with a photoresist layer having a thickness of 0.5 μm. The resist was exposed using a photomask having a mask pattern complementary to that used in step D, and the resist was developed using an alkali developing solution. As a result, the resist layer was removed, leaving a portion corresponding to the groove 14 under the insulating film 15. Next, the insulating film 15 having a thickness of 0.2 μm exposed at the removed portion was removed by ion beam etching with argon. The etching time at this time was about 60 minutes. After that, when the residual resist was removed using a stripping solution, the interlayer insulating film 24 was formed by the insulating film 15 filling the inside of the groove 14, and the surface of the interlayer insulating film 24, the substrate 11 around the interlayer insulating film 24, and the superconductor. A connecting portion 23a between the outer coil end of the thin film coil and the superconducting thin film wiring portion, and a connecting portion 25 between the inner coil end of the superconducting thin film coil and the superconducting thin film cross connecting wiring portion.
The surface of a was at the same position level, and a flat surface was formed (FIGS. 1F and 2F).

【0047】(工程G)工程Fで得られた表面が平坦な
基板11を高周波マグネトロンスパッタ装置にセット
し、第3層目の成膜としてYBCO薄膜16を平坦な表面の
全面に0.4μmの厚さで成長させた。このときの成膜
条件は工程Bと同様であった。これにより基板11の表
面の全面に0.4μm厚のYBCO薄膜16が積層され、こ
のYBCO薄膜16の下層には層間絶縁膜24を介して超電
導薄膜コイルのターン部22が位置し、しかも超電導薄
膜コイルの外側コイル端と内側コイル端は夫々接続部2
3a及び25aでYBCO薄膜16と接合された状態となっ
た(図1G及び図2G)。
(Step G) The substrate 11 having a flat surface obtained in the step F is set in a high frequency magnetron sputtering apparatus, and a YBCO thin film 16 having a thickness of 0.4 μm is formed on the entire flat surface as a third layer. Grow in thickness. The film forming conditions at this time were the same as those in the step B. As a result, the YBCO thin film 16 having a thickness of 0.4 μm is laminated on the entire surface of the substrate 11, and the turn portion 22 of the superconducting thin film coil is located under the YBCO thin film 16 via the interlayer insulating film 24. The outer coil end and the inner coil end of the coil are respectively connected to the connecting portion 2
It became a state of being bonded to the YBCO thin film 16 at 3a and 25a (FIGS. 1G and 2G).

【0048】(工程H)工程GでYBCO薄膜16を積層し
た基板11の表面にスピンコータによってフォトレジス
トを塗布し、基板11の表面上のYBCO薄膜16を厚さ
0.5μmのフォトレジスト層で全面被覆したのち、予
め予定された超電導薄膜配線部及び超電導薄膜クロス接
続配線部の各平面形状に対応するマスクパターンのフォ
トマスクを用いてレジストの露光を行い、アルカリ現像
液を用いてレジストを現像した。これにより超電導薄膜
配線部及び超電導薄膜クロス接続配線部の各平面形状と
同じ形状のレジストパターンを残してYBCO薄膜16の表
面が露出された。
(Step H) A photoresist is applied by a spin coater to the surface of the substrate 11 on which the YBCO thin film 16 is laminated in step G, and the YBCO thin film 16 on the surface of the substrate 11 is entirely covered with a photoresist layer having a thickness of 0.5 μm. After coating, the resist was exposed using a photomask having a mask pattern corresponding to the plane shapes of the superconducting thin film wiring portion and the superconducting thin film cross connection wiring portion, which were previously planned, and the resist was developed using an alkali developing solution. . As a result, the surface of the YBCO thin film 16 was exposed, leaving a resist pattern having the same shape as the planar shape of the superconducting thin film wiring portion and the superconducting thin film cross connection wiring portion.

【0049】次いでこの露出部分のYBCO薄膜16に対し
てアルゴンによるイオンビームエッチングを約40分間
に亘って行い、その後、剥離液を用いて残存レジストを
除去したところ、超電導薄膜配線部23及び超電導薄膜
クロス接続配線部25が厚さ0.4μmで基板11の所
定位置に形成され、先に基板11に埋設形成された超電
導薄膜コイルのターン部22と共に超電導量子干渉デバ
イス用入力コイル20が得られた(図1H及び図2
H)。
Next, the exposed portion of the YBCO thin film 16 was subjected to ion beam etching with argon for about 40 minutes, and then the residual resist was removed using a stripping solution. The superconducting thin film wiring portion 23 and the superconducting thin film were then removed. The cross-connect wiring part 25 having a thickness of 0.4 μm was formed at a predetermined position of the substrate 11, and the input part 20 for the superconducting quantum interference device was obtained together with the turn part 22 of the superconducting thin-film coil previously embedded in the substrate 11. (Fig. 1H and Fig. 2
H).

【0050】以上のようにして作成された第1実施例の
入力コイル20の超電導薄膜配線部23及び超電導薄膜
クロス接続配線部25に金電極を作り込み、直流四端子
法でその臨界温度Tc及び臨界電流Icを測定したとこ
ろ、臨界温度Tcは85Kであり、臨界電流Icは77
Kにおいて55mAであった。
Gold electrodes were formed in the superconducting thin film wiring portion 23 and the superconducting thin film cross connecting wiring portion 25 of the input coil 20 of the first embodiment prepared as described above, and their critical temperatures Tc and When the critical current Ic was measured, the critical temperature Tc was 85K and the critical current Ic was 77.
It was 55 mA in K.

【0051】=第2実施例= MgO(100)単結晶に代えて SrTiO3(100)単結晶からなる基
板を用いて第1実施例と同様の工程で超電導量子干渉デ
バイス用入力コイルを作成し、同様に金電極を作り込ん
で直流四端子法によりその臨界温度Tc及び臨界電流I
cを測定したところ、臨界温度Tcは86Kであり、臨
界電流Icは77Kにおいて62mAであった。
= Second Embodiment = An input coil for a superconducting quantum interference device was prepared in the same process as in the first embodiment by using a substrate made of SrTiO 3 (100) single crystal instead of MgO (100) single crystal. , A gold electrode is similarly formed, and its critical temperature Tc and critical current I are measured by the DC four-terminal method.
When c was measured, the critical temperature Tc was 86K and the critical current Ic was 62 mA at 77K.

【0052】=第3実施例= 層間絶縁膜を MgOからSrTiO3に代えた以外は第2実施例
と同様にして超電導量子干渉デバイス用入力コイルを作
成した。この場合、層間絶縁膜としてのSrTiO3の成膜条
件は、基板を高周波マグネトロンスパッタ装置にセット
して300℃に加熱し、装置のチャンバにはスパッタガ
スとしてアルゴンガスを導入し、全ガス圧を2mTorrと
した。またターゲットにはSrTiO3焼結体を用い、成膜時
間は1時間とした。
= Third Example = An input coil for a superconducting quantum interference device was prepared in the same manner as in the second example except that the interlayer insulating film was changed from MgO to SrTiO 3 . In this case, the conditions for forming SrTiO 3 as the interlayer insulating film are as follows: the substrate is set in a high-frequency magnetron sputtering device and heated to 300 ° C., argon gas is introduced into the chamber of the device as a sputtering gas, and the total gas pressure is set to It was set to 2 mTorr. A SrTiO 3 sintered body was used as the target, and the film formation time was 1 hour.

【0053】このようにして作成された第3実施例の入
力コイルの第1及び第2の超電導薄膜配線部に同様に金
電極を作り込み、直流四端子法によりその臨界温度Tc
及び臨界電流Icを測定したところ、臨界温度Tcは8
6Kであり、臨界電流Icは77Kにおいて68mAで
あった。
Gold electrodes are similarly formed in the first and second superconducting thin film wiring portions of the input coil of the third embodiment thus produced, and their critical temperature Tc is obtained by the DC four-terminal method.
When the critical current Ic is measured, the critical temperature Tc is 8
6K, and the critical current Ic was 68mA at 77K.

【0054】=第4実施例= 各超電導薄膜の材料をYBCOからBi2Sr2Ca1Cu2OXに代えた
以外は第1実施例と同様にして超電導量子干渉デバイス
用入力コイルを作成した。この場合、各超電導薄膜とし
てのBi2Sr2Ca1Cu2OXの成膜条件は、基板を高周波マグネ
トロンスパッタ装置にセットして800℃に加熱し、ス
パッタガスとしてアルゴンと酸素との1:3の混合ガス
を導入し、全ガス圧は100mTorrとした。また、ター
ゲットにはBi2Sr2Ca1Cu2OX焼結体を用い、成膜時間は5
時間とした。
= Fourth Embodiment = An input coil for a superconducting quantum interference device was prepared in the same manner as in the first embodiment except that the material of each superconducting thin film was changed from YBCO to Bi 2 Sr 2 Ca 1 Cu 2 O X. . In this case, the film forming conditions of Bi 2 Sr 2 Ca 1 Cu 2 O X as each superconducting thin film are as follows: the substrate is set in a high frequency magnetron sputtering device and heated to 800 ° C. The mixed gas of No. 3 was introduced, and the total gas pressure was 100 mTorr. Further, a Bi 2 Sr 2 Ca 1 Cu 2 O X sintered body was used as a target, and the film formation time was 5
It was time.

【0055】このようにして作成された第4実施例の入
力コイルの第1及び第2の超電導薄膜配線部に同様に金
電極を作り込み、直流四端子法によりその臨界温度Tc
及び臨界電流Icを測定したところ、臨界温度Tcは8
2Kであり、臨界電流Icは77Kにおいて41mAで
あった。
Gold electrodes are similarly formed in the first and second superconducting thin film wiring portions of the input coil of the fourth embodiment thus produced, and their critical temperature Tc is obtained by the DC four-terminal method.
When the critical current Ic is measured, the critical temperature Tc is 8
It was 2K and the critical current Ic was 41mA at 77K.

【0056】=第5実施例= 本発明の第5実施例に係る超電導量子干渉デバイス用入
力コイルについて、その薄膜積層構造を成膜プロセスの
順を追って図6及び図7に示す。即ち、図6A〜Hは以
下に述べる成膜プロセスの工程A〜Hの順に示した模式
平面図、図7A〜Hは同様に図1bに対応して工程A〜
Hの順に示した模式断面図である。
= Fifth Embodiment = FIG. 6 and FIG. 7 show a thin film laminated structure of an input coil for a superconducting quantum interference device according to a fifth embodiment of the present invention in the order of the film forming process. That is, FIGS. 6A to 6H are schematic plan views showing the steps A to H of the film forming process described below in order, and FIGS. 7A to 7H also correspond to FIG.
It is a schematic cross section shown in order of H.

【0057】(工程A)MgO(100)単結晶からなる基板6
1の表面にスピンコータによってフォトレジストを塗布
し、基板61の表面を厚さ0.5μmのフォトレジスト
層で全面被覆したのち、予め予定されたクロス接続配線
部の平面形状に対応するマスクパターンのフォトマスク
を用いてレジストの露光を行い、アルカリ現像液を用い
てレジストを現像した。これによりクロス接続配線部の
平面形状と同じ形状の開口がレジスト層に形成された。
次いでこの開口から露出する部分の基板表面に対してア
ルゴンによるイオンビームエッチングを行い、クロス接
続配線部の平面形状と同じ開口形状で平坦な底面をもつ
深さ0.4μmの溝62を、基板61の所定位置に形成
した(図6A及び図7A)。
(Step A) Substrate 6 made of MgO (100) single crystal
1 is coated with a photoresist by a spin coater, and the surface of the substrate 61 is entirely covered with a photoresist layer having a thickness of 0.5 μm. Then, a photomask having a mask pattern corresponding to a plan shape of a cross-connect wiring portion is prepared in advance. The resist was exposed using a mask, and the resist was developed using an alkaline developer. As a result, an opening having the same shape as the plan shape of the cross connection wiring portion was formed in the resist layer.
Next, ion beam etching with argon is performed on the substrate surface of the portion exposed from this opening to form a 0.4 μm deep groove 62 having a flat bottom surface with the same opening shape as the plane shape of the cross connection wiring portion. Was formed at a predetermined position (FIGS. 6A and 7A).

【0058】(工程B)工程Aで溝62が形成された基
板61を高周波マグネトロンスパッタ装置にセットし、
第1層目の成膜としてYBCO薄膜63を全面に0.4μm
の厚さで成長させた。このときの成膜条件は、基板61
を700℃に加熱し、スパッタガスとしてアルゴンと酸
素の1:1の混合ガスを導入し、全ガス圧は150mTo
rr、ターゲットにはYBCO焼結体を用い、成膜時間は
4時間とした。これにより溝62が丁度開口縁までYBCO
薄膜で埋められ、溝62の周囲の基板表面には0.4μ
m厚のYBCO薄膜が積層された(図6B及び図7B)。
(Step B) The substrate 61 having the groove 62 formed in the step A is set in a high frequency magnetron sputtering apparatus,
A YBCO thin film 63 is formed on the entire surface to form a first layer of 0.4 μm.
Grown to a thickness of. The film forming conditions at this time are as follows:
Is heated to 700 ° C., a 1: 1 mixed gas of argon and oxygen is introduced as a sputtering gas, and the total gas pressure is 150 mTo.
rr, a YBCO sintered body was used as the target, and the film formation time was 4 hours. This allows the groove 62 to reach the opening edge YBCO
Filled with a thin film, 0.4μ on the substrate surface around the groove 62
An m-thick YBCO thin film was laminated (FIGS. 6B and 7B).

【0059】(工程C)工程Bで得られた基板61のYB
CO薄膜63上にスピンコータによってフォトレジストを
塗布し、YBCO薄膜63の表面を厚さ0.5μmのフォト
レジスト層で全面被覆したのち、工程Aで使用したのと
相補的なマスクパターンのフォトマスクを用いてレジス
トの露光を行い、アルカリ現像液を用いてレジストを現
像した。これにより、YBCO薄膜63の下層にある溝62
に合致する部分を残してレジスト層が除去された。次い
でこの除去部分に露出する0.4μm厚のYBCO薄膜をア
ルゴンによるイオンビームエッチングで除去した。この
ときのエッチング時間は40分程度であった。その後、
剥離液を用いて残存レジストを除去したところ、溝62
内を埋めているYBCO薄膜63の表面とその周囲の基板6
1の表面とが同一の位置レベルとなり、面一の平坦な表
面が形成された(図6C及び図7C)。
(Step C) YB of the substrate 61 obtained in Step B
A photoresist is applied onto the CO thin film 63 by a spin coater, the surface of the YBCO thin film 63 is entirely covered with a photoresist layer having a thickness of 0.5 μm, and then a photomask having a mask pattern complementary to that used in step A is formed. Was used to expose the resist, and the resist was developed using an alkaline developer. As a result, the groove 62 under the YBCO thin film 63 is formed.
The resist layer was removed, leaving a portion corresponding to. Next, the 0.4 μm-thick YBCO thin film exposed at this removed portion was removed by ion beam etching with argon. The etching time at this time was about 40 minutes. afterwards,
When the residual resist was removed using a stripping solution, the groove 62
The surface of the YBCO thin film 63 filling the inside and the substrate 6 around it
The surface of No. 1 was at the same position level, and a flush surface was formed (FIGS. 6C and 7C).

【0060】(工程D)工程Cで溝62内をYBCO薄膜6
3で埋めた基板61の表面にスピンコータによってフォ
トレジストを塗布し、基板61の表面を厚さ0.5μm
のフォトレジスト層で全面被覆したのち、予め予定され
た層間絶縁膜の平面形状に対応するマスクパターンのフ
ォトマスクを用いてレジストの露光を行い、アルカリ現
像液を用いてレジストを現像した。これにより層間絶縁
膜の平面形状と同じ形状の開口が溝62内のYBCO薄膜6
3上のレジスト層に形成された。次いでこの開口から露
出する部分のYBCO薄膜63の表面に対してアルゴンによ
るイオンビームエッチングを約20分間に亘って行っ
た。その後、剥離液を用いて残存レジストを除去したと
ころ、溝62内のYBCO薄膜63の表面の所定位置に、層
間絶縁膜の平面形状と同じ開口形状をもつ深さ0.2μ
mの別の溝64が形成され、溝64の両端に基板表面と
同一位置レベルの接続部75a,75bを有する超電導
薄膜クロス配線部75が形成された(図6D及び図7
D)。
(Step D) In step C, the inside of the groove 62 is filled with the YBCO thin film 6
A photoresist is applied to the surface of the substrate 61 filled with 3 with a spin coater, and the surface of the substrate 61 has a thickness of 0.5 μm.
After the entire surface was covered with the photoresist layer, the resist was exposed by using a photomask having a mask pattern corresponding to a predetermined planar shape of the interlayer insulating film, and the resist was developed by using an alkali developing solution. As a result, an opening having the same shape as the planar shape of the interlayer insulating film is formed in the YBCO thin film 6 in the groove 62.
3 was formed on the resist layer. Next, the surface of the YBCO thin film 63 exposed from this opening was subjected to ion beam etching with argon for about 20 minutes. After that, the residual resist was removed using a stripping solution, and a depth of 0.2 μm having the same opening shape as the planar shape of the interlayer insulating film was formed at a predetermined position on the surface of the YBCO thin film 63 in the groove 62.
Another groove 64 of m is formed, and a superconducting thin film cross wiring portion 75 having connection portions 75a and 75b at the same position level as the substrate surface is formed at both ends of the groove 64 (FIGS. 6D and 7).
D).

【0061】(工程E)工程Dで超電導薄膜クロス配線
部75が形成された基板61を高周波マグネトロンスパ
ッタ装置にセットし、第2層目の成膜として MgOからな
る絶縁膜65を全面に0.2μmの厚さで成長させた。
このときの成膜条件は、基板61を500℃に加熱し、
スパッタガスとしてアルゴンガスを導入し、全ガス圧は
1mTorrとした。またターゲットには MgO焼結体を用
い、成膜時間は2時間とした。これにより、クロス配線
部75の表面の溝64が丁度開口縁まで MgO絶縁膜で埋
められ、溝64の周囲の基板表面には0.2μm厚の M
gO絶縁膜が積層された(図6E及び図7E)。
(Step E) In step D, the substrate 61 on which the superconducting thin film cross wiring portion 75 is formed is set in a high frequency magnetron sputtering apparatus, and an insulating film 65 made of MgO is formed on the entire surface as a second layer. It was grown to a thickness of 2 μm.
The film forming conditions at this time are as follows: the substrate 61 is heated to 500 ° C.
Argon gas was introduced as the sputtering gas, and the total gas pressure was 1 mTorr. A MgO sintered body was used as the target, and the film formation time was 2 hours. As a result, the groove 64 on the surface of the cross wiring portion 75 is filled with the MgO insulating film just up to the opening edge, and a 0.2 μm thick M
A gO insulating film was laminated (FIGS. 6E and 7E).

【0062】(工程F)工程Eで得られた基板61の絶
縁膜65上にスピンコータによってフォトレジストを塗
布し、絶縁膜65の表面を厚さ0.5μmのフォトレジ
スト層で全面被覆したのち、工程Dで使用したのと相補
的なマスクパターンのフォトマスクを用いてレジストの
露光を行い、アルカリ現像液を用いてレジストを現像し
た。これにより、絶縁膜65の下層にある溝64に合致
する部分を残してレジスト層が除去された。次いでこの
除去部分に露出する0.2μm厚の絶縁膜65をアルゴ
ンによるイオンビームエッチングで除去した。このとき
のエッチング時間は約60分であった。その後、剥離液
を用いて残存レジストを除去したところ、溝64内を埋
めている絶縁膜65によって層間絶縁膜74が形成さ
れ、しかもこの層間絶縁膜74の表面とその周囲の基板
61及び各接続部75a,75bの表面とが同一の位置
レベルとなり、平坦な表面が形成された(図6F及び図
7F)。
(Step F) A photoresist is applied to the insulating film 65 of the substrate 61 obtained in the step E by a spin coater, and the surface of the insulating film 65 is entirely covered with a photoresist layer having a thickness of 0.5 μm. The resist was exposed using a photomask having a mask pattern complementary to that used in step D, and the resist was developed using an alkali developing solution. As a result, the resist layer was removed, leaving a portion corresponding to the groove 64 under the insulating film 65. Next, the insulating film 65 having a thickness of 0.2 μm exposed at the removed portion was removed by ion beam etching with argon. The etching time at this time was about 60 minutes. Then, when the residual resist is removed by using a stripping solution, an interlayer insulating film 74 is formed by the insulating film 65 filling the inside of the groove 64, and the surface of the interlayer insulating film 74 and the surrounding substrate 61 and each connection. The surfaces of the parts 75a and 75b were at the same position level, and a flat surface was formed (FIGS. 6F and 7F).

【0063】(工程G)工程Fで得られた表面が平坦な
基板61を高周波マグネトロンスパッタ装置にセット
し、第3層目の成膜としてYBCO薄膜66を平坦な表面の
全面に0.4μmの厚さで成長させた。このときの成膜
条件は工程Bと同様であった。これにより基板61の表
面の全面に0.4μm厚のYBCO薄膜66が積層され、こ
のYBCO薄膜66の下層には層間絶縁膜74を介してクロ
ス接続配線部75が位置し、しかもクロス接続配線部7
5の各接続部75a,75bとYBCO薄膜66とは接合さ
れた状態となった(図6G及び図7G)。
(Step G) The substrate 61 having a flat surface obtained in the step F is set in a high frequency magnetron sputtering apparatus, and a YBCO thin film 66 having a thickness of 0.4 μm is formed on the entire flat surface as a third layer. Grow in thickness. The film forming conditions at this time were the same as those in the step B. As a result, the YBCO thin film 66 having a thickness of 0.4 μm is laminated on the entire surface of the substrate 61, and the cross connection wiring part 75 is located under the YBCO thin film 66 via the interlayer insulating film 74. 7
The connection parts 75a and 75b of No. 5 and the YBCO thin film 66 were joined (FIGS. 6G and 7G).

【0064】(工程H)工程GでYBCO薄膜66を積層し
た基板61の表面にスピンコータによってフォトレジス
トを塗布し、基板61の表面上のYBCO薄膜66を厚さ
0.5μmのフォトレジスト層で全面被覆したのち、予
め予定された超電導薄膜コイルターン部及び第1と第2
の超電導薄膜配線部の各平面形状に対応するマスクパタ
ーンのフォトマスクを用いてレジストの露光を行い、ア
ルカリ現像液を用いてレジストを現像した。これにより
超電導薄膜コイルターン部及び第1と第2の超電導薄膜
配線部の各平面形状と同じ形状のレジストパターンを残
してYBCO薄膜66の表面が露出された。
(Step H) A photoresist is applied by a spin coater to the surface of the substrate 61 on which the YBCO thin film 66 is laminated in step G, and the YBCO thin film 66 on the surface of the substrate 61 is entirely covered with a photoresist layer having a thickness of 0.5 μm. After coating, the superconducting thin film coil turn portion and the first and second predetermined
The resist was exposed to light using a photomask having a mask pattern corresponding to each planar shape of the superconducting thin film wiring part, and the resist was developed using an alkali developing solution. As a result, the surface of the YBCO thin film 66 was exposed, leaving a resist pattern having the same shape as the planar shapes of the superconducting thin film coil turn portion and the first and second superconducting thin film wiring portions.

【0065】次いでこの露出部分のYBCO薄膜66に対し
てアルゴンによるイオンビームエッチングを約40分間
に亘って行い、その後、剥離液を用いて残存レジストを
除去したところ、超電導薄膜コイル72(ターン部)及
び第1と第2の超電導薄膜配線部73b,73aが厚さ
0.4μmで基板61の所定位置に形成され、先に基板
61に埋設形成された超電導薄膜クロス接続配線部75
と共に超電導量子干渉デバイス用入力コイル70が得ら
れた(図6H及び図7H)。
Then, the exposed YBCO thin film 66 was subjected to ion beam etching with argon for about 40 minutes, and then the residual resist was removed by using a stripping solution. As a result, the superconducting thin-film coil 72 (turn portion) was obtained. Also, the first and second superconducting thin film wiring portions 73b and 73a are formed at a predetermined position on the substrate 61 with a thickness of 0.4 μm, and the superconducting thin film cross connection wiring portion 75 which is previously embedded in the substrate 61 is formed.
At the same time, an input coil 70 for a superconducting quantum interference device was obtained (FIGS. 6H and 7H).

【0066】以上のようにして作成された第5実施例の
入力コイル70の第1及び第2の超電導薄膜配線部73
b,73aに金電極を作り込み、直流四端子法でその臨
界温度Tc及び臨界電流Icを測定したところ、臨界温
度Tcは85Kであり、臨界電流Icは77Kにおいて
55mAであった。
The first and second superconducting thin film wiring portions 73 of the input coil 70 of the fifth embodiment produced as described above.
When a gold electrode was formed in b and 73a and the critical temperature Tc and the critical current Ic were measured by the DC four-terminal method, the critical temperature Tc was 85K and the critical current Ic was 55mA at 77K.

【0067】=第6実施例= MgO(100)単結晶に代えて SrTiO3(100)単結晶からなる基
板を用いて第5実施例と同様の工程で超電導量子干渉デ
バイス用入力コイルを作成し、同様に金電極を作り込ん
で直流四端子法によりその臨界温度Tc及び臨界電流I
cを測定したところ、臨界温度Tcは86Kであり、臨
界電流Icは77Kにおいて62mAであった。
= Sixth Embodiment = An input coil for a superconducting quantum interference device was prepared in the same process as in the fifth embodiment by using a substrate made of SrTiO 3 (100) single crystal instead of MgO (100) single crystal. , A gold electrode is similarly formed, and its critical temperature Tc and critical current I are measured by the DC four-terminal method.
When c was measured, the critical temperature Tc was 86K and the critical current Ic was 62 mA at 77K.

【0068】=第7実施例= 層間絶縁膜を MgOからSrTiO3に代えた以外は第6実施例
と同様にして超電導量子干渉デバイス用入力コイルを作
成した。この場合、層間絶縁膜としてのSrTiO3の成膜条
件は、基板を高周波マグネトロンスパッタ装置にセット
して300℃に加熱し、装置のチャンバにはスパッタガ
スとしてアルゴンガスを導入し、全ガス圧を2mTorrと
した。またターゲットにはSrTiO3焼結体を用い、成膜時
間は1時間とした。
= Seventh Example = An input coil for a superconducting quantum interference device was prepared in the same manner as in the sixth example except that the interlayer insulating film was changed from MgO to SrTiO 3 . In this case, the conditions for forming SrTiO 3 as the interlayer insulating film are as follows: the substrate is set in a high-frequency magnetron sputtering device and heated to 300 ° C., argon gas is introduced into the chamber of the device as a sputtering gas, and the total gas pressure is set to It was set to 2 mTorr. A SrTiO 3 sintered body was used as the target, and the film formation time was 1 hour.

【0069】このようにして作成された第7実施例の入
力コイルの第1及び第2の超電導薄膜配線部に同様に金
電極を作り込み、直流四端子法によりその臨界温度Tc
及び臨界電流Icを測定したところ、臨界温度Tcは8
6Kであり、臨界電流Icは77Kにおいて68mAで
あった。
Gold electrodes are similarly formed in the first and second superconducting thin film wiring portions of the input coil of the seventh embodiment thus produced, and their critical temperature Tc is obtained by the DC four-terminal method.
When the critical current Ic is measured, the critical temperature Tc is 8
6K, and the critical current Ic was 68mA at 77K.

【0070】=第8実施例= 各超電導薄膜の材料をYBCOからBi2Sr2Ca1Cu2OXに代えた
以外は第5実施例と同様にして超電導量子干渉デバイス
用入力コイルを作成した。この場合、各超電導薄膜とし
てのBi2Sr2Ca1Cu2OXの成膜条件は、基板を高周波マグネ
トロンスパッタ装置にセットして800℃に加熱し、ス
パッタガスとしてアルゴンと酸素との1:2の混合ガス
を導入し、全ガス圧を100mTorrとした。また、ター
ゲットにはBi2Sr2Ca1Cu2OX焼結体を用い、成膜時間は5
時間とした。
= Eighth Embodiment = An input coil for a superconducting quantum interference device was prepared in the same manner as in the fifth embodiment except that the material of each superconducting thin film was changed from YBCO to Bi 2 Sr 2 Ca 1 Cu 2 O X. . In this case, the film forming conditions of Bi 2 Sr 2 Ca 1 Cu 2 O X as each superconducting thin film are as follows: the substrate is set in a high frequency magnetron sputtering device and heated to 800 ° C. The mixed gas of 2 was introduced and the total gas pressure was set to 100 mTorr. Further, a Bi 2 Sr 2 Ca 1 Cu 2 O X sintered body was used as a target, and the film formation time was 5
It was time.

【0071】このようにして作成された第8実施例の入
力コイルの第1及び第2の超電導薄膜配線部に同様に金
電極を作り込み、直流四端子法によりその臨界温度Tc
及び臨界電流Icを測定したところ、臨界温度Tcは8
2Kであり、臨界電流Icは77Kにおいて41mAで
あった。
Gold electrodes are similarly formed in the first and second superconducting thin film wiring portions of the input coil of the eighth embodiment thus produced, and their critical temperature Tc is obtained by the DC four-terminal method.
When the critical current Ic is measured, the critical temperature Tc is 8
It was 2K and the critical current Ic was 41mA at 77K.

【0072】第1実施例〜第8実施例についての測定結
果から、本発明による積層薄膜構造を持つ入力コイルに
おける臨界電流は、先に述べた図3及び図4の従来例に
比べて桁違いの大きさであることが確認できた。
From the measurement results of the first to eighth examples, the critical current in the input coil having the laminated thin film structure according to the present invention is incomparable to that of the conventional examples of FIGS. 3 and 4 described above. It was confirmed to be the size of.

【0073】[0073]

【発明の効果】以上に述べたように、本発明の超電導量
子干渉デバイス用入力コイルは超電導薄膜の成膜を全て
実質的に平坦な面に対して行うことができる薄膜積層構
造を備えているので、ペロブスカイト構造の酸化物超電
導体として知られる高温超電導体によってスパッタリン
グ等の通常の薄膜プロセスによる成膜技術で作成するこ
とができるだけでなく、高温超電導薄膜の成膜に際して
凹凸や段差のある表面上に成膜する工程を一切なくすこ
とができるので、プロセス中に超電導薄膜内に局部的な
大傾角粒界部を形成することがない。したがって、超電
導薄膜による閉回路中に局部的な大傾角粒界部が介在す
ることによる臨界電流の低下を抑止することができ、従
来に比べて臨界電流が飛躍的に向上した入力コイルを実
現してSQUIDの検出感度の向上に寄与することがで
きるものである。
As described above, the input coil for a superconducting quantum interference device of the present invention has a thin film laminated structure capable of forming a superconducting thin film on a substantially flat surface. Therefore, not only can it be formed by a high-temperature superconductor known as an oxide superconductor having a perovskite structure by a film-forming technique by a normal thin-film process such as sputtering, but also on a surface having unevenness or steps when forming a high-temperature superconducting thin film. Since it is possible to eliminate the step of forming a film at all, there is no formation of a local high-angle grain boundary part in the superconducting thin film during the process. Therefore, it is possible to prevent a decrease in the critical current due to the interposition of a high-angle tilt grain boundary part in the closed circuit formed by the superconducting thin film, and to realize an input coil in which the critical current is dramatically improved compared to the conventional one. It can contribute to the improvement of the detection sensitivity of SQUID.

【0074】このため、本発明による入力コイルで構成
した磁束トランスの閉回路には充分に大きな臨界電流を
流すことができ、SQUIDの感度を従来よりも飛躍的
に高めることが可能になる。
Therefore, a sufficiently large critical current can be passed through the closed circuit of the magnetic flux transformer constituted by the input coil according to the present invention, and the sensitivity of the SQUID can be remarkably increased as compared with the conventional case.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1A〜Hは、本発明の第1実施例に係る超電
導量子干渉デバイス用入力コイルについて、その薄膜積
層構造を成膜プロセスの工程A〜Hの順に示した模式平
面図である。
1A to 1H are schematic plan views showing a thin film stack structure of an input coil for a superconducting quantum interference device according to a first embodiment of the present invention in the order of steps A to H of a film forming process. .

【図2】図2A〜Hは、第1実施例に係る超電導量子干
渉デバイス用入力コイルの薄膜積層構造を図1に対応し
て工程A〜Hの順に示した模式断面図である。
2A to 2H are schematic cross-sectional views showing the thin film laminated structure of the input coil for the superconducting quantum interference device according to the first embodiment in the order of steps A to H corresponding to FIG.

【図3】図3Aは従来の磁束トランスにおける入力コイ
ルの一例を示す拡大平面図、図3Bは図3AのB−B線
矢視模式断面図である。
FIG. 3A is an enlarged plan view showing an example of an input coil in a conventional magnetic flux transformer, and FIG. 3B is a schematic sectional view taken along the line BB of FIG. 3A.

【図4】図4Aは従来の入力コイルの別の一例を示す拡
大平面図、図4Bおよび図4Cはそれぞれ図4AのB−
BおよびC−C矢視模式断面図である。
FIG. 4A is an enlarged plan view showing another example of the conventional input coil, and FIGS. 4B and 4C are B- of FIG. 4A, respectively.
FIG. 3 is a schematic cross-sectional view taken along arrows B and C-C.

【図5】成膜プロセス中に高温超電導薄膜内に形成され
る局部的な大傾角粒界部を説明するための模式断面図で
ある。
FIG. 5 is a schematic cross-sectional view for explaining a local high-angle grain boundary portion formed in a high temperature superconducting thin film during a film forming process.

【図6】図6A〜Hは、本発明の第5実施例に係る超電
導量子干渉デバイス用入力コイルについて、その薄膜積
層構造を成膜プロセスの工程A〜Hの順に示した模式平
面図である。
6A to 6H are schematic plan views showing the thin film laminated structure of an input coil for a superconducting quantum interference device according to a fifth embodiment of the present invention in the order of steps A to H of the film forming process. .

【図7】図7A〜Hは、第5実施例に係る超電導量子干
渉デバイス用入力コイルの薄膜積層構造を図1に対応し
て工程A〜Hの順に示した模式断面図である。
7A to 7H are schematic cross-sectional views showing the thin film laminated structure of the input coil for the superconducting quantum interference device according to the fifth embodiment in the order of steps A to H corresponding to FIG.

【符号の説明】[Explanation of symbols]

11:基板 12:溝(基板表面下に形成された溝) 13:YBCO薄膜 14:溝(超電導薄膜コイル部の表面下に形成された
溝) 15:MgO 絶縁膜 16:YBCO薄膜 20:超電導量子干渉デバイス用入力コイル 22:超電導薄膜コイル(ターン部) 23:超電導薄膜配線部 23a:外側コイル端と超電導薄膜配線部との接続部 24:層間絶縁膜 25:超電導薄膜クロス接続配線部 25a:内側コイル端と超電導薄膜クロス接続配線部と
の接続部 61:基板 62:溝(基板表面下に形成された溝) 63:YBCO薄膜 64:溝(超電導薄膜クロス接続配線部の表面下に形成
された溝) 65:MgO 絶縁膜 66:YBCO薄膜 70:超電導量子干渉デバイス用入力コイル 72:超電導薄膜コイル(ターン部) 73a:第2の超電導薄膜配線部 73b:第1の超電導薄膜配線部 74:層間絶縁膜 75:超電導薄膜クロス接続配線部 75a:内側コイル端と超電導薄膜クロス接続配線部と
の接続部 75b:第1の超電導薄膜配線部と超電導薄膜クロス接
続配線部との接続部
11: Substrate 12: Groove (groove formed under the surface of substrate) 13: YBCO thin film 14: Groove (groove formed under surface of superconducting thin film coil) 15: MgO insulating film 16: YBCO thin film 20: Superconducting quantum Input coil for interference device 22: Superconducting thin film coil (turn part) 23: Superconducting thin film wiring part 23a: Connection part between outer coil end and superconducting thin film wiring part 24: Interlayer insulating film 25: Superconducting thin film cross connecting wiring part 25a: Inside Connection part between coil end and superconducting thin film cross connecting wiring part 61: Substrate 62: Groove (groove formed under the substrate surface) 63: YBCO thin film 64: Groove (formed under superconducting thin film cross connecting wiring part surface Groove) 65: MgO insulating film 66: YBCO thin film 70: Input coil for superconducting quantum interference device 72: Superconducting thin film coil (turn part) 73a: Second superconducting thin film wiring part 73b: First Superconducting thin film wiring portion 74: Interlayer insulating film 75: Superconducting thin film cross connecting wiring portion 75a: Connection portion between inner coil end and superconducting thin film cross connecting wiring portion 75b: First superconducting thin film wiring portion and superconducting thin film cross connecting wiring portion Connection

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 超電導量子干渉デバイスを構成するため
のジョセフソン接合を含む超電導リングに対して磁気結
合するように基板上に薄膜積層構造として形成され、磁
場検知用のピックアップコイルと超電導閉回路の磁束ト
ランスを構成するように接続される入力コイルであっ
て、 複数ターンの渦巻状超電導薄膜コイル(22)と、 超電導薄膜コイル(22)の外側コイル端とピックアップコ
イルの一端との接続のための超電導薄膜配線部(23)と、 超電導薄膜コイル(22)の内側コイル端から超電導薄膜コ
イル(22)のターン部を径方向に横切ってピックアップコ
イルの他端との接続のための超電導薄膜クロス接続配線
部(25)と、 超電導薄膜クロス接続配線部(25)と超電導薄膜コイル(2
2)のターン部との間を絶縁する層間絶縁膜(24)とを備え
たものにおいて、 超電導薄膜コイル(22)のターン部が、基板(11)の表面下
に形成された第1の溝(12)内に埋設され、 層間絶縁膜(24)が、超電導薄膜コイル(22)の表面下に形
成された第2の溝(14)内に埋設され、 超電導薄膜コイル(22)の表面と層間絶縁膜(24)の表面と
を含む領域の実質的に平坦な基板表面上に超電導薄膜配
線部(23)及び超電導薄膜クロス接続配線部(25)とが形成
されていることを特徴とする超電導量子干渉デバイス用
入力コイル。
1. A pickup coil for magnetic field detection and a superconducting closed circuit formed as a thin film laminated structure on a substrate so as to be magnetically coupled to a superconducting ring including a Josephson junction for constituting a superconducting quantum interference device. An input coil connected so as to form a magnetic flux transformer, which is for connecting the spiral superconducting thin film coil (22) with multiple turns and the outer coil end of the superconducting thin film coil (22) to one end of the pickup coil. A superconducting thin film cross connection for connecting the superconducting thin film wiring part (23) and the other end of the pickup coil across the turn part of the superconducting thin film coil (22) from the inner coil end of the superconducting thin film coil (22) in the radial direction. Wiring part (25), superconducting thin film cross connection Wiring part (25) and superconducting thin film coil (2
The inter-layer insulating film (24) for insulating between the turn portion of (2) and the turn portion of the superconducting thin film coil (22), the first groove formed under the surface of the substrate (11). The interlayer insulating film (24) embedded in (12) is embedded in the second groove (14) formed below the surface of the superconducting thin film coil (22), and the surface of the superconducting thin film coil (22) is Characterized in that the superconducting thin film wiring portion (23) and the superconducting thin film cross connection wiring portion (25) are formed on the substantially flat substrate surface in the region including the surface of the interlayer insulating film (24) Input coil for superconducting quantum interference device.
【請求項2】 超電導薄膜コイル(22)の外側コイル端と
超電導薄膜配線部(23)との接続部(23a) の表面及び超電
導薄膜コイル(22)の内側コイル端と超電導薄膜クロス接
続配線部(25)との接続部(25a) の表面が層間絶縁膜(24)
の表面と共に基板(11)の表面と同一位置レベルの平面上
にあり、この平面上に形成された単一の平坦な超電導薄
膜層(16)から超電導薄膜配線部(23)及び超電導薄膜クロ
ス接続配線部(25)とが形成されていることを特徴とする
請求項1に記載の超電導量子干渉デバイス用入力コイ
ル。
2. A surface of a connecting portion (23a) between an outer coil end of the superconducting thin film coil (22) and the superconducting thin film wiring portion (23), an inner coil end of the superconducting thin film coil (22) and a superconducting thin film cross connecting wiring portion. The surface of the connection part (25a) with (25) is the interlayer insulation film (24).
Superconducting thin film wiring part (23) and superconducting thin film cross connection from a single flat superconducting thin film layer (16) which is on the same level as the surface of the substrate (11) together with the surface of The input coil for a superconducting quantum interference device according to claim 1, wherein a wiring portion (25) is formed.
【請求項3】 超電導量子干渉デバイスを構成するため
のジョセフソン接合を含む超電導リングに対して磁気結
合されるように基板上に薄膜積層構造として形成され、
磁場検知用のピックアップコイルと超電導閉回路の磁束
トランスを構成するように接続される入力コイルであっ
て、 複数ターンの渦巻状の超電導薄膜コイル(72)と、 超電導薄膜コイル(72)の外側コイル端とピックアップコ
イルの一端との接続のための第1の超電導薄膜配線部(7
3b) と、 超電導薄膜コイル(72)の内側コイル端とピックアップコ
イルの他端との接続のための第2の超電導薄膜配線部(7
3a) と、 超電導薄膜コイル(72)の内側コイル端から超電導薄膜コ
イル(72)のターン部を径方向に横切って第2の超電導薄
膜配線部(73a) に達する超電導薄膜クロス接続配線部(7
5)と、 超電導薄膜クロス接続配線部(75)と超電導薄膜コイル(7
2)のターン部との間を絶縁する層間絶縁膜(74)とを備え
たものにおいて、 超電導薄膜クロス接続配線部(75)が、超電導薄膜コイル
(72)のターン部を横切る部位において基板(61)の表面下
に形成された第1の溝(62)内に埋設され、 層間絶縁膜(74)が、超電導薄膜コイル(72)の内側コイル
端と第2の超電導薄膜配線部(73a) とに対する超電導薄
膜クロス接続配線部(75)の各接続部(75a,75b)を除く部
位において超電導薄膜クロス接続配線部(25)の表面下に
形成された第2の溝(64)内に埋設され、 前記各接続部(75a,75b) の表面と層間絶縁膜(74)の表面
とを含む領域の実質的に平坦な基板表面上に超電導薄膜
コイル(72)と第1の超電導薄膜配線部(73b) 及び第2の
超電導薄膜配線部(73a) とが形成されていることを特徴
とする超電導量子干渉デバイス用入力コイル。
3. A thin film laminated structure formed on a substrate so as to be magnetically coupled to a superconducting ring including a Josephson junction for constituting a superconducting quantum interference device,
An input coil connected so as to form a magnetic field detection pickup coil and a magnetic flux transformer of a superconducting closed circuit, which is a spiral superconducting thin film coil (72) with multiple turns and an outer coil of the superconducting thin film coil (72). The first superconducting thin film wiring section (7) for connecting the end to one end of the pickup coil.
3b) and a second superconducting thin film wiring part (7) for connecting the inner coil end of the superconducting thin film coil (72) and the other end of the pickup coil.
3a) and a superconducting thin film cross-connect wiring part (7a) that crosses the turn part of the superconducting thin film coil (72) radially from the inner coil end of the superconducting thin film coil (72) to reach the second superconducting thin film wiring part (73a).
5), the superconducting thin film cross connection wiring part (75) and the superconducting thin film coil (7
2) which has an interlayer insulating film (74) for insulating between the turn part and the turn part, the superconducting thin film cross connecting wiring part (75) is a superconducting thin film coil.
The inter-layer insulation film (74) is embedded in the first groove (62) formed below the surface of the substrate (61) at a position crossing the turn part of the (72), and the inner coil of the superconducting thin film coil (72). Formed below the surface of the superconducting thin film cross connecting wiring part (25) except the respective end portions (75a, 75b) of the superconducting thin film cross connecting wiring part (75) to the end and the second superconducting thin film wiring part (73a). Embedded in the formed second groove (64), and the superconducting thin film is formed on the substantially flat substrate surface in the region including the surfaces of the connection portions (75a, 75b) and the surface of the interlayer insulating film (74). An input coil for a superconducting quantum interference device, comprising a coil (72), a first superconducting thin film wiring portion (73b) and a second superconducting thin film wiring portion (73a).
【請求項4】 超電導薄膜コイル(72)の内側コイル端と
第2の超電導薄膜配線部(73a) とに対する超電導薄膜ク
ロス接続配線部(75)の各接続部(75a,75b) の表面が層間
絶縁膜(74)の表面と共に基板(61)の表面と同一位置レベ
ルの平面上にあり、この平面上に形成された単一の平坦
な超電導薄膜層(66)から超電導薄膜コイル(72)と第1の
超電導薄膜配線部(73b) 及び第2の超電導薄膜配線部(7
3a) が形成されていることを特徴とする請求項1に記載
の超電導量子干渉デバイス用入力コイル。
4. The surface of each connecting portion (75a, 75b) of the superconducting thin film cross connecting wiring portion (75) with respect to the inner coil end of the superconducting thin film coil (72) and the second superconducting thin film wiring portion (73a) is an interlayer. The surface of the insulating film (74) and the surface of the substrate (61) are on the same level level plane, and a single flat superconducting thin film layer (66) formed on this plane is replaced with the superconducting thin film coil (72). The first superconducting thin film wiring section (73b) and the second superconducting thin film wiring section (7b)
The input coil for a superconducting quantum interference device according to claim 1, wherein 3a) is formed.
JP6307043A 1994-09-16 1994-11-17 Input coil for superconducting quantum interference device Pending JPH08139376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6307043A JPH08139376A (en) 1994-09-16 1994-11-17 Input coil for superconducting quantum interference device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24675394 1994-09-16
JP6-246753 1994-09-16
JP6307043A JPH08139376A (en) 1994-09-16 1994-11-17 Input coil for superconducting quantum interference device

Publications (1)

Publication Number Publication Date
JPH08139376A true JPH08139376A (en) 1996-05-31

Family

ID=26537894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6307043A Pending JPH08139376A (en) 1994-09-16 1994-11-17 Input coil for superconducting quantum interference device

Country Status (1)

Country Link
JP (1) JPH08139376A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012026788A (en) * 2010-07-21 2012-02-09 Japan Oil Gas & Metals National Corp Magnetic sensor for underground resource exploration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012026788A (en) * 2010-07-21 2012-02-09 Japan Oil Gas & Metals National Corp Magnetic sensor for underground resource exploration

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