JPH08139332A - Apparatus and method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: To form a compact anodic-oxide layer having a uniform thickness by adding a specified amount of a IIIa-group element to Al. CONSTITUTION: A gate electrode is made of a material contg. Al as a main component and IIIa-group element (Sc) 0.01-1.0wt.%. For example, on a substrate 201 a base film 202 of SiN is formed and Al film is formed by the sputtering, in which Sc is contained 0.2wt.%. The contained material utilizes a rate earth element in the Periodic table IIIa and its content is 0.05-0.40wt.%, preferably, 0.1-0.25wt.%. The Al film is patterned and etched to form a gate electrode 203 and a gate wiring 204. The surface of the Al electrode is anodic-oxidized to form oxide layers 205 and 206.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a gate electrode of an insulating gate type field effect transistor and a wiring (gate wiring) extending from the gate electrode. The present invention particularly relates to one using a thin film semiconductor.

[0002]

2. Description of the Related Art An insulating gate type field effect transistor (hereinafter simply referred to as TF) using a thin film semiconductor formed on an insulating substrate.
(T) is known. This TFT is used as a switching element of a pixel electrode of an active matrix type liquid crystal display device or a driving element of a peripheral driver circuit. It can also be used in image sensors and other integrated circuits.

As a structure of a TFT, a structure as shown in FIG. 1 has been proposed. What is shown in FIG. 1A is called a bottom gate type, in which a gate insulating film 5 and a semiconductor active layer 6 are formed on a gate wiring 2 in the same layer as a gate electrode 1 containing aluminum as a main component. Is formed.
An amorphous or crystalline silicon thin film is used for the active layer. Since the source 8 and the drain 9 are on the opposite side of the gate electrode 1 with the active layer 6 interposed therebetween, the source 8 and the drain 9 are stagger type and are also bottom gate stagger type, so they are also called inverted stagger type. Wirings 10 and 11 are connected to the source and drain. An etching stopper 7 may be provided so as not to divide the active layer during the source / drain etching.

Here, the insulation between the gate electrode 1 and the active layer 6 or between the gate wiring 2 and the upper wiring 11 is mainly maintained by the gate insulating film 5. However, in order to further improve the insulating property, anodic oxidation is performed. Material coatings 3 and 4 are formed on the surfaces of the gate electrodes and wirings. This is because anodic oxides, especially barrier type anodic oxides, have no pinholes and the breakdown voltage thereof is almost the same as the maximum voltage of anodic oxidation.

The structure shown in FIG. 1B is called a top gate type. That is, the island-shaped thin film semiconductor active layer 21 is provided with a source 22, a drain 23 and a channel forming region, a gate insulating film 24 is formed so as to cover the active layer, and a gate containing aluminum as a main component is formed thereon. An electrode 25 and a gate wiring 26 are provided. Source/
It is also called a coplanar type because the drain is in the same plane as the gate electrode. And, covering the gate electrode and wiring,
An interlayer insulator 29 is formed, and an upper layer wiring 30,
31 is provided. Also in this case, in order to improve the insulation between the upper layer wiring and the gate wiring, the anodic oxide coatings 27, 2 are formed by anodizing the surface of the gate electrode / wiring.
It is proposed to provide 8.

Further, it has been proposed to use an offset gate structure in which the source / drain and the gate electrode are separated by a distance x by utilizing the fact that the gate electrode recedes due to anodic oxidation. (JP-A-5-267667) That is, the offset gate region is formed by utilizing the thickness of the oxide layer 27 provided around the gate electrode 25. In the structure shown in FIG. 1B, when the source 22 and the drain 23 are formed by an ion implantation method or an ion doping method, the gate electrode 25 and the oxide layer 27 around it become a mask.

As a result, a region which does not function as a channel and which does not function as a source / drain is formed adjacent to the source / drain in the region sandwiched between the source / drain. This region is called an offset gate region and has a function of relaxing electric field concentration between the channel and the drain or between the channel and the source. By providing this offset gate region, it is possible to obtain effects such as reduction of off current and improvement of on / off ratio when reverse bias is applied.

On the contrary, the width of the offset gate region (determined by the thickness of the oxide layer 27) can control the TFT characteristics to some extent. On the contrary, when the thickness of the oxide layer 27 cannot be formed with good controllability, the TFT characteristics vary. In addition, in the case of FIG.
Also in this case, when an anodic oxide coating is used to improve the insulation between wiring layers, a dense anodic oxide having a high breakdown voltage is required, and its variation is desired to be small.

The barrier type anodic oxide for such purpose is
The aluminum gate electrode / wiring is, for example, a 3% tartaric acid ethylene glycol solution (pH adjusted to neutral with ammonia).
It is formed by immersing the substrate in an adjusted one) and raising the voltage to 120 V or more at 1 to 10 V / min, for example, 4 V / min. Further, in the manufacturing process of the TFT,
A heating step and a step of irradiating with flash lamp light and laser light are required, but in such a step, it is also necessary that the oxide layer has resistance (laser resistance, heat resistance). .

According to various experiments conducted by the present inventors, when a pure aluminum material is used for the gate electrode / wiring, there is a problem that abnormal growth of aluminum (called hillock) occurs in the anodizing process. It was
In addition, in the structure in which the anodic oxide is formed on the surface of the aluminum film thus obtained, particularly when the anodic oxide is thin, resistance to irradiation with strong light such as laser light (laser resistance ) Is weak and does not have heat resistance. (That is, hillocks are generated and the anodic oxide layer is destroyed. Especially, hillocks are remarkably generated in the heat treatment at 350 ° C. or more.).

It can be considered that the above problems are caused by the fact that aluminum atoms easily move around at the atomic level when a large amount of energy is applied. To solve this problem, a method of suppressing the movement of aluminum at the atomic level by adding a trace amount of a material having a melting point higher than that of aluminum can be considered. Therefore, a method of adding Si or Pd to aluminum can be considered. The addition of such an element suppresses the generation of hillocks and improves the heat resistance.

However, since Si and Pd have a lower ionization rate than aluminum, there is a problem that the anodic oxide cannot be thickened in the anodizing step. In addition, the periodic table IV
Si which is an element of group b and Pd which is an element of group VIII of the periodic table
However, there is a problem that the oxidation does not proceed uniformly, the thickness of the oxide layer is not uniform, and a dense oxide layer cannot be formed (see Example 3). As a result, the laser resistance is rather lowered. Further, when a TFT as shown in FIG. 1B is formed using such an aluminum material, the thickness of the anodic oxide layer 27 varies depending on the location, so that the width of the offset region varies. There is also a problem.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems. In particular, in the anodizing step, it is an object to form the oxide layer densely and uniformly with good reproducibility, and to increase the resistance in the subsequent heating step and laser beam irradiation step.

[0014]

The present invention is capable of preventing abnormal growth of aluminum in an oxidation step or a heating step by adding 0.01% by weight to 1.0% by weight of a Group IIIa element to aluminum. Is. II here
Group Ia elements are Sc, Y, lanthanoids, and actinides. Particularly, the present invention is characterized in that Sc (scandium) is added to aluminum in an amount of 0.05% by weight to 0.40% by weight, preferably 0.1% by weight to 0.25% by weight.

When the concentration is 0.05% by weight or less, the heat resistance is not sufficient, and hillocks are generated at 350 ° C. for 1 hour. For etching these materials, wet etching or dry etching can be used as in the conventional case. When dry etching is performed, additional elements (such as scandium) remain as a residue depending on the conditions, and especially when this amount is 0.40 wt% or more, the residue remains on the surface etched by dry etching. However, this can be removed by washing with pure water.

[0016]

When the anodic oxidation is carried out by using the aluminum containing such impurities, a dense and uniform anodic oxide layer can be obtained. Further, it is possible to prevent abnormal growth of aluminum in the anodizing step. S
Besides c, Y, La and lanthanoids can be used. As a result, the anodic oxidation process can be performed with good controllability and reproducibility. When a TFT having an offset region as shown in FIG. A TFT having a uniform width (that is, uniform characteristics) can be obtained.

Sc has a higher ionization rate than aluminum and does not interfere with the oxidation of aluminum in the anodizing step. Therefore, a dense oxide layer can be formed. Further, since the effect of suppressing the movement of aluminum at the atomic level is also high, it is possible to suppress the generation of hillocks in the heating or anodizing process. The anodic oxide layer is dense and has a smooth surface.
Since the surface state of the interface between the anodic oxide layer and the aluminum film has few irregularities, it excels in light reflection and enhances laser resistance.

The above applies to the case of forming a thin anodic oxide having a thickness of 1200 Å or less. Conventional S
The heat resistance and laser resistance could not be expected unless the anodic oxide layer containing i or Pd had a certain thickness (usually 2000 Å or more). This is because the surface of the anodic oxide is uneven as described above, and the anodic oxide is thin and thick, and the thin anodic oxide layer is destroyed by heating and laser irradiation. . However, when the Group IIIa element of the present invention is added,
Since the anodization progresses uniformly, the above-mentioned unevenness hardly occurs. Therefore, 300 ~ 1200Å
Even with such a thin anodic oxide layer, one having excellent heat resistance and laser resistance was obtained.

[0019]

Example 1 In this example, as shown in FIGS. 2A to 2E, a bottom gate type TFT circuit using amorphous silicon formed on a glass substrate 201 is formed. This is an example.
The configuration of this embodiment can be applied to the switching element of the pixel electrode of the active type liquid crystal display device.

FIG. 2 shows a cross-sectional view of the manufacturing process of this embodiment. First, a 2000-Å-thick silicon nitride base film 202 was formed on a substrate (Corning 7059) 201 by a plasma CVD method. Ammonia (NH ₃ ) and monosilane (SiH ₄ ) were used as source gases for CVD, and the substrate temperature during film formation was 300 to 450 ° C., for example 350 ° C. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then the
When gradually cooled down to a strain temperature or less at 1.0 ° C./min, a process involving a subsequent temperature rise (eg, including subsequent infrared light irradiation)
Substrate shrinkage is small and mask alignment is ready.
For Corning 7059 substrate, 1 to 620 to 660 ° C
After annealing for 4 hours, it is gradually cooled at 0.1 to 1.0 ° C./min, preferably 0.03 to 0.3 ° C./min, and 400 to 50.
It is recommended to take out when the temperature has dropped to 0 ° C.

Subsequently, by the sputtering method,
A film of aluminum having a thickness of 3000 to 8000 Å, for example 4000 Å, was formed. 0.2% in this aluminum
By weight Sc is included. As a material to be contained in this aluminum, a rare earth element of Group IIIa of the periodic table can be used. The content is 0.05 to
0.40% by weight, preferably 0.1-0.25% by weight
Can be

Then, the aluminum film was patterned and etched to form a gate electrode 203 and a gate wiring 204. A wet etching method was used for etching. Further, the surface of the aluminum electrode was anodized to form oxide layers 205 and 206 on the surface. This anodization is carried out at a pH of 6.9 containing tartaric acid of 1 to 5%.
It was carried out in the ethylene glycol solution of 7.1. On this occasion,
Anodization was performed by raising the voltage to 150V at 4V / min. The thickness of the obtained oxide layers 205 and 206 was 2000Å. (Fig. 2 (A))

After that, a thickness of 3 is formed by the plasma CVD method.
A 000Å silicon nitride film 207 was formed as a gate insulating film. Since an anodic oxide layer was formed on the surface of the gate electrode / wiring, no hillock was generated in this film formation.

Then, an intrinsic (I-type) amorphous silicon film 208 having a thickness of 200 to 500 Å, for example, 300 Å was formed by the plasma CVD method. Further, a silicon nitride film having a thickness of 1000 to 3000 Å, for example 2000 Å, was deposited thereon by a plasma CVD method. Then, after patterning, the silicon nitride film was etched with hot phosphoric acid to form an etching stopper 209. (FIG. 2 (B))

Thereafter, a microcrystalline N-type silicon film 210 having a thickness of 1000 to 4000 Å was formed by the plasma CVD method. In this embodiment, the thickness of the silicon film is 2000Å. As the raw material gas, a mixture of monosilane or disilane (Si ₂ H ₆ ) and 1 to 5 volume% of phosphine (PH ₃ ) was used. (FIG. 2C) In this step, a method of depositing an almost intrinsic amorphous silicon film and then adding an impurity imparting N conductivity type by an ion doping method (also referred to as a plasma doping method) is adopted. Good.

Then, the N-type silicon film 210 and the intrinsic silicon film 208 are dry-etched to form an active layer 211, a source 212 and a drain 213. Since the etching rate of the etching stopper 209 was sufficiently low, the active layer thereunder was not etched. (Fig. 2 (D))

Then, a TFT electrode / wiring 214 is formed of a metal material, for example, a multilayer film of titanium and aluminum,
215 was formed. The TFT 216 was completed as described above. At that time, the gate wiring 217 and the upper wiring 21
At the intersection 217 with 5, the dense anodic oxide coating 206 was present, and there was almost no short circuit between the wirings. Also in the TFT, there was no short circuit between the gate electrode and the active layer. (Fig. 2
(E))

[Embodiment 2] The manufacturing process of this embodiment is shown in FIG. First, as shown in FIG. 3A, a glass substrate (alumina silicate glass, Corning 1737 in this embodiment) 30 is used.
A silicon oxide film 302 having a thickness of 2000 Å was formed as a base film on 1 by a sputtering method or a plasma CVD method. Next, an amorphous silicon film made of N-type conductivity by doping with phosphorus
Plasma CVD method or low pressure thermal CVD to a thickness of 000Å
Film is formed by a method and is etched to form island regions 303,
304 was formed. This is the source / drain of the TFT.

After that, plasma CVD method or reduced pressure heat C
An amorphous silicon film 305 having a thickness of 500Å was formed by the VD method. Then, the silicon film is formed at 500 to 650 ° C., for example, 55
Crystallization was performed by performing thermal annealing at 0 ° C. for 4 hours. In the case of thermal annealing, JP-A-6-2441
As shown in 04, when a trace amount of a metal element such as nickel, cobalt, palladium, iron, or platinum is added, crystallization proceeds at a lower temperature in a shorter time due to the catalytic action of these metals. Next, a silicon oxide film 306 was formed as a gate insulating film by plasma CVD to a thickness of 3000 Å. Then, the aluminum film 307 is sputtered to 5000 Å
Was deposited to a thickness of. 0.25% by weight for aluminum film
Of scandium (Sc). (Fig. 3
(A))

Then, the aluminum film 307, the gate insulating film 306, and the silicon film 305 are etched to form a gate electrode 310, a gate insulating film 309, an active layer 308, and a gate wiring 311. The TFT having the structure of the present embodiment is a stagger type TFT as in the first embodiment, but differs in that it is a top gate type. Such a structure is called a forward stagger type. Particularly, in the structure of this embodiment, the etching of the active layer and the etching of the gate electrode are simultaneously performed, so that the number of steps can be reduced accordingly. (Fig. 3
(B))

After that, an anodic oxide film was formed on the surface of the gate electrode / wiring by the same anodic oxidation treatment as in Example 1. Anodization was performed under the same conditions as in Example 1, and in this example, the maximum voltage was raised to 150V. As a result, anodic oxide coatings 312 and 313 having a thickness of 2000 Å were formed. (Fig. 3 (C))

After that, a silicon oxide film 314 having a thickness of 3000 Å was formed as an interlayer insulator by the plasma CVD method. Further, contact holes were formed in the interlayer insulator, and metal wirings 315 and 316 containing aluminum as a main component were formed by a normal wiring forming technique. 1 to 5 atomic% of silicon or tungsten may be mixed in aluminum. The TFT 217 was formed as described above. At the intersection 318 between the gate wiring 311 and the wiring 316, there was no interlayer short circuit due to the existence of the anodic oxide coating 313. (FIG. 3D) By the above, a basic circuit could be formed. Since the structure of the forward staggered TFT of this embodiment is different from the normal one, its layer structure is shown in FIG. After that, an upper wiring, an interlayer insulating material, a transparent conductive film, and the like may be further formed.

[Third Embodiment] FIG. 4 shows the present embodiment. First, a silicon oxide film having a thickness of 1000 to 3000 Å was formed as a base oxide film 402 on a substrate (Corning 7059) 401. After that, an amorphous silicon film is deposited by plasma CVD or LPCVD to 300 to 5000 Å, preferably 500 to 1000 Å, and this is deposited at 550 to 600 ° C.
It was left to stand in a reducing atmosphere for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the crystallized silicon film was etched to form the island-shaped region 403. Further, a silicon oxide film 4 having a thickness of 700 to 1500 Å is formed on this by a sputtering method.
04 was formed.

Thereafter, aluminum having a thickness of 1000Å to 3 μm (0.1 to 0.3% by weight of Sc (scandium))
Film) was formed by a sputtering method. Then, a photoresist (for example, OFPR800 /
30 cp) was formed by spin coating. Before forming the photoresist, the thickness of 100 to 100
If a 1000 Å aluminum oxide film is formed on the surface, the adhesion to the photoresist is good, and the current leakage from the photoresist is suppressed, so that a porous anodic oxide is used in the subsequent anodizing step. It was effective in forming only on the side surface. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a gate electrode 405 and a gate wiring 406. Mask film 4 on the gate electrode / wiring
07 and 408 were left to remain. (Fig. 4 (A))

Further, a current is passed through the gate electrode / wiring in the electrolytic solution to anodize the side surface thereof to a thickness of 3000-60.
00Å, for example, 5000Å thick anodic oxide 409,
410 was formed. The anodic oxidation may be performed using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 10 to 30 V may be applied to the gate electrode. In this example, the oxalic acid solution (3
The voltage was set to 10 V in (0 ° C.) and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. Since the mask film was present, no anodic oxide was formed on the upper surface of the gate electrode / wiring. The anodic oxide thus obtained was porous unlike the barrier type anodic oxide. (Fig. 4 (B))

Next, the masks 407 and 408 were removed, and a current was applied again to the gate electrode / wiring in the electrolytic solution. This time, an ethylene glycol solution containing 3 to 10% tartar solution, boric acid, and nitric acid was used. Solution temperature is 1
A better oxide film was obtained at a temperature lower than room temperature around 0 ° C.
Therefore, barrier type anodic oxides 411 and 412 were formed on the upper and side surfaces of the gate electrode / wiring. The thickness of the anodic oxides 411 and 412 is proportional to the applied voltage, and an anodic oxide of 2000 Å was formed at an applied voltage of 150V.
(Fig. 4 (C))

After that, the silicon oxide film 404 was etched by the dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being deeply etched by sufficiently increasing the selection ratio of silicon and silicon oxide. For example, if CF ₄ is used as the etching gas, the anodic oxide is not etched, but only the silicon oxide film 404 is etched. Also,
Silicon oxide film 41 under the porous anodic oxides 409 and 410
3, 414 remained without being etched. (Fig. 4
(D))

Then, the porous anodic oxides 409 and 410 were etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the porous anodic oxide was etched, and the etching rate was about 600Å / min. The barrier type anodic oxide was barely etched and therefore the internal aluminum electrode was not etched. In addition, the gate insulating films 413 and 414 underneath remain as they are.

Then, by the ion doping method, T
The active layer 403 of the FT includes a gate electrode portion (that is, a gate electrode and an anodic oxide film around the gate electrode) and a gate insulating film 41.
3 is used as a mask to implant impurities in a self-aligned manner to form N-type high concentration impurity regions (source / drain regions) 414,
17, N type low concentration impurity regions 415 and 416 were formed. Phosphine (PH ₃ ) was used as the doping gas. In this example, doping was performed in two steps. In the first doping, the dose amount is 1 × 10 ¹⁴ ~
5 × 10 ¹⁵ atoms / cm ² , acceleration energy is 10-30
It was set to keV. In this doping, the exposed silicon is mainly doped with impurities, and the high-concentration impurity regions 41 are removed.
4,417 were formed.

In the second doping, the dose amount is 1 × 1.
0 ^{12 to} 5 × 10 ¹³ atoms / cm ² , acceleration energy is 60
˜90 keV. In this doping, the impurity was doped to a deep portion, and the impurity was added to the low concentration impurity regions 415 and 416 under the gate insulating film 413, which was not added in the first doping.
Such two-step doping does not lead to a substantial increase in the number of steps because it is only necessary to change the doping conditions without having to put the substrate in and out of the apparatus each time. (Fig. 4
(E)) Then, a KrF excimer laser (wavelength 248 nm,
A pulse width of 20 nsec) was applied to activate the impurity ions introduced into the active layer. This step may be by thermal annealing.

Finally, an interlayer insulator 418 is formed on the entire surface,
A silicon oxide film having a thickness of 3000 Å was formed by the CVD method. Then, contact holes are formed in the source / drain of the TFT, and aluminum wiring / electrodes 419 and 420 are formed.
Was formed. Further, hydrogen annealing was performed at 200 to 400 ° C. By the above, the TFT was completed. Also in the present example, at the intersection 421 between the gate wiring 406 and the wiring 420, there was no interlayer short circuit due to the presence of the anodic oxide coating 412. (Fig. 4 (F))

[0042]

[Effect] In the anodic oxidation step of the gate electrode / wiring, Sc is added to aluminum in an amount of 0.05 to 0.40% by weight, preferably 0.1 to 0.25% by weight. It is possible to prevent abnormal growth (hillock) of the region to be covered. (2) The controllability of the oxidized thickness can be improved. (3) A uniform oxide layer can be formed. (4) The heat resistance can be increased. (5) The laser resistance can be increased. (6) Especially when forming an offset region of the TFT, T
The characteristics of FT can be made uniform. (7) Since a dense oxide layer can be formed without abnormal growth, a thin oxide layer can be formed. It is possible to obtain such an effect.

[Brief description of drawings]

FIG. 1 shows a TFT having a structure in which a gate electrode / wiring is anodized.

FIG. 2 shows a manufacturing process of Example 1.

FIG. 3 shows a manufacturing process of Example 2.

FIG. 4 shows a manufacturing process of a third embodiment.

[Explanation of symbols]

 1 ... Gate electrode 2 ... Gate wiring 3, 4 ... Anodic oxide film 5 ... Gate insulating film 6 ... Active layer 7 ... Etching stopper 8 ... Source 9 ... Drain 10, 11 Wiring 21 ... Island semiconductor region 22 ... Drain 23 ... Source 24 ... Gate insulating film 25 ... Gate electrode 26 ...・ ・ ・ Gate wiring 27, 28 ・ Anodic oxide film 29 ・ ・ ・ ・ Interlayer insulator 30, 31 ・ Wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 9056-4M H01L 29/78 617 W

Claims (5)

[Claims] 1. An insulated gate semiconductor device, the gate electrode of which is made of a material containing aluminum as a main component, and an oxide layer obtained by oxidizing the material is formed on the surface of the gate electrode. , IIIa element is contained in an amount of 0.01% by weight to 1.0% by weight. 2. The element according to claim 1, wherein the group IIIa element is scandium (Sc) and the concentration thereof is 0.05% by weight or more.
A semiconductor device comprising 0.40% by weight. 3. The semiconductor device according to claim 1, wherein the insulating gate type semiconductor device is a bottom gate type. 4. The semiconductor device according to claim 1, wherein the insulating gate type semiconductor device is a top gate type. 5. The semiconductor device according to claim 1, wherein the oxide layer is formed by an anodic oxidation process.