JPH08139196A - Semiconductor element simulator - Google Patents

Abstract

PURPOSE: To predict the occurring states of a junction leakage current and a film exfoliation by extracting correlation data between a stress and the leakage current from memory means when stress information is supplied, and judging the state of the occurrence of the leakage current based on the information to judge the propriety of a semiconductor element. CONSTITUTION: A process simulator 1 simulates impurity distribution and shape based on manufacturing conditions, and a stress due to oxidation and deposition and residual defect due to the implantation. Judging means 3 judges whether junction leakage and film exfoliation occur or not based on the correlation data between the stress and the current or the exfoliation. In this case, if the leakage or the exfoliation is judged, altering means 5 alters the conditions of the oxidation and the deposition. Electric characteristics calculating means decides whether the result of a device simulation coincides with desired electric characteristics or not. if it is coincident, it becomes optimum manufacturing conditions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device simulation apparatus which utilizes information obtained by a process simulation to optimize manufacturing conditions.

[0002]

2. Description of the Related Art LSI to be Solved
With the miniaturization of semiconductor devices, the process is becoming lower in temperature and more complicated, and as a result, the influence of stress and residual defects generated in the semiconductor substrate on the electrical characteristics of the device and thus the yield cannot be ignored. For example, stress generated during sidewall oxidation of the gate electrode forms a dislocation loop inside the substrate and causes a junction leak, or residual defects due to source / drain implantation increase the junction leak. Alternatively, when polycide is formed in the gate electrode portion, stress is generated due to the difference in the coefficient of thermal expansion of each film, causing film peeling and reducing the yield. At present, there is no quantitative model that expresses the above-mentioned relationship between stress and defects and electrical characteristics, and trial and error are repeated individually to optimize manufacturing conditions. However, as the process becomes complicated, such a conventional method has a problem that the development period becomes long. The present invention has been made to solve such problems, and an object of the present invention is to provide a semiconductor device simulation apparatus capable of predicting the conditions of occurrence of junction leakage current and film peeling. A further object of the present invention is to provide a semiconductor device simulation apparatus capable of easily obtaining optimum manufacturing conditions in manufacturing a semiconductor device.

[0003]

Means for Solving the Problem and Its Action The present invention is based on a storage means for storing correlation data between stress and a junction leak current generated during a manufacturing process of a semiconductor device, and a given manufacturing condition. A process simulation device for calculating stress, connected to the storage device and the process simulation device, and when the information related to the stress is supplied from the process simulation device, the correlation data between the stress and the junction leakage current is stored from the storage means. And a determination unit that determines the quality of the semiconductor element by determining the state of occurrence of the junction leak current based on the stress information.

The present invention further includes a storage means for storing correlation data between stress and film peeling occurring during a semiconductor element manufacturing process, and a process simulation device for calculating stress based on given manufacturing conditions. It is connected to the storage device and the process simulation device, and when the information related to the stress is supplied from the process simulation device, the correlation data between the stress and the film peeling is extracted from the storage means and the film peeling based on the stress information. And a determination unit that determines the quality of the semiconductor element by determining the occurrence state.

Further, the present invention provides a storage means for storing correlation data between a defect and a junction leak current generated during a semiconductor element manufacturing process, and a process simulation device for calculating the defect based on given manufacturing conditions. Connected to the storage device and the process simulation device, when the process simulation device supplies information on the defect, the correlation data between the defect and the junction leak current is extracted from the storage means, and the junction is detected based on the defect information. And a determination means for determining the quality of the semiconductor element by determining the state of occurrence of the leakage current.

Further, the present invention provides a process simulation device for calculating an impurity distribution and a shape based on given manufacturing conditions, and a process simulation device connected to the process simulation device to supply information on the impurity distribution and the shape. Electrical characteristic calculation means for calculating electrical characteristics of the semiconductor element based on the information of the impurity distribution and shape and determining whether or not the electrical characteristics match a desired value.

With this configuration, the judging means is
The state of occurrence of the leak current or the film peeling is determined based on the information on the stress obtained from the process simulation device and the information on the leak current or the film peeling obtained from the storage means. Further, the judging means judges the state of occurrence of the leak current based on the information on the defect obtained from the process simulation device and the information on the leak current obtained from the storage means. Therefore, the determination means, the process simulation device, and the storage means act so as to be able to predict the state of occurrence of junction leakage current and film peeling.

Further, when the judgment means is connected to the judgment means and the judgment means judges the occurrence of the junction leak current or the film peeling, the manufacturing is performed in order to reduce the stress or the defects in order to prevent the generation of the junction leakage current or the film peeling. A changing means for changing the condition may be provided.

Further, a changing means may be provided which is connected to the electric characteristic calculating means and changes the manufacturing condition so as to make the electric characteristics match when the electric characteristic calculating means determines that the electric characteristics do not match. .

With this configuration, the changing means is
When the determination means and the electrical characteristic calculation means determine the occurrence of leakage current, the occurrence of film peeling, or the mismatch of electrical characteristics, the occurrence of leakage current, the occurrence of film peeling or the mismatch of electrical characteristics is corrected. To change the manufacturing conditions. Therefore, the changing means acts to easily obtain the optimum manufacturing conditions in manufacturing the semiconductor element.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device simulation apparatus of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the semiconductor device simulation apparatus of this embodiment. The process simulation apparatus 1 models the steps of ion implantation, diffusion, oxidation, etc. in the semiconductor element manufacturing process to simulate the impurity distribution, shape, and the behavior of residual defects due to stress and implantation generated during the oxidation and deposition steps. And uses existing equipment. The storage unit 2 stores correlation data between the stress and the junction leak current generated during the manufacturing process of the semiconductor device, which is obtained in advance from the results of experiments and process simulations.
The correlation data between the stress and the film peeling and the correlation data between the defect and the junction leak current are stored. Specifically, in the correlation data between the stress and the junction leakage current or the film peeling, the situation of the leak occurrence due to the stress, the experiment investigating the situation of the film peeling,
A correlation database as shown in FIG. 3 is created based on the result (stress) of the process simulation considering stress under the same conditions. In addition, the correlation data between the above-mentioned defects and junction leakage currents are based on the results of an experiment investigating the state of leakage generation due to defects and the results of process simulation (defects) considering defects under the same conditions. Create a correlation database such as 4. The storage means 2 may store only a part of the above-mentioned correlation data.

The judgment means 3 is connected to the process simulation device 1 and the storage means 2 and performs the following two operations. That is, the judging means 3 receives the information on the stress from the process simulation apparatus 1, while reading the correlation data between the stress and the leak current or the film peeling from the storage means 2, and supplies the information supplied from the process simulation apparatus 1. The state of occurrence of junction leak and film peeling is judged based on the stress information and the above correlation data. Also, the judging means 3
Receives the information on the residual defect from the process simulation apparatus 1, while reading the correlation data between the defect and the leak current from the storage means 2, and the information on the residual defect and the correlation data supplied from the process simulation apparatus 1. The state of occurrence of the junction leak due to the defect is determined based on the above.

The electrical characteristic calculation means 4 is connected to the process simulation apparatus 1, reads the information on the above-mentioned impurity distribution and shape from the process simulation apparatus 1, simulates the electrical characteristics of the semiconductor element, and confirms that the values match the desired values. Determine whether The changing means 5 is connected to the judging means 3 and the electrical characteristic calculating means 4 and performs the following operation. That is, when the determination unit 3 determines that the junction leak or film peeling due to the stress is generated, or when the defect causes the junction leakage to occur, or the electrical characteristic calculation unit 4 determines the electrical characteristic. When the mismatch is determined, the changing unit 5 changes the manufacturing condition of the semiconductor element so that the occurrence of the junction leak and the mismatch of the electrical characteristics are eliminated. Then, preferably, the changed manufacturing conditions are fed back to the process simulation device 1.

The operation of the semiconductor device simulation apparatus configured as described above will be described below with reference to FIG. In step (indicated by “S” in FIG. 2) 1,
As the setting of the initial condition, an arbitrary manufacturing condition of the semiconductor element is supplied to the process simulation device 1, and further desired electric characteristics are supplied to the electric characteristic calculation means 4. In step 2, the process simulation apparatus 1 simulates the impurity distribution and shape based on the above manufacturing conditions, and also simulates stress due to oxidation and vapor deposition and residual defects due to implantation.

In step 3, it is the result of simulation by the process simulation device 1,
Information on stress, that is, information on the position where stress is concentrated and its magnitude is supplied to the judging means 3. Further, the judging unit 3 reads out the correlation data between the stress and the junction leak current or the film peeling from the stress database corresponding to the storage unit 2. Whether the junction leak or the film peeling occurs is determined based on the above-mentioned information on the position where the stress is concentrated and the magnitude thereof and the correlation data between the stress and the junction leak current or the film peeling described above. In Step 4, if it is determined that the junction leak or the film peeling has occurred in the operation of the determination unit 3 in Step 3, the changing unit 5 sets the conditions of the oxidation and the vapor deposition to reduce stress. change. After the change, return to step 2.

In step 6, if there is no junction leak or film peeling in step 3, the judging means 3
Of the simulation results in step 2, information regarding the residual defect, that is, information regarding the position and size of the residual defect is read, and further, correlation data between the above-mentioned residual defect and the junction leakage current is obtained from the defect database corresponding to the storage unit 2. read out. Based on the above-mentioned information about the position and size of the residual defect and the correlation data between the residual defect and the junction leak current,
When it is determined in step 7 that the junction leak has occurred in step 7, the changing means 5 determines whether the implantation condition or the subsequent annealing condition is defective. Change so that After the change, return to step 2.

In step 9, if it is determined in step 6 that there is no junction leak, the electrical characteristic calculation means 4
Of the simulation results in step 2,
Read the information on the impurity distribution and shape and perform device simulation. And in step 10,
The electrical characteristic calculation means 4 determines whether or not the result of the device simulation matches the desired electrical characteristic. As a result, when it is determined that the electrical characteristics do not match, the changing unit 5 changes the implantation, oxidation, and diffusion conditions in the direction in which the electrical characteristics match in step 11. After changing, go back to step 2. On the other hand, if the electrical characteristics match in step 10, it means that the manufacturing conditions initially set in step 1 are optimum manufacturing conditions that are free from the effects of stress and defects and that satisfy the desired electrical characteristics. become.

As described above, according to the semiconductor device simulation apparatus of this embodiment, the following effects can be obtained. Correlation data between stress and junction leakage current,
By using the stress database that stores the correlation data between the stress and the film peeling, it is possible to easily determine the occurrence of the junction leak current or the film peeling due to the stress from the result of the process simulation.

Further, by using the defect database which stores the correlation data between the defect and the junction leak current, it is possible to easily judge from the result of the process simulation whether or not the junction leak current is caused by the defect.

Further, when the occurrence of the junction leakage current or the film peeling or the occurrence of the junction leakage current due to a defect is confirmed by the judgment of the situation of the occurrence of the junction leakage current or the film peeling due to the stress as described above. In addition, it is possible to optimize the manufacturing conditions by changing the manufacturing conditions so that there is no influence of stress and defects and the desired electric characteristics are satisfied.

[0021]

As described above in detail, according to the inventions of claims 1 to 4, the correlation data between the stress and the junction leak current generated during the manufacturing process of the semiconductor element and the correlation data between the stress and the film peeling. , And the correlation data between the defect and the junction leakage current are stored in advance, the information about the stress or the information about the defect is sent from the process simulation device, so that the junction leakage current or the film peeling based on the correlation data is transmitted. It is possible to determine the occurrence status of.

Further, according to the inventions of claims 5 and 6,
When a junction leak current, film peeling, or a mismatch in electrical characteristics occurs, there is no influence of stress or defects because there is a change means to correct the mismatch in junction leak current, film peeling or an electrical characteristic, and the desired It is possible to optimize the manufacturing conditions so as to satisfy the electric characteristics of.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor device simulation apparatus of the present invention.

FIG. 2 is a flowchart showing an operation of the semiconductor device simulation apparatus shown in FIG.

FIG. 3 is a diagram showing an example of a stress database in a storage unit of the semiconductor device simulation apparatus shown in FIG.

FIG. 4 is a diagram showing an example of a defect database in a storage unit of the semiconductor device simulation apparatus shown in FIG.

[Explanation of symbols]

1 ... Process simulation device, 2 ... Storage means, 3
... judgment means, 4 ... electric characteristic calculation means, 5 ... change means.

Claims (6)

[Claims] 1. A storage means for storing correlation data between a stress and a junction leak current generated during a manufacturing process of a semiconductor device, a process simulation device for calculating a stress based on given manufacturing conditions, and the above storage. Connected to the device and the process simulation device, and when the information related to the stress is supplied from the process simulation device, the correlation data between the stress and the junction leakage current is extracted from the storage means, and the junction leakage current is based on the stress information. A semiconductor element simulation device, comprising: a determination unit configured to determine a situation of occurrence of a semiconductor element and determine whether the semiconductor element is good or bad. 2. Storage means for storing correlation data between stress and film peeling occurring during a semiconductor element manufacturing process, a process simulation device for calculating stress based on given manufacturing conditions, and the storage device. And, when the information related to the stress is supplied from the process simulation device connected to the process simulation device, the correlation data between the stress and the film peeling is extracted from the storage means and the situation of the film peeling based on the stress information. A semiconductor element simulation device comprising: a determination unit that determines whether the semiconductor element is good or bad. 3. A storage means for storing correlation data between a defect and a junction leak current generated during a semiconductor device manufacturing process, a process simulation device for calculating a defect based on given manufacturing conditions, and the above storage. Connected to the device and the process simulation device, when the information regarding the defect is supplied from the process simulation device, the correlation data between the defect and the junction leakage current is extracted from the storage means and the junction leakage current based on the defect information is extracted. A semiconductor element simulation device comprising: a determination unit that determines a generation state and determines whether a semiconductor element is good or bad. 4. A process simulation device for calculating an impurity distribution and a shape based on given manufacturing conditions, and a process simulation device connected to the process simulation device to supply information on the impurity distribution and the shape from the process simulation device. An electrical characteristic calculation means for calculating the electrical characteristic of the semiconductor element based on the information of the distribution and the shape and determining whether or not the electrical characteristic matches a desired value,
A semiconductor element simulation device comprising: 5. The manufacturing method for reducing the stress or the defect in order to prevent the occurrence of the junction leak current or the film peeling when the judgment means is connected to the judging means and judges the occurrence of the junction leak current or the film peeling. 4. A changing means for changing the condition, comprising:
5. The semiconductor element simulation device according to any one of 1. 6. The changing means, which is connected to the electric characteristic calculating means and changes the manufacturing condition so as to make the electric characteristics coincide when the electric characteristic calculating means determines that the electric characteristics do not coincide with each other. The semiconductor device simulation apparatus described.