JPH08139174A - Semiconductor device - Google Patents

Abstract

PURPOSE: To suppress generation of a crack due to difference between coefficients of thermal expansion even in the case where a semiconductor layer on a substrate is of different kind from that of the substrate, with regard to semiconductor devices wherein different kinds of semiconductor layers formed on the semiconductor substrate are separated into a plurality of device region layers by grooves. CONSTITUTION: This device comprises a plurality of device region layers 22 consisting of semiconductor layers formed on a substrate 21, grooves 23 formed in regions between adjacent device region layers 22, and connecting parts 24 for connecting the adjacent device regions 22 with partial regions, and a plurality of connecting parts 24 are arranged such that they are bent at one or more positions or they are interrupted by the grooves 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a heterogeneous semiconductor layer formed on a semiconductor substrate is separated into a plurality of element region layers by grooves. In recent years, semiconductor integrated circuit devices and optical devices are required to be low in cost and highly integrated. Therefore, it is often necessary to stack different kinds of semiconductor layers on the semiconductor substrate. In this case, the semiconductor substrate and the different semiconductor layer often have different coefficients of thermal expansion, and it is desired to take measures against the occurrence of cracks or the like in the semiconductor layer.

[0002]

2. Description of the Related Art FIGS. 6 (b) and 6 (c) are sectional views of an infrared detecting element according to a conventional example, and FIG. 6 (a) is a plan view showing a plurality of element region layers formed on a semiconductor substrate. . Figure 6
The cross-sectional views of the element region layers of (b) and (c) are shown in FIG.
This corresponds to a cross-sectional view taken along the line AA and the line BB in (a).

A plurality of element region layers 2 made of HgCdTe layers are formed on a silicon substrate 1. Then, in order to prevent diffusion of carriers generated by light irradiation to the adjacent element region layer, the adjacent element region layer 2 is separated by the groove 3. In this case, a partial region between the adjacent element region layers 2 is formed of HgC as the connecting portion 4 of the common electrode of the element region layer 2.
The dTe film is left as it is.

As shown in FIG. 6A, the groove 3 is formed in a portion corresponding to the side of the element region layer 2 having a square shape or a rectangular shape, and the connecting portion 4 is a central portion of the side of each element region layer 2. It is provided in. Therefore, a continuous region where the element region layer 2 and the connecting portion 4 are not bent and are continuous in a straight line exists along a straight line that crosses the central portion of the element region layer 2. Further, as shown in FIG. 6B, the element region layer 2 includes a p-type layer 2a and a p-type layer 2a.
An n-type region layer 2b is formed in the inner region of the upper surface layer. Further, the protective insulating film 5 is formed so as to cover the element region layer 2, and the extraction electrode 6 is n-typed through the opening 5 a of the protective insulating film 5.
It is connected to the mold region layer 2b.

Further, as shown in FIG. 6C, the connecting portion 4 is formed by using the p-type layer 2a in the peripheral portion of each element region layer 2 as a common electrode.
Thus, all the element region layers 2 are electrically connected to each other, and are connected to the common p-type extraction layer 7 formed on the silicon substrate 1 around the chip. The p-type lead layer 7 is formed with a lead electrode 8 for connecting to a signal processing circuit.

Further, a signal processing circuit such as a CCD is formed on the element region layer 2 through the extraction electrodes 6 and 8 in order to detect the position and intensity of the received light applied to the element region layer 2 and perform signal processing. The semiconductor chips 9 thus formed are stacked upside down.

[0007]

However, the above infrared detector is cooled to the liquid nitrogen temperature (77K) in order to suppress the dark current in order to improve the sensitivity during use, and is kept at room temperature when not in use. To be done. When such a temperature cycle is applied, since the silicon substrate 1 and the HgCdTe layer 2 have different thermal expansion coefficients, the HgCdTe layer 2 that is continuous in a straight line
A crack may occur in the continuous region of the CdTe layer 2.

Therefore, there is a problem in that the resistance between the input and output terminals increases and a sufficient photocurrent cannot be obtained, or the photocurrent cannot be detected at all. The present invention was created in view of the problems of the above-mentioned conventional example, and even when the semiconductor layer on the substrate is of a type different from the substrate, it is possible to suppress the occurrence of cracks due to the difference in thermal expansion coefficient. It is an object to provide a semiconductor device.

[0009]

The above-mentioned problems are as follows. First, a plurality of element region layers made of semiconductor layers formed on a substrate and isolation trenches formed in a region between adjacent element region layers. And a connecting portion that connects the adjacent element region layers to each other in a partial region, and the arrangement of the plurality of connecting portions is bent at one or more places, or is interrupted halfway by the groove. Achieved by the semiconductor device,
In the semiconductor device according to the first invention, the connecting portion is integrally formed with the element region layer by the semiconductor layer. Thirdly, the connecting portion is A fourth aspect of the present invention is achieved by the semiconductor device according to the first aspect of the present invention, which is formed of a polycrystalline semiconductor layer, and fourthly, the arrangement of the plurality of connecting portions is bent at a length between the adjacent connecting portions. No, and is continuous without interruption due to the groove, or is continuous without interruption due to the groove within a length including the two element region layers and one of the connecting portions. The present invention is achieved by the semiconductor device according to any one of the third inventions, and fifthly, the plurality of element region layers are electrically connected by the connecting portion. According to the semiconductor device described in And sixth, the plurality of device region layers each have a P-type conductive layer and an N-type conductive layer, and the connection portion connects the P-type conductive layer and the N-type conductive layer of the plurality of device region layers. One of the above is electrically connected to the semiconductor device according to the fifth aspect of the present invention. Seventh, the semiconductor layer is a compound semiconductor layer made of mercury-cadmium-tellurium. An eighth aspect of the present invention is achieved by the semiconductor device according to the sixth aspect of the present invention, and eighthly, a first semiconductor substrate having a signal processing circuit formed thereon is laminated on the element region layer via an electrode. According to a seventh aspect of the present invention, there is provided a semiconductor device according to the seventh aspect of the present invention, and ninthly, the substrate is a high-resistance second semiconductor substrate. Achieved by the described semiconductor device Tenth, the substrate is a P-type or N-type conductivity type third semiconductor substrate, and the source / drain region layer of the field effect transistor is formed on the third semiconductor substrate, and the source / drain region layer is formed. The drain region layer is connected to one of the P-type conductive layer and the N-type conductive layer of the element region layer by a conductive-type region layer formed on the third semiconductor substrate. A sixth or seventh aspect of the present invention, which is achieved by the semiconductor device according to the sixth or seventh aspect, and eleventh, wherein the second or third semiconductor substrate is a silicon substrate. Achieved by semiconductor devices.

[0010]

According to the semiconductor device of the present invention, the semiconductor device has a groove formed in a region between adjacent element region layers and a connecting portion connecting between the adjacent element region layers. Is bent at one or more places, or is interrupted by a groove. Therefore, since the length of the continuous region where the element region layer and the connecting portion are continuous on a straight line is limited, the region where strain is generated due to the difference in thermal expansion coefficient is limited, and the increase in strain is suppressed.

For this reason, the length of the continuous region is less than the length at which cracks due to strain do not occur, for example, the length between adjacent connecting portions or the length including two element region layers and one connecting portion. By so doing, it is possible to effectively suppress the occurrence of cracks in the semiconductor layer.

[0012]

【Example】

(1) Description of Infrared Detector According to First Embodiment of the Present Invention FIGS. 1B and 1C are sectional views showing an infrared detector according to a first embodiment of the present invention, and FIG. FIG. 8A) is a plan view showing element region layers formed on a semiconductor substrate and separated by separation grooves. The cross-sectional views of the element region layers in FIGS. 1B and 1C correspond to the cross-sectional views taken along the lines CC and DD in FIG. 1A, respectively.

In FIGS. 1B and 1C, reference numeral 21 is a silicon substrate (substrate) having a high resistance in which impurities imparting a conductivity type are not introduced. A p-type mercury-cadmium-tellurium layer (HgCdTe layer; element region layer) 22 having a thickness of about 20 μm is formed on the silicon substrate 21. Adjacent HgC of carriers generated by light irradiation
In order to prevent diffusion into the dTe layer 22, adjacent HgC
The dTe layers 22 are separated from each other by a separation groove 23.
The width of the separation groove 23 is 5 μm, and the pitch is 50 μm in both the vertical and horizontal directions.

A plurality of element region layers 22 are formed on the silicon substrate 21. Each element region layer 22
N in the inner region of the p-type layer 22a and the upper surface layer of the p-type layer 22a.
The mold region layer 22b is formed. In addition, as shown in FIG. 1A, a partial region between the adjacent element region layers 22 serves as a connecting portion 24 without forming the separation groove 23 and is a p-type HgCdT.
The e-layer 22 is left as it is. Then, all the element region layers 22 are electrically connected to each other through the connecting portion 24 by using the p-type layer 22a around the element region layer 22 as a common electrode.

Further, there is a continuous region in which the element region layer 22 and the connecting portion 24 are not bent, and exist continuously in a straight line and without interruption due to the separation groove 23. Unlike the conventional example, this continuous region does not extend over the entire chip region, but is divided by the separation groove 23 into an appropriate length. In the case of the embodiment, the length of the continuous region is such that cracks due to strain do not occur, for example, the length L1 or 2 between two connecting portions.
The length L2 includes one element region layer 22 and the connecting portion 24.

Further, as shown in FIG. 1B, a protective insulating film 25 made of a ZnS film having a thickness of about 0.4 μm is formed so as to cover the element region layer 22, and the protective insulating film 25 is drawn out through an opening 25a. The electrode 26 is connected to the n-type region layer 22b. Further, all the device region layers 22 in the chip are p-type layers 22.
They are electrically connected to each other by a connecting portion 24 using a as a common electrode, and are connected to a common p-type extraction layer 27 formed on the silicon substrate 21 around the chip. The p-type lead layer 27 is formed with a lead electrode 28 for connecting to a signal processing circuit.

The element region layer 22 is formed from the silicon substrate side.
The extraction electrodes 26, 28 are provided on the element region layer 22 in order to detect the position and intensity of the received light applied to the device and perform signal processing.
Semiconductor chips 29 on which a signal processing circuit such as a CCD is formed are stacked in an upside down manner. next,
FIG. 2 shows the results of investigation of the current-voltage characteristics and the differential resistance-voltage characteristics of the diode between the n-type region layers 22b / p-type layers 22a in the plurality of element region layers 22 formed on the silicon substrate 21. The left vertical axis represents the current density (A / cm ² ), and the right vertical axis represents the differential resistance R normalized by the area of the n-type region layer.
It represents dA (Ωcm ² ). The horizontal axis represents the applied voltage (V).

As shown in FIG. 2, the differential resistance, the leakage current, and the forward voltage did not exhibit the characteristics showing an increase in resistance due to cracks or an increase in leakage current. Next, a temperature cycle test was conducted on the sample having the isolation pattern of the element region layer of the first embodiment of the present invention. A plan view and a sectional view taken along line EE of the used test sample are shown in FIG. For comparison, a similar test was performed on the comparative sample. FIG. 3 is a plan view and a cross-sectional view taken along line FF of the comparative sample.
It shows in (b). As shown in FIGS. 3A and 3B, both the test sample and the comparative sample had a silicon substrate with a thickness of 300 μm.
A HgCdTe layer 102a having a film thickness of 20 μm was laminated on 101a, and a chip size of 5 mm was used.

In the test sample and the comparative sample, the separation grooves 103a, 10a
The arrangement of 3b is different. That is, the test sample has the same arrangement as that shown in FIG. 1A, and the arrangement of the plurality of connecting portions 104a is continuous without being bent at the length L1 between the adjacent connecting portions 104a and without being interrupted by the separation groove 103a. Alternatively, it is continuous without interruption by the separation groove 103a at a length L2 including the two element region layers 102a and one connecting portion 104a. On the other hand, in the arrangement of the separation groove 103b of the comparative sample, the connection portions 104b are formed at the four corners of the device region layer 102b, and the device region layer 10 is formed over the entire chip along the diagonal line.
There is a continuous area of 2b and the connecting portion 104b. However, separation groove
The pitch of 103a and 103b is the same in both the test sample and the comparative sample, and is 1.1 mm in the vertical direction and 0.8 mm in the horizontal direction.

When the temperature cycle of room temperature (about 25 ° C.) and liquid nitrogen temperature (about 77 K) was repeated 5 times with respect to the test sample and the comparative sample, no crack was generated in the test sample. On the other hand, in the comparative sample, as shown in FIG. 3B, many cracks were generated in the oblique direction along the continuous region. As described above, in the infrared detection device according to the first embodiment of the present invention, as shown in FIG.
It has an isolation groove 23 formed in a region between the adjacent element region layers 22 and a connecting portion 24 connecting the adjacent element region layers 22. The plurality of connecting portions 24 are arranged in two connecting portions 24. Bending after a straight line with a length of L1 or 2
It is separated by the separation groove 23 after being continuous in a straight line with a length L2 including one element region layer and one connecting portion.

Therefore, the length L1 of the continuous region where the element region layer 22 and the HgCdTe layer of the connecting portion 24 are continuous in a straight line.
Alternatively, since L2 is limited, a region where strain is generated due to a difference in thermal expansion coefficient is limited, and an increase in strain is suppressed. Therefore, by setting the length L1 or L2 of the continuous region to a length that does not cause cracks due to strain, the occurrence of cracks in the HgCdTe layer 22 can be effectively suppressed.

(Other Embodiments) In the first embodiment, only one example is described as the planar shape of the element region layer 22 and the arrangement of the isolation trenches 23, but as shown in FIG.
The planar shape of the gCdTe layer (element region layer) 22 may be circular, or the separation groove 23 may be arranged as shown in FIG. 4B. Besides, various arrangements to which the present invention can be applied are conceivable. In this case, the length of the continuous region is set to be equal to or less than the length at which cracks due to strain do not occur.
It is possible to effectively suppress the generation of cracks in the dTe layer 22.

Further, although the present invention is applied to the combination of the silicon substrate 21 and the element region layer 22 composed of the HgCdTe layer, it may be applied to other combinations of the substrate and the semiconductor layer having different thermal expansion coefficients. Further, it is possible to apply a combination of these to semiconductor devices other than the infrared detection device. Further, as the substrate 21, an insulating layer,
A metal layer or a semiconductor layer may be used. (2) Description of Infrared Detector According to Second Embodiment of the Present Invention FIG. 5 is a sectional view showing an infrared detector according to a second embodiment of the present invention. The isolation trench and the plurality of element region layers are arranged in the same manner as in the plan view of FIG.

The second embodiment differs from the first embodiment in that a low-concentration n-type silicon substrate 21a is used as a semiconductor substrate, and a signal processing circuit such as a CCD is adjacent to the element region layer 22c. It is formed on the silicon substrate 21a. Further, the signal processing circuit is provided in the element region layer 22.
c Since it is formed on the underlying silicon substrate 21a, the extraction electrode is not used, and instead the silicon substrate 21a is used.
A p-type region layer 30 for connecting the p-type region layer 22d of the device region layer 22c and the source / drain region layer 31a of the signal processing circuit therein.
Is also provided, which is also different from the first embodiment.
The p-type region layer 22d of the element region layer 22c is selectively p-typed in the central region of the patterned n-type HgCdTe layer.
It is formed by introducing a type impurity.

In FIG. 5, another reference numeral 32 is an insulating film which insulates the p-type region layer 30 from the n-type layer 22e of the element region layer 22c, 33 is a gate insulating film formed on the silicon substrate 21a, and 34a. Is a gate electrode, 34b is a gate wiring layer, 35a,
35b is a source / drain electrode / wiring layer, and 36 is a source / drain electrode.
A cover insulating film that covers the drain electrodes / wiring layers 35a and 35b, and 27a is an n-type layer that is connected to the n-type layer 22e of the plurality of element region layers 22c serving as a common electrode through the connecting portion between the adjacent element region layers 22c. The contact layer, 37 is formed on the surface layer of the silicon substrate 21a and is an n ⁺ type wiring region layer for connecting the n-type contact layer 27a to the signal processing circuit, and 25a covers the n-type contact layer 27a and the element region layer 22c. Is a protective insulating film made of ZnS.

In the infrared detector, the signal processing circuit is formed on the silicon substrate 21a at the bottom of the isolation groove 23a between the element region layers 22c, for example. At this time, the gate wiring layer
34b and the source / drain electrode / wiring layers 35a, 35b are connected to the gate wiring layer and the source / drain electrode / wiring layer of the adjacent transistor passing above or below the connecting portion covered with the protective insulating film 25a.

As described above, according to the second embodiment, as in the first embodiment, the arrangement of the connecting portions does not bend at the length between the adjacent connecting portions, and is interrupted by the separation groove 23a. However, since it is continuous or is interrupted by the separation groove 23a in a length including the two element region layers 22c and one connecting portion, the same operational effect as that of the first embodiment is obtained. In addition, since the signal processing circuit is formed on the silicon substrate 21a on which the element region layer 22c is laminated, it is not necessary to separately prepare a silicon substrate on which the signal processing circuit is formed, and the step of laminating the silicon substrate is unnecessary. Becomes

[0028]

As described above, according to the semiconductor device of the present invention, the semiconductor device has the groove formed in the region between the adjacent element region layers and the connecting portion for connecting the adjacent element region layers, Since the arrangement of the plurality of connecting portions is bent at one or more places or is interrupted in the middle by the groove, the length of the continuous region where the element region layer and the connecting portion are continuous is limited, and the strain due to the difference in thermal expansion coefficient The generation area is limited, and the increase in strain is suppressed.

Therefore, by setting the length of the continuous region to be equal to or less than the length at which cracks due to strain do not occur, it is possible to effectively suppress the occurrence of cracks in the semiconductor layer.

[Brief description of drawings]

FIG. 1 is a plan view showing an arrangement of a separation groove and an element region layer on a chip according to a first embodiment of the present invention, and a sectional view showing an infrared detection device.

FIG. 2 is a characteristic diagram showing current-voltage characteristics and differential resistance measurement results of pn junctions of element region layers separated by the arrangement of the separation grooves according to the first example of the present invention.

3A and 3B are a plan view and a cross-sectional view of a sample used for a temperature cycle of an element region layer on a silicon substrate, which is separated by the arrangement of separation grooves according to the first embodiment of the present invention.

FIG. 4 is a plan view showing another arrangement of the isolation trench and the element region layer on the chip according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing an infrared detection device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing an arrangement of a separation groove and an element region layer on a chip according to a conventional example, and a cross-sectional view showing an infrared detection device.

[Explanation of symbols]

 21, 101a Silicon substrate (substrate), 22, 22c, 102a Element region layer (HgCdTe layer), 22a p-type layer, 22b n-type region layer, 22d, 30 p-type region layer, 22en-type layer, 23, 23a, 103a isolation groove, 24, 104a connecting portion, 25, 25a protective insulating film, 26, 28 extraction electrode, 27 p-type contact layer, 27a n-type contact layer, 29 semiconductor chip, 31a, 31b source / drain region layer, 32 insulation Film, 33 gate insulating film, 34a gate electrode, 34b gate wiring layer, 35a, 35b source / drain electrode / wiring layer, 36 cover insulating film.

Claims (11)

[Claims] 1. A plurality of element region layers made of a semiconductor layer formed on a substrate, a groove formed in a region between the adjacent element region layers, and a portion of the adjacent element region layers. A semiconductor device having a connecting portion that connects with each other, wherein a plurality of the connecting portions are arranged in a line at one or more places or are interrupted in the middle by the groove. 2. The semiconductor device according to claim 1, wherein the connecting portion is formed integrally with the element region layer by the semiconductor layer. 3. The semiconductor device according to claim 1, wherein the connecting portion is formed of a polycrystalline semiconductor layer. 4. The array of the plurality of connecting portions is continuous without being bent by the length between the adjacent connecting portions and without being interrupted by the groove, or two element region layers and one connecting portion. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a length equal to or less than, and is continuous without being interrupted by the groove. 5. The semiconductor device according to claim 1, wherein a plurality of the element region layers are electrically connected by the connecting portion. 6. The plurality of element region layers each have a P-type conductive layer and an N-type conductive layer, and each of the P-type conductive layer and the N-type conductive layer of the plurality of element region layers is formed by the connecting portion. The semiconductor device according to claim 5, wherein one of them is electrically connected. 7. The semiconductor device according to claim 6, wherein the semiconductor layer is a compound semiconductor layer made of mercury-cadmium-tellurium. 8. The semiconductor device according to claim 7, wherein a first semiconductor substrate on which a signal processing circuit is formed is laminated on the element region layer via an electrode. 9. The semiconductor device according to claim 1, wherein the substrate is a high-resistance second semiconductor substrate. 10. The substrate is a P-type or N-type conductive type third semiconductor substrate, and a source / drain region layer of a field effect transistor is formed on the third semiconductor substrate, and the source / drain is formed. The region layer is a conductive type region layer formed on the third semiconductor substrate, and the P type conductive layer and the N type conductive layer of the element region layer are formed.
The semiconductor device according to claim 6, wherein the semiconductor device is connected to either one of the mold conductive layers. 11. The semiconductor device according to claim 9, wherein the second or third semiconductor substrate is a silicon substrate.