JPH08139148A - Inspection method of wire bondability of conductor circuit - Google Patents

Inspection method of wire bondability of conductor circuit

Info

Publication number
JPH08139148A
JPH08139148A JP6276860A JP27686094A JPH08139148A JP H08139148 A JPH08139148 A JP H08139148A JP 6276860 A JP6276860 A JP 6276860A JP 27686094 A JP27686094 A JP 27686094A JP H08139148 A JPH08139148 A JP H08139148A
Authority
JP
Japan
Prior art keywords
conductor circuit
copper
wire
layer
bondability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6276860A
Other languages
Japanese (ja)
Inventor
Makoto Soma
誠 相馬
Atsushi Makino
篤 牧野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP6276860A priority Critical patent/JPH08139148A/en
Publication of JPH08139148A publication Critical patent/JPH08139148A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
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    • H01L2924/01029Copper [Cu]
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    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PURPOSE: To obtain a method for inspecting the wire bondability of a conductor circuit quickly. CONSTITUTION: Prior to wire bonding of a conductor circuit 1 and an electronic device, the surface of the conductor circuit 1 is subjected to quantitative analysis of element. When the conductor circuit 1 comprises an underlying layer 4 of copper, an intermediate layer 6 of palladium, and a surface layer 7 of gold, wire bondability of the conductor circuit 1 is decided based on the atomic concentration of copper component on the surface. When the conductor circuit 1 comprises an underlying layer of copper, a lower intermediate layer of nickel, an upper intermediate layer of palladium, and a surface layer of gold, wire bondability of the conductor circuit is decided based on the total atomic concentration of copper component on the surface and nickel component.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は導体回路と電子部品をワ
イヤーボンディングする前に、この導体回路のワイヤー
ボンディング性を検査する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inspecting the wire bondability of a conductor circuit before wire-bonding the conductor circuit to an electronic component.

【0002】[0002]

【従来の技術】セラミック基板や樹脂基板上に形成され
た導体回路と半導体チップ等の電子部品をワイヤーボン
ディングで接続する方法が多用されている。このワイヤ
ーボンディング性が正常に行われているか否かを検査す
る方法は、図5に示す如く、導体回路11と電子部品1
2をボンディングしたワイヤー13を所定の強度で引っ
張り、剥がれ発生の有無で判定している。しかし、この
方法ではワイヤーのボンディング性を評価するのに多数
のワイヤー、例えば500本程度のワイヤー13を1本
1本引っ張る必要があるため、判定にかなりの時間を要
している。
2. Description of the Related Art A method of connecting a conductor circuit formed on a ceramic substrate or a resin substrate to an electronic component such as a semiconductor chip by wire bonding is widely used. As shown in FIG. 5, the method of inspecting whether or not the wire bonding property is normally performed is as follows.
The wire 13 to which 2 is bonded is pulled with a predetermined strength, and the presence or absence of peeling is judged. However, in this method, it is necessary to pull a large number of wires, for example, about 500 wires 13 one by one, in order to evaluate the bondability of the wires, and therefore it takes a considerable time for the determination.

【0003】[0003]

【発明が解決しようとする課題】本発明は上述の事実を
鑑みてなされたもので、その目的とするところは、導体
回路のボンディング性を素早く検査できる導体回路のワ
イヤーボンディング性の検査方法を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above facts, and an object of the present invention is to provide a method for inspecting the wire bondability of a conductor circuit that can quickly inspect the bondability of the conductor circuit. To do.

【0004】[0004]

【課題を解決するための手段】本発明の請求項1に係る
導体回路のワイヤーボンディング性の検査方法は、下地
層が銅、中間層がパラジウム、表面層が金からなる三層
の導体回路と電子部品をワイヤーボンディングする前
に、この導体回路の表面を定量元素分析をし、上記表面
の銅成分の原子濃度によって導体回路のボンディング性
の良否を判別することを特徴とする。
According to a first aspect of the present invention, there is provided a method of inspecting a wire bonding property of a conductor circuit, comprising a three-layer conductor circuit including a base layer made of copper, an intermediate layer made of palladium and a surface layer made of gold. Before wire-bonding an electronic component, the surface of the conductor circuit is subjected to quantitative elemental analysis, and the quality of the bondability of the conductor circuit is determined by the atomic concentration of the copper component on the surface.

【0005】本発明の請求項2に係る導体回路のワイヤ
ーボンディング性の検査方法は、請求項1記載の導体回
路のワイヤーボンディング性の検査方法において、上記
導体回路の表面の銅成分の原子濃度が25at.%以上
のものを不良とし、除去することを特徴とする。
According to a second aspect of the present invention, there is provided a method for inspecting the wire bondability of a conductor circuit according to the first aspect, wherein the atomic concentration of the copper component on the surface of the conductor circuit is 25 at. % Or more is regarded as a defect and is removed.

【0006】本発明の請求項3に係る導体回路のワイヤ
ーボンディング性の検査方法は、下地層が銅、中間下層
がニッケル、中間層がパラジウム、表面層が金からなる
四層の導体回路と電子部品をワイヤーボンディングする
前に、この導体回路の表面を定量元素分析し、上記表面
の銅、及び、ニッケル成分の合計の原子濃度によって導
体回路のボンディング性の良否を判別することを特徴と
する。
According to a third aspect of the present invention, there is provided a method for inspecting a wire bondability of a conductor circuit, comprising a four-layer conductor circuit comprising an underlayer of copper, an intermediate lower layer of nickel, an intermediate layer of palladium, and a surface layer of gold, and an electron. Before wire-bonding a component, the surface of the conductor circuit is subjected to quantitative elemental analysis, and the quality of the bondability of the conductor circuit is determined based on the total atomic concentration of copper and nickel components on the surface.

【0007】本発明の請求項4に係る導体回路のワイヤ
ーボンディング性の検査方法は、請求項3記載の導体回
路のワイヤーボンディング性の検査方法において、上記
導体回路の表面の銅、及び、ニッケル成分の合計の原子
濃度が25at.%以上のものを不良とし、除去するこ
とを特徴とする。
According to a fourth aspect of the present invention, there is provided a method for inspecting the wire bondability of a conductor circuit according to the third aspect, which is the method for inspecting wire bondability of the conductor circuit according to the third aspect. Has a total atomic concentration of 25 at. % Or more is regarded as a defect and is removed.

【0008】以下本発明を詳細に説明する。図1は本発
明の請求項1に係る検査方法が使用されるプリント配線
板の断面図の一例を示し、図2は本発明の請求項3に係
る検査方法が使用されるプリント配線板の断面図の一例
を示す。
Hereinafter, the present invention will be described in detail. FIG. 1 shows an example of a sectional view of a printed wiring board in which the inspection method according to claim 1 of the present invention is used, and FIG. 2 is a sectional view of a printed wiring board in which the inspection method according to claim 3 of the present invention is used. An example of the figure is shown.

【0009】本発明の検査の対象となるのは、基板8上
に形成された導体回路1である。上記基板1は、例え
ば、アルミナ等のセラミック基板、エポキシ樹脂等の樹
脂が硬化した基板が用いられる。
The object of the inspection of the present invention is the conductor circuit 1 formed on the substrate 8. As the substrate 1, for example, a ceramic substrate such as alumina or a substrate obtained by curing a resin such as an epoxy resin is used.

【0010】本発明の請求項1に係る検査方法を説明す
る。図1に示す如く、上記導体回路1は、基板8側より
下地層4を銅、中間層6をパラジウム、表面層7を金と
する三層の構成である。本発明は上記導体回路1と半導
体チップ等の電子部品をワイヤーで接続する際の、導体
回路1の良否を素早く判定する、ワイヤーボンディング
性の検査方法である。
An inspection method according to claim 1 of the present invention will be described. As shown in FIG. 1, the conductor circuit 1 has a three-layer structure in which the base layer 4 is copper, the intermediate layer 6 is palladium, and the surface layer 7 is gold from the substrate 8 side. The present invention is a wire bondability inspection method for quickly determining the quality of the conductor circuit 1 when connecting the conductor circuit 1 and an electronic component such as a semiconductor chip with a wire.

【0011】本発明はワイヤーボンディングする前に、
導体回路1の表面を定量元素分析を行い、上記表面の銅
成分の原子濃度によって、導体回路1の良否を判別する
ものである。本発明者等は、上記構成をした導体回路1
は、半導体チップ等を実装する際に高温、例えば400
℃以上で加温されるため、下地層4の銅が表面層7まで
拡散し、銅酸化物を表面に形成する。この銅酸化物が表
面に存在する量が多いと、金からなるワイヤーと導体回
路1のボンディング性が低下し、ワイヤーが付かなかっ
たり、付いても剥がれやすくなることを見い出した。従
って、導体回路1の表面の銅成分の原子濃度を測定する
ことによって、ワイヤーでボンディングすることなく、
導体回路1の良否を判定できる。
According to the present invention, before wire bonding,
The surface of the conductor circuit 1 is subjected to quantitative elemental analysis, and the quality of the conductor circuit 1 is determined by the atomic concentration of the copper component on the surface. The present inventors have found that the conductor circuit 1 having the above-described configuration is used.
Is a high temperature when mounting a semiconductor chip or the like, for example, 400
Since the heating is performed at a temperature of not less than 0 ° C., the copper of the underlayer 4 diffuses to the surface layer 7 and forms copper oxide on the surface. It has been found that when the amount of the copper oxide present on the surface is large, the bondability between the wire made of gold and the conductor circuit 1 is deteriorated, and the wire is not attached or is easily peeled off even if attached. Therefore, by measuring the atomic concentration of the copper component on the surface of the conductor circuit 1, without bonding with a wire,
The quality of the conductor circuit 1 can be determined.

【0012】本発明において用いられる定量元素分析と
しては、オージェ電子分光法が挙げられる。オージェ電
子分光法の測定条件としては、具体的には、約1×10
-9Torrの真空中で、加速電圧10kV、試料電流1
×10-7Aに設定し、得られたスペクトルの銅、パラジ
ウム、及び、金のピークの信号強度から換算して求め
る。定量値は、銅、パラジウム、及び、金の総計を10
0at.%として、これらに対する銅成分の原子濃度を
計算する。この導体回路1の良否判定基準は、銅成分の
原子濃度が25at.%以上のものを不良とすることが
実用上適している。
The quantitative elemental analysis used in the present invention includes Auger electron spectroscopy. Specifically, the measurement conditions for Auger electron spectroscopy are about 1 × 10
-9 Torr vacuum, acceleration voltage 10kV, sample current 1
The value is set to × 10 -7 A and converted from the signal intensities of the peaks of copper, palladium, and gold in the obtained spectrum to obtain the value. The quantitative value is 10 for the total of copper, palladium, and gold.
0 at. Calculate the atomic concentration of the copper component for these as%. The quality criterion for the conductor circuit 1 is that the atomic concentration of the copper component is 25 at. It is practically suitable to make the percentage of% or more defective.

【0013】上記銅成分の原子濃度が25at.%以上
のものを除去し、原子濃度が25at.%未満のものを
用いて、図3に示す如く、上記導体回路1と半導体チッ
プ等の電子部品2をワイヤー3でボンディングすると、
ワイヤーボンディング性の良好な電子部品を搭載したプ
リント配線板が得られる。
The atomic concentration of the copper component is 25 at. % Or more, and the atomic concentration is 25 at. If the conductor circuit 1 and the electronic component 2 such as a semiconductor chip are bonded with a wire 3 as shown in FIG.
It is possible to obtain a printed wiring board on which an electronic component having a good wire bonding property is mounted.

【0014】次に、本発明の請求項3に係る検査方法を
説明する。図2に示す如く、上記導体回路1は、基板8
側より下地層4を銅、中間下層5をニッケル、中間層6
をパラジウム、表面層7を金とする四層の構成である。
Next, an inspection method according to claim 3 of the present invention will be described. As shown in FIG. 2, the conductor circuit 1 includes a substrate 8
From the side, the underlying layer 4 is copper, the intermediate lower layer 5 is nickel, and the intermediate layer 6
Is a four-layer structure in which Pd is palladium and the surface layer 7 is gold.

【0015】本発明はワイヤーボンディングする前に、
導体回路1の表面を定量元素分析し、上記表面の銅、及
び、ニッケル成分の原子濃度によって判別するものであ
る。これは上述と同様に、半導体チップ等を実装する際
の高温により、銅、及び、ニッケルが表面層7まで拡散
し、銅酸化物、及び、ニッケル酸化物を表面に形成す
る。この銅酸化物、及び、ニッケル酸化物が表面に存在
する量が多いと、金からなるワイヤーと導体回路1のボ
ンディング性が低下し、ワイヤーが付かなかったり、付
いても剥がれやすくなることを見い出した。従って、導
体回路1が上記構成の場合は、表面の銅、及び、ニッケ
ル成分の原子濃度を測定することによって、ワイヤーで
ボンディングすることなく、導体回路1の良否を判定で
きるものである。
According to the present invention, before wire bonding,
The surface of the conductor circuit 1 is subjected to a quantitative elemental analysis, and it is determined by the atomic concentrations of copper and nickel components on the surface. In the same manner as described above, copper and nickel diffuse to the surface layer 7 due to a high temperature when mounting a semiconductor chip or the like, and copper oxide and nickel oxide are formed on the surface. It has been found that when the amount of the copper oxide and nickel oxide present on the surface is large, the bondability between the wire made of gold and the conductor circuit 1 is lowered, and the wire is not attached or is easily peeled off even if attached. It was Therefore, in the case where the conductor circuit 1 has the above-described configuration, the quality of the conductor circuit 1 can be determined by measuring the atomic concentrations of the copper and nickel components on the surface without bonding with wires.

【0016】オージェ電子分光法による定量元素分析
は、上述の如く行い、得られたスペクトルの銅、ニッケ
ル、パラジウム、及び、金のピークの信号強度から、
銅、ニッケル、パラジウム、及び、金の総計を100a
t.%として、これらに対する銅、及び、ニッケル成分
の合計原子濃度を計算する。この導体回路1の良否判定
基準は、銅、及び、ニッケル成分の合計の原子濃度が2
5at.%以上のものを不良とすることが実用上適して
いる。その後、原子濃度が25at.%未満のものを用
いて、図4に示す如く、上記導体回路1と半導体チップ
等の電子部品2をワイヤー3でボンディングすると、ワ
イヤーボンディング性の良好な電子部品を搭載したプリ
ント配線板が得られる。
The quantitative elemental analysis by Auger electron spectroscopy was performed as described above, and from the signal intensities of the peaks of copper, nickel, palladium and gold of the obtained spectrum,
The total amount of copper, nickel, palladium, and gold is 100a
t. Calculate the total atomic concentration of copper and nickel components for these as%. The quality criterion of this conductor circuit 1 is that the total atomic concentration of copper and nickel components is 2
5 at. It is practically suitable to make the percentage of% or more defective. After that, the atomic concentration was 25 at. If the conductor circuit 1 and the electronic component 2 such as a semiconductor chip are bonded with a wire 3 using less than 100%, as shown in FIG. 4, a printed wiring board on which the electronic component having good wire bonding property is mounted can be obtained. .

【0017】上述の如く、本発明の導体回路のワイヤー
ボンディング性の検査方法は、ワイヤーでボンディング
することなく、導体回路1の良否を判定できるので、導
体回路のワイヤーボンディング性の検査が素早くできる
As described above, according to the method for inspecting the wire bonding property of the conductor circuit of the present invention, the quality of the conductor circuit 1 can be determined without bonding with a wire, so that the wire bonding property of the conductor circuit can be quickly inspected.

【0018】[0018]

【作用】本発明の請求項1に係る導体回路のワイヤーボ
ンディング性の検査方法は、半導体チップ等を実装する
際の加温により、下地層の銅が表面層まで拡散し、銅酸
化物を表面に形成するので、この銅酸化物が表面に存在
する量が多いと、金からなるワイヤーと導体回路のボン
ディング性が低下するため、導体回路の表面の銅成分の
原子濃度を測定する。
In the method for inspecting the wire bondability of the conductor circuit according to the first aspect of the present invention, the copper of the underlayer diffuses to the surface layer by heating when mounting a semiconductor chip or the like, and the copper oxide is surfaced. When the amount of the copper oxide present on the surface is large, the bondability between the wire made of gold and the conductor circuit deteriorates. Therefore, the atomic concentration of the copper component on the surface of the conductor circuit is measured.

【0019】本発明の請求項3に係る導体回路のワイヤ
ーボンディング性の検査方法は、半導体チップ等を実装
する際の加温により、銅、及び、ニッケルが表面層まで
拡散し、銅酸化物、及び、ニッケル酸化物を表面に形成
するので、この銅酸化物、及び、ニッケル酸化物が表面
に存在する量が多いと、金からなるワイヤーと導体回路
のボンディング性が低下するため、導体回路の表面の
銅、及び、ニッケル成分の原子濃度を測定する。
According to a third aspect of the present invention, there is provided a method for inspecting a wire bonding property of a conductor circuit, wherein copper and nickel diffuse to a surface layer by heating when mounting a semiconductor chip or the like, copper oxide, And, since the nickel oxide is formed on the surface, if the copper oxide and the nickel oxide are present on the surface in a large amount, the bondability between the wire made of gold and the conductor circuit deteriorates. Measure the atomic concentration of copper and nickel components on the surface.

【0020】[0020]

【実施例】【Example】

実施例1 基板にアルミナ基板を用い、メッキ法により下地層が
銅、中間層がパラジウム、表面層が金からなる三層の導
体回路を形成した。下地層、及び、表面層の厚みは一定
とし、中間層の厚みを様々に変え、430℃で6分間加
熱した後に、オージェ電子分光法により表面層の定量元
素分析を行った。結果は表1に示すとおり、銅成分の濃
度が2.8at.%、19.5at.%、23.7a
t.%、46.2at.%のものを得た。確認のため、
実際に450ヵ所ワイヤーボンディングを行った後に、
これらワイヤーを引っ張り、剥がれ試験を行ったとこ
ろ、銅成分の濃度が46.2at.%のものだけ10カ
所剥がれた。
Example 1 An alumina substrate was used as a substrate, and a three-layer conductor circuit including a base layer of copper, an intermediate layer of palladium, and a surface layer of gold was formed by a plating method. The thicknesses of the underlayer and the surface layer were kept constant, the thickness of the intermediate layer was variously changed, and after heating at 430 ° C. for 6 minutes, the surface layer was subjected to quantitative elemental analysis by Auger electron spectroscopy. As shown in Table 1, the result shows that the concentration of the copper component is 2.8 at. %, 19.5 at. %, 23.7a
t. %, 46.2 at. I got a percentage. For confirmation,
After actually performing wire bonding at 450 points,
When these wires were pulled and tested for peeling, the copper component concentration was 46.2 at. Only 10% peeled off in 10 places.

【0021】[0021]

【表1】 [Table 1]

【0022】実施例2 基板にアルミナ基板を用い、メッキ法により下地層が
銅、中間下層がニッケル、中間層がパラジウム、表面層
が金からなる四層の導体回路を形成した。下地層、及
び、表面層の厚みは一定とし、中間下層のニッケル、及
び、中間層のパラジウムの厚みを様々に変え、430℃
で6分間加熱した後に、オージェ電子分光法により表面
層の定量元素分析を行った。結果は表2に示すとおり、
銅、及び、ニッケル成分の合計の濃度が7.5at.
%、24.3at.%、29.3at.%のものを得
た。確認のため、実際に450ヵ所ワイヤーボンディン
グを行った後に、これらワイヤーを引っ張り、剥がれ試
験を行ったところ、銅、及び、ニッケル成分の合計の濃
度が29.3at.%のものだけ4カ所剥がれた。
Example 2 An alumina substrate was used as a substrate, and a four-layer conductor circuit was formed by a plating method in which the underlayer was copper, the intermediate lower layer was nickel, the intermediate layer was palladium, and the surface layer was gold. The thickness of the base layer and the surface layer is constant, and the thicknesses of nickel in the intermediate lower layer and palladium in the intermediate layer are variously changed to 430 ° C.
After heating for 6 minutes, the surface layer was subjected to quantitative elemental analysis by Auger electron spectroscopy. The results are shown in Table 2.
The total concentration of copper and nickel components is 7.5 at.
%, 24.3 at. %, 29.3 at. I got a percentage. For confirmation, after wire bonding was actually carried out at 450 points, the wires were pulled and a peeling test was carried out. As a result, the total concentration of copper and nickel components was 29.3 at. Only 4% peeled off in 4 places.

【0023】[0023]

【表2】 [Table 2]

【0024】[0024]

【発明の効果】本発明の請求項1乃至請求項4いずれか
に係る導体回路のワイヤーボンディング性の検査方法を
用いると、ワイヤーでボンディングすることなく、導体
回路の良否を判定できるので、導体回路のワイヤーボン
ディング性の検査が素早くできる
When the method for inspecting the wire bonding property of a conductor circuit according to any one of claims 1 to 4 of the present invention is used, the quality of the conductor circuit can be determined without bonding with a wire. Quick inspection of wire bondability

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の請求項1に係る検査方法が使用される
プリント配線板の断面図を示す。
FIG. 1 shows a cross-sectional view of a printed wiring board in which an inspection method according to claim 1 of the present invention is used.

【図2】本発明の請求項3に係る検査方法が使用される
プリント配線板の断面図を示す。
FIG. 2 is a sectional view of a printed wiring board in which the inspection method according to claim 3 of the present invention is used.

【図3】ワイヤーボンディングしたプリント配線板の断
面図の一例を示す。
FIG. 3 shows an example of a sectional view of a wire-bonded printed wiring board.

【図4】ワイヤーボンディングしたプリント配線板の断
面図の一例を示す。
FIG. 4 shows an example of a sectional view of a wire-bonded printed wiring board.

【図5】従来のワイヤーボンディング性の検査方法を示
した略図である。
FIG. 5 is a schematic view showing a conventional wire bondability inspection method.

【符号の説明】[Explanation of symbols]

1 導体回路 4 下地層 5 中間下層 6 中間層 7 表面層 8 基板 1 Conductor Circuit 4 Underlayer 5 Intermediate Lower Layer 6 Intermediate Layer 7 Surface Layer 8 Substrate

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 下地層が銅、中間層がパラジウム、表面
層が金からなる三層の導体回路と電子部品をワイヤーボ
ンディングする前に、この導体回路の表面を定量元素分
析し、上記表面の銅成分の原子濃度によって導体回路の
ボンディング性の良否を判別することを特徴とする導体
回路のワイヤーボンディング性の検査方法。
1. A surface of a conductor circuit is quantitatively analyzed by a quantitative elemental analysis before wire-bonding a three-layer conductor circuit including an underlayer of copper, an intermediate layer of palladium and a surface layer of gold to an electronic component by wire bonding. A method for inspecting the wire bondability of a conductor circuit, which comprises determining whether the bondability of the conductor circuit is good or bad by the atomic concentration of a copper component.
【請求項2】 上記導体回路の表面の銅成分の原子濃度
が25at.%以上のものを不良とし、除去することを
特徴とする請求項1記載の導体回路のワイヤーボンディ
ング性の検査方法。
2. The atomic concentration of the copper component on the surface of the conductor circuit is 25 at. 2. The method for inspecting the wire bonding property of a conductor circuit according to claim 1, wherein the one having a percentage of not less than 100% is regarded as defective and removed.
【請求項3】 下地層が銅、中間下層がニッケル、中間
層がパラジウム、表面層が金からなる四層の導体回路と
電子部品をワイヤーボンディングする前に、この導体回
路の表面を定量元素分析し、上記表面の銅、及び、ニッ
ケル成分の合計の原子濃度によって導体回路のボンディ
ング性の良否を判別することを特徴とする導体回路のワ
イヤーボンディング性の検査方法。
3. A quantitative elemental analysis of the surface of the conductor circuit before wire-bonding a four-layer conductor circuit comprising an underlayer of copper, an intermediate lower layer of nickel, an intermediate layer of palladium, and a surface layer of gold Then, the method for inspecting the wire bondability of a conductor circuit is characterized by determining whether the bondability of the conductor circuit is good or bad based on the total atomic concentration of copper and nickel components on the surface.
【請求項4】 上記導体回路の表面の銅、及び、ニッケ
ル成分の合計の原子濃度が25at.%以上のものを不
良とし、除去することを特徴とする請求項3記載の導体
回路のワイヤーボンディング性の検査方法。
4. The total atomic concentration of copper and nickel components on the surface of the conductor circuit is 25 at. 4. The method for inspecting the wire bondability of a conductor circuit according to claim 3, wherein the one having a percentage of not less than 100% is regarded as defective and is removed.
JP6276860A 1994-11-10 1994-11-10 Inspection method of wire bondability of conductor circuit Withdrawn JPH08139148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6276860A JPH08139148A (en) 1994-11-10 1994-11-10 Inspection method of wire bondability of conductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6276860A JPH08139148A (en) 1994-11-10 1994-11-10 Inspection method of wire bondability of conductor circuit

Publications (1)

Publication Number Publication Date
JPH08139148A true JPH08139148A (en) 1996-05-31

Family

ID=17575425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6276860A Withdrawn JPH08139148A (en) 1994-11-10 1994-11-10 Inspection method of wire bondability of conductor circuit

Country Status (1)

Country Link
JP (1) JPH08139148A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100352661B1 (en) * 2000-02-10 2002-09-12 퀄리플로나라테크 주식회사 A precleaning method for the enhancement of the deposition rate of the copper film for wiring of elemental semiconductor devices
US6759597B1 (en) * 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces
JP2017022314A (en) * 2015-07-14 2017-01-26 Jx金属株式会社 Process liquid of semiconductor wafer, processed semiconductor wafer, and processing method of semiconductor wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759597B1 (en) * 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces
KR100352661B1 (en) * 2000-02-10 2002-09-12 퀄리플로나라테크 주식회사 A precleaning method for the enhancement of the deposition rate of the copper film for wiring of elemental semiconductor devices
JP2017022314A (en) * 2015-07-14 2017-01-26 Jx金属株式会社 Process liquid of semiconductor wafer, processed semiconductor wafer, and processing method of semiconductor wafer

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