JPH08138385A - Operation method for nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE: To obtain a control system for nonvolatile semiconductor memory device in which electric rewriting can be carried out reliably at high rate. CONSTITUTION: When information is written in a floating gate type nonvolatile memory cell or the information is erased therefrom, a writing or erasing voltage is split into a plurality of voltage pulses including at least one voltage pulse having a rising time different from those of other voltage pulses. Rising of voltage pulse is made gentle immediately after starting the writing operation and a switching is made to a steep voltage pulse in the way thus preventing excess rewriting of high rate bit while allowing high rate writing of low rate bit. Furthermore, a voltage pulse rising slowly is applied immediately after starting the rewriting operation in order to relax stress being applied to a gate insulation film thus prolonging the lifetime of a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device operating method, and more particularly to a rewritable nonvolatile semiconductor memory device operating method at high speed and with high controllability.

[0002]

2. Description of the Related Art In a floating gate type non-volatile semiconductor memory device, the threshold voltage of a MOS transistor is changed by writing / erasing information by injecting electrons into the floating gate or emitting electrons from the floating gate. It is realized in. The above-mentioned electron injection / emission operation to the floating gate is caused by the channel hot electron phenomenon or Fowler-Nordh
It is realized by eim (FN) tunnel phenomenon etc., but at this time, stress due to injected charges is applied to the gate insulating film,
There is a problem that the gate insulating film deteriorates. The stress applied to the gate insulating film at the time of rewriting is determined by the electric field strength applied to the insulating film, and in the case of a NOR type memory cell, a large electric field is applied at the time of emission of electrons that pull out the electrons accumulated in the floating gate. In particular, when a high electric field is suddenly applied to the gate insulating film in a state where the amount of charges accumulated in the floating gate is excessive, the stress increases.

As a conventional method of operating a non-volatile semiconductor memory device for reducing the stress, for example, Japanese Patent Laid-Open No. 61-61160 is available.
-239497, Japanese Patent Laid-Open No. 61-239498, Japanese Patent Laid-Open No. 2-193398 and the like, there is a method of operating a nonvolatile semiconductor memory device.

In the method of operating a nonvolatile semiconductor memory device disclosed in Japanese Patent Laid-Open No. 61-239497, a voltage for writing is set to a first voltage pulse Vd2 and a second voltage higher in voltage level than the first voltage pulse. It is given by a series of voltage pulses consisting of the voltage pulse Vd1. This voltage application flow is shown in Fig. 4 (a).
Shown in After the charges are lightly injected into the floating gate by the first voltage pulse due to the channel hot electron phenomenon, the second voltage having a higher voltage level than the first voltage pulse is injected.
Then, the electric charge was further injected by the voltage pulse of (1) to write. As a result, compared with the case where the second voltage pulse of a high voltage is applied suddenly from the beginning, the fluctuation of the floating gate potential before and after the rewriting can be suppressed, so that the charge injection region in the gate insulating film becomes wider, Rewriting characteristics are improved by suppressing the amount of channel hot electrons trapped in the gate insulating film.

Similarly, as a method for suppressing the fluctuation of the floating gate potential before and after rewriting, there is a method of operating a nonvolatile semiconductor memory device disclosed in Japanese Patent Laid-Open No. 61-239498. In this method, the drive voltage for writing is given by a voltage pulse having a rise time tr (the time required for the voltage pulse to rise from 10% to 90% of the target voltage level) to be 300 μsec or more. When writing is performed with a voltage pulse having a gradual rise in this way, a transient voltage until the voltage pulse reaches a predetermined drive potential causes light charge injection into the floating gate due to the channel hot electron phenomenon. The same effect as the method of applying the pulse in two steps can be obtained.

Further, in Japanese Patent Laid-Open No. 2-193398, a rewriting voltage pulse is divided into a plurality of voltage pulses having a sharp rise / fall time and a short pulse width to be applied. This voltage application flow is shown in FIG. Here, the pulse width is defined as the time from when the voltage pulse starts to rise to when it completely falls (see FIG. 4). Each of the plurality of voltage pulses is
Only a part of the charge amount to be injected or discharged in one rewriting shall be injected or discharged. This makes F-
A nonvolatile semiconductor memory device having a long life is provided by suppressing generation of holes due to N current and reducing holes trapped in a gate insulating film.

[0007]

In the above-described method of operating a nonvolatile semiconductor memory device according to the prior art, a voltage pulse applied to a memory cell in rewriting information is given by a plurality of voltage pulses having a constant rise time. . Therefore, when realizing a large-capacity non-volatile semiconductor memory device capable of low-voltage operation, how to realize high-speed rewriting with high controllability becomes an issue.

FIG. 4 is a diagram showing a voltage applying method in the conventional writing / erasing method. In the voltage application method of FIG. 4A, the voltage for rewriting is set to the first voltage pulse Vd.
2 and a second voltage level higher than the first voltage pulse
And a series of voltage pulses Vd1 and Vd1. At this time, due to variations in the characteristics of the memory cells, for example, if there is a bit in which electrons are extracted faster than a standard bit, the extraction will proceed even at the first voltage,
When a second voltage pulse having a higher voltage level is applied, there is a problem that the bit is overdrawn.

In the voltage application method of FIG. 4 (b), the voltage for rewriting is given by a voltage pulse having a rise time tr of 300 μsec or more. Due to variations in the characteristics of the memory cells and the like, if the memory cell to be rewritten is in a higher threshold state than, for example, a standard bit, there is a problem that it takes a long time to rewrite.

In the voltage application method of FIG. 4 (c), the drive voltage is divided into a plurality of voltage pulses to enhance the controllability of the threshold voltage, and the write time is increased for a predetermined time as compared with the conventional example. This is a method of applying a drive voltage pulse for realizing the writing of data inside. In order to realize high-speed writing / erasing, the rise time of the voltage pulse is approximately 1 μsec. FIG. 5 is a diagram showing the rising tendency of voltage pulses having various rising times, and FIG. 6 shows the electric field fluctuation in the gate insulating film when the voltage pulse is used as a predetermined drive voltage for rewriting. FIG. In this way, the voltage application method in which the rise time of the pulse is as steep as 1 μsec, for example, causes a higher electric field to be applied to the gate insulation film than the voltage application method in which the rise voltage is as gentle as 100 μsec. Connect

In the voltage application method of FIG. 4 (d), a plurality of voltage pulses for rewriting are applied while gradually increasing the peak level from the first voltage pulse. This method enables fine control of the threshold voltage while preventing a high electric field from being suddenly applied to the gate insulating film, but it requires a limiter circuit to control the peak value of the voltage pulse. Therefore, when realizing a large-capacity nonvolatile semiconductor memory device, there is a problem in terms of high integration.

Further, in a general non-volatile semiconductor memory device, the characteristics of the memory cell are deteriorated as the rewriting is repeated. Therefore, in the voltage applying method using a voltage pulse of a constant width, the rewriting time increases as the number of rewriting increases. There is also. As described above, in order to realize a highly reliable nonvolatile semiconductor memory device capable of high-speed rewriting, the threshold voltage of the fastest rewriting memory cell caused by the characteristic variation of the memory cell is set to be It is necessary to control well and prevent deterioration due to rewriting, and to control the threshold voltage of the latest rewriting memory cell within a predetermined time. Further, it is necessary to realize these rewriting operation means with a small circuit configuration.

An object of the present invention is to provide a method of controlling a non-volatile semiconductor memory device capable of electrically rewriting at high speed and with high reliability.

[0014]

The above-mentioned conventional problems are as follows.
This can be solved by a threshold voltage control method for a memory cell, which includes at least the voltage application operation described below.

At least a gate insulating film, a floating gate, an interlayer insulating film, and a control gate are laminated on the semiconductor substrate or the well diffusion layer shown in FIG. 2, and the conductivity is opposite to the conductivity type of the substrate or the well diffusion layer. In writing or erasing information in or from a memory cell having a source and drain regions of a positive type, as shown in FIG. 1, first, the control gate is raised to a predetermined drive voltage Vcgw, and then a predetermined drive voltage Vdw is applied to the drain. Is given at a voltage approximately equal to half the pulse width rise time of the voltage pulse. After a small amount of electrons are injected into or extracted from the floating gate by the applied voltage, the potential of the drain and control gate is lowered, and then a read operation for confirming whether the data rewriting operation is properly performed. Do. This is called a verify operation. After confirming that the rewriting is not completed, a voltage pulse is applied again to rewrite, and a verify operation is performed to inject or withdraw electrons into the floating gate. The above operation is repeated several times, and when the rewriting is not completed yet, the voltage pulse applied to the drain is further switched to the voltage pulse having a steep rising edge. In this way, the predetermined driving voltage applied to the memory cell is divided into a plurality of voltage pulses, and at least one of the plurality of voltage pulses is a series of voltage pulses having a different rise time from other voltage pulses. Then, the memory cell is set to a predetermined threshold value and the rewriting is completed.

[0016]

In the following, the electron emission operation for extracting the electrons accumulated in the floating gate is defined as data writing. However,
The present invention is not limited to this, and can be applied to the electron injection operation. FIG. 2 is a diagram showing a voltage application state of the memory cell at the time of writing data. During data writing, the floating gate voltage Vf is controlled by the control gate voltage Vcgw, the drain voltage Vdw, the memory cell coupling ratio (ratio of the capacitance between the floating gate and the control gate to the total capacitance viewed from the floating gate) Cr, and Amount of accumulated charge in the floating gate
Using Q, control gate-floating gate capacitance C2, and floating gate-drain capacitance Cd, Vf = Cr × (Vcgw + Cd
× Vdw / C2 + Q / C2) A high electric field of | Vf-Vdw | / Tox is applied to the gate insulating film having a thickness Tox between the floating gate and the drain. However, the potential of the substrate or well is set to approximately the ground potential, and the potential of the source is set to floating. As a result, the F
The -N tunnel emission phenomenon occurs, electrons are emitted from the floating gate to the drain diffusion layer region, and the memory cell can be set to the low threshold state.

FIG. 1 is a diagram showing a first embodiment of a write voltage application flow according to the present invention. In data writing, the write voltage Vdw of the drain is first applied with a gentle rise voltage, for example, a ramp voltage. By repeating writing with the ramp voltage several times, the accumulated electrons in the floating gate are gradually extracted. The verify operation performed between application of the write voltage pulse is performed by writing / erasing time of information (after a predetermined drive voltage for writing / erasing starts rising due to variations in characteristics of memory cells, etc.).
Even if there is a faster write / erase completion time until the drive voltage falls to a lower level than a standard memory cell, the write / erase operation is performed in order to end normally. By repeating the writing with the ramp voltage, it is possible to control the threshold voltage with high accuracy in the initial stage of the writing operation. When the writing is not completed with the above ramp voltage, the voltage pulse applied to the drain is further switched to the rectangular voltage pulse having a steep rising edge.
By switching the write voltage to the rectangular pulse, the extraction of electrons is promoted, and the memory cell can be set to a predetermined threshold value within a target time. Further, since the stored electrons are lightly extracted in advance by the lamp voltage, an excessively high electric field is not applied to the gate insulating film even if a voltage pulse having a steep rising rectangle is applied thereafter.

In the method for operating the nonvolatile semiconductor memory device of the present invention, after the write operation is started, first, the electrons are gently extracted from the floating gate several times by the first voltage pulse having a long rise time. Therefore, even if the writing of the bit in which electrons are extracted faster than the standard bit is completed during this period, the verify operation can be performed before the excessive extraction and the writing can be normally completed. In this way, the write voltage pulse corresponding to the bit with a fast write is applied immediately after the start of write, and then the applied voltage pulse is switched to a pulse with a steep rising edge, and a memory cell with standard characteristics is obtained. To improve the efficiency of writing. Figure 7
FIG. 4 is a diagram showing how the threshold voltage changes during data writing. As shown in FIG. 7, the threshold voltage of the memory cell varies logarithmically with the drive voltage application time.
In the voltage application method of the present invention, the write time is increased as compared with the conventional example by using a voltage pulse having a gentle rising edge several times immediately after the start of the write operation, and then applying a voltage pulse having a sharp rising edge to increase the write efficiency. It is possible to realize the writing of data within a predetermined time without doing so.
Immediately after the start of the write operation, by applying a voltage pulse with a gentle rise, the electrons in the floating gate can be pulled out lightly by the electric field created by the transient potential during the rise of the voltage pulse. The maximum electric field applied to the gate insulating film when the pulse reaches the write voltage value Vdw can be suppressed as compared with the case where the rising edge of the voltage pulse is steep. Therefore, the stress applied to the gate insulating film can be reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 to 3 and 6 to 9. FIG. 3 is a diagram showing voltage conditions at the time of writing information (emitting electrons from the floating gate) when the memory cell is an n-channel MOS transistor.

In the first embodiment, as shown in FIG. 3, the control gates of the memory cells M1-1 and M1-2 are connected to the word line W1 and the control gates of the memory cells M2-1 and M2-2 are connected to the word line W1. Connected by word line W2, the drains of M1-1 and M2-1 are connected to data line D1 and M1-2
And the drains of M2-2 are connected to the data line D2, and M1-1 and M2-1
Is connected to the source line S1, and the sources of M1-2 and M2-2 are connected to the source line S2. In this embodiment, a plurality of memory cells are connected in parallel as shown in FIG. 3 and arranged in a matrix, but the method of arranging the memory cells is not limited to this. The number of word lines and data lines, and the number of memory cells are not limited to this. Further, although these memory cells are connected by a common well wiring WEL, the wells may be separately driven at a scale of 1 megabit or 4 megabit when the scale of the array configuration becomes large.

FIG. 1 is a diagram showing a write voltage flow in the first embodiment of the present invention. FIG. 2 is a diagram showing a voltage application state of the memory cell at the time of writing data. When writing data, first raise the control gate voltage Vcg to the specified drive potential Vcgw = -10V, and then drain voltage Vcg
d is given with a ramp voltage where the rise time of the voltage pulse is approximately equal to half the pulse width. The rise time of the pulse is
10 μsec. By the method of applying the voltage pulse having the gradual rise in this way, the electrons in the floating gate are slightly extracted by the weak electric field created by the transient potential during the rise of the pulse.

FIG. 7 is a diagram showing how the threshold voltage fluctuates when writing is performed by the drive voltage having various rising times shown in FIG. The amount of electrons that can be extracted by one voltage pulse with a constant pulse width (defined as the time from when the voltage pulse starts to rise to when it completely falls) has a steeper rise for a slower rise, such as a lamp voltage. Since it is smaller than in some cases, the fluctuation of the threshold value is small. Therefore, it is possible to control the threshold voltage with high accuracy. The same ramp voltage is repeatedly applied to the drain 10 times, and if there is a bit with a high write speed during this time, this is detected by the verify operation and the write operation is ended. However, the number of times the lamp voltage is applied is not limited to this. As described above, in the first embodiment of the present invention, even if there is a bit in which writing is fast due to characteristic variations, writing can be performed without causing excessive writing. Further, as shown in FIG. 6, the electric field applied to the gate insulating film is reduced as compared with the pulse having a steep rise, so that the stress applied to the gate insulating film can be suppressed. It is understood from FIG. 6 that the longer the rise time is, the more the maximum electric field applied to the gate insulating film can be suppressed. However, it is important to set the rise time to an appropriate value because if the rise time becomes too long to be ignored compared to the write time, the write time will increase.

After the lamp voltage is applied to the drain 10 times in succession, the voltage pulse applied to the drain is switched to a rectangular pulse having a rise time of 0.1 μsec.

FIG. 8 shows an example of a voltage supply circuit that applies two types of voltage pulses having different rise times to the drain during data writing. Initially, a voltage pulse with a long rise time is output through the source / drain path of a p-channel transistor with a small gm, and then a p-channel transistor with a large gm is switched to output a voltage pulse with a short rise time. Thus, two types of transistors having different gm can easily output voltage pulses having different rise times. Of course, in order to output three or more types of voltage pulses having different rise times, three or more types of transistors having different gm's should be prepared.

FIG. 9 is a diagram showing how the threshold voltage of a standard memory cell fluctuates when programming is performed according to the programming voltage flow of FIG. In this embodiment, since a plurality of voltage pulses having a gentle rise and a short pulse width are applied immediately after the start of the write operation, the threshold value starts to change as compared with the case where a predetermined drive voltage is applied by a single pulse. Although the time becomes late, by switching the applied voltage pulse to a voltage pulse having a steep rise time in the middle of writing, it is possible to write to a memory cell having standard characteristics in the same writing time as before.

In the nonvolatile semiconductor memory device of this embodiment,
Since the memory cells are connected in parallel, high speed read operation during data read is maintained. Since electrons are injected / released by the FN tunnel phenomenon for writing / erasing data in the memory cell, an excessive current component other than the tunnel current is not required, and low power consumption can be achieved with a single power supply. The operation of the memory chip becomes possible.

Further, since the operation method of this embodiment requires only two types of voltage pulses having different rise times,
High integration can be achieved without requiring a complicated limiter circuit or the like for controlling the applied voltage peak level.

In the first embodiment of the present invention, the writing of data has been described above, but the present invention is not limited to this and is effective in erasing data. It is also effective when the electrons in the floating gate are extracted to the source instead of the drain. Further, it is also effective to control the above voltage pulse with respect to the gate voltage.

The second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the potential of the data line at the time of writing, which is applied as shown in FIG. 1 in the first embodiment, is applied as shown in the flow of FIG.

FIG. 11 shows an example of the circuit configuration of the second embodiment. In the second embodiment, a write voltage control circuit is inserted between the drain write voltage generation circuit and the data line, and a timer is connected to the write voltage control circuit. During data write operation, after raising the potential of word line W1 to Vcgw = -10V, which is the predetermined write potential, the write voltage generator generates the predetermined drive voltage with rise time tr = 10μsec.
A voltage pulse that rises to Vdw = 4.5v is generated. This voltage pulse input to the write voltage control circuit is cut by a timer in a time shorter than the rising time tr of the voltage pulse. For example, the cutting is performed at the first time of 5 μsec which is ½ of the rise time of the voltage pulse. However, the rising time and the cutting time are not limited to this. Therefore, the potential of the data line D1 is the predetermined drive voltage Vdw =
It only rises to a potential lower than 4.5v (about 2.2V). Also, the write voltage pulse width becomes shorter. In this way, the applied voltage pulse in the initial stage of the write operation is a voltage pulse having a lower voltage level and a shorter pulse width than the voltage pulse in the first embodiment, whereby the electric field strength applied to the gate insulating film can be relaxed. The stored electrons in the gate can be pulled out more slowly. Therefore, the threshold voltage can be controlled with higher accuracy, and even if there is a bit for which writing is fast, this can be detected by the verify operation before overwriting and the writing operation can be completed. After the predetermined verify operation, the voltage pulse whose pulse width is controlled by the write voltage control circuit is applied to the drain again. However,
The cutting time is longer than the first time, for example, 6 μsec. Below, the time to cut is 7,8 μse
c. ． ． And the same operation is repeated 10 times. Here, when the cutting time is 10 μsec, the potential of the data line rises up to approximately the predetermined write voltage Vdw = 4.5v. Then, in the subsequent voltage pulse, the write voltage level becomes constant, and only the pulse width increases. By increasing the width of the voltage pulse at a predetermined operating voltage in this manner, standard bit writing is promoted.

If the writing is not completed by the above operation, then the write voltage pulse is switched to a voltage pulse having a steep rise time by the control circuit shown in FIG.
For example, tr = 0.1 μsec. As a result, the write efficiency can be further increased, and thus even if there is a bit that is slow to write, the write can be completed within a predetermined time.

The operating method of the present embodiment can more accurately cope with variations in threshold voltage by controlling the pulse width in addition to controlling the rise time of the applied voltage. In addition, the maximum electric field applied to the gate insulating film can be further suppressed, and the stress on the insulating film can be reduced.
A nonvolatile semiconductor memory device having a long life can be provided. In addition, by increasing the pulse width of the voltage pulse during the write operation, the write efficiency is increased, and the write time is the same as before, even for bits with slow write characteristics, for example 1 m.
It can be within sec. FIG. 12 shows how the threshold voltage of the memory cell varies during data writing in the operation system of the nonvolatile semiconductor memory device of the second embodiment.

Also in this embodiment, since the memory cells are connected in parallel, the high speed at the time of reading data is maintained. Further, since the data of the memory cell is written / erased by the FN tunnel phenomenon, an excessive current component other than the tunnel current is not required, so that the power consumption can be reduced and the external single power supply of the chip can be operated. It goes without saying that it will be. Further, since the voltage level of the applied voltage pulse is low at the initial stage of the write operation, stress on the gate insulating film can be reduced and the life of the memory cell can be extended.

[0034]

As described above, in the floating gate type non-volatile semiconductor memory device of the present invention, a predetermined writing or erasing voltage is divided into a plurality of voltage pulses at the time of writing or erasing data, and the plurality of voltage pulses are divided. It is possible to control the threshold voltage with high accuracy by appropriately changing the rise time of the memory cell, and it is possible to provide a rewrite operation with high controllability that responds to variations in the characteristics of the memory cells. Especially, by making the rise of the voltage pulse immediately after the start of the write operation gentle and switching it to a voltage pulse with a sharp rise in the middle, it is possible to prevent excessive writing for fast rewriting bits and fast writing for slow bits. This can be realized and the stress applied to the gate insulating film can be reduced, and the life of the memory cell can be extended.

[Brief description of drawings]

FIG. 1 is a diagram showing a voltage application flow at the time of writing in a first embodiment of an operation system of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a write operation to a memory cell of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a nonvolatile semiconductor memory device of the present invention and a voltage condition during writing.

FIG. 4 is a diagram showing a voltage application flow at the time of writing in the operation system of the conventional nonvolatile semiconductor memory device.

FIG. 5 is a diagram showing a rising tendency of a drain voltage pulse having a rising time of 0.1 μsec to 100 μsec.

FIG. 6 is a diagram showing electric field fluctuations in a gate insulating film of a memory cell when data is written with drain voltage pulses of various rise times shown in FIG. 5 in the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a diagram showing variations in the threshold voltage of a memory cell when data is written with drain voltage pulses of various rise times shown in FIG. 5 in the nonvolatile semiconductor memory device of the present invention.

FIG. 8 is a diagram showing a circuit for supplying write voltages having different rise times to data lines during data writing in the operation system of the nonvolatile semiconductor memory device of the present invention.

FIG. 9 is a diagram showing variations in the threshold voltage of the memory cell at the time of data writing in the first embodiment of the operation system of the nonvolatile semiconductor memory device of the present invention.

FIG. 10 is a diagram showing a voltage application flow at the time of writing in the second embodiment of the operation system of the nonvolatile semiconductor memory device of the present invention.

FIG. 11 is a diagram showing a circuit for supplying write voltages having different pulse widths to the data lines during data writing in the second embodiment of the operation system of the nonvolatile semiconductor memory device of the present invention.

FIG. 12 is a diagram showing variations in the threshold voltage of the memory cell at the time of data writing in the second embodiment of the operation system of the nonvolatile semiconductor memory device of the present invention.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoki Miyamoto 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (8)

[Claims] 1. A gate insulating film, a floating gate, an interlayer insulating film, at least on a semiconductor substrate or a well diffusion layer,
In a memory cell array formed by stacking control gates and arranging a plurality of memory cells having a source region and a drain region of a conductivity type opposite to the conductivity type of the substrate or the well diffusion layer, arranged in a matrix, At the time of writing or erasing information in the memory cell, when a predetermined driving voltage applied to achieve one writing or erasing is divided into a plurality of voltage pulses and applied, at least one of the plurality of voltage pulses is applied. One is a method for operating a nonvolatile semiconductor memory device, which has a rise time different from that of other voltage pulses. 2. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the rise time of a plurality of voltage pulses is the rise time of a certain voltage pulse. The rising time is at least not longer than the rising time of the non-volatile semiconductor memory device. 3. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the plurality of voltage pulses have rise times substantially equal to half the pulse width. A method for operating a nonvolatile semiconductor memory device, comprising one voltage pulse and a second voltage pulse having a rise time shorter than half the pulse width. 4. A method for operating a nonvolatile semiconductor memory device according to claim 1, wherein the pulse widths of the plurality of voltage pulses are gradually increased. Method of operating non-volatile semiconductor memory device. 5. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the plurality of voltage pulses have a constant pulse width. Method of operating a non-volatile semiconductor memory device. 6. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein at least one voltage pulse of the plurality of voltage pulses has a voltage level of A method for operating a non-volatile semiconductor memory device, characterized in that the voltage level is smaller than a predetermined drive voltage value applied to achieve writing or erasing, and the voltage levels of the plurality of voltage pulses gradually increase. 7. A method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the data line connected to a drain region of a memory cell or a source region is connected. A method of operating a non-volatile semiconductor memory device, wherein the plurality of voltage pulses are applied to a source line. 8. A method for operating a nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cells are provided for a word line connected to a control gate of a memory cell. A method of operating a non-volatile semiconductor memory device, wherein a voltage pulse is applied.