JPH08137830A - Signal processor - Google Patents

Abstract

PURPOSE: To provide a signal processor which is decreased in circuit scale and reduced in the number of constituent components without sacrificing characteristics of convolution processing. CONSTITUTION: This signal processor consists of a scanning converting circuit 1 which divides a two-dimensional digital data array into plural blocks and converts input data obtained by scanning the blocks, one by one, into the scanning order of an array format, data buffers 3-1 and 3-2 which delay the output data from the scanning converting circuit 1, S/P converting circuits 2-1, 2-2, and 2-3 which output output data from the scanning converting circuit 1 or data buffers 3-1 and 3-2 in parallel, a shift register array 4 which stores the data from the S/P converting circuits, a data selector 7 which takes data out of the shift register array 4, and a convolution processing circuit 8 which performs the convolution processing by using the taken-out data and a two-dimensional coefficient array.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a two-dimensional digital data array into a plurality of blocks and scans each block to obtain time-series input data and a predetermined two-dimensional coefficient array. The present invention relates to a signal processing device that performs the convolution processing of.

[0002]

2. Description of the Related Art For example, a two-dimensional convolution processing device using a two-dimensional coefficient array of 9 rows and 9 columns generally has a configuration as shown in FIG. That is, when the time-series input data obtained by scanning the two-dimensional digital data array is not in the raster scan order as shown in FIG. 5, the scan conversion circuit 101 first converts it into the raster scan order. Then, the scan conversion circuit 101
The raster scan order time series data obtained by
A delay means having a delay amount corresponding to the number of pieces of data forming one row (defined as a line) of the original two-dimensional digital data array, that is, the line buffer 102-1 is used to delay the shift register It is supplied to the array 103. The output from the line buffer 102-1 is output together with the line buffer 102-1 from the shift register array 10
Supplied to 3.

Similarly, each line buffer 102-2 to 102-
The outputs of 7 are line buffers 102-3 to 102-3 of the next stage.
It is supplied to the shift register array 103 together with 102-8, and the output of the last line buffer 102-8 is also supplied to the shift register array 103. These line buffers 102-1 to 102-8 are required by the number obtained by subtracting 1 from the number of coefficients forming one column of the coefficient array. In this configuration example, eight line buffers are required. Become. Each line
From the buffers 102-1 to 102-8, eight data delayed by one line with respect to the input data are output. That is, nine pieces of data arranged in the column direction including the input data are supplied to the shift register array 103.

The shift register array 103 is composed of a plurality of shift registers D00 to D88 having the same number of stages as the number of coefficients constituting one row of the coefficient array (9 stages in this configuration example). Store up to 8 previous data for each row. The number of shift registers required is the same as the number of coefficients constituting one column of the coefficient array, and in the case of this configuration example, nine shift registers are required.

By adopting the above configuration, the shift
The partial array (9 rows and 9 columns) of the original two-dimensional data array is reconstructed on the register array 103. For example, when the first data of the first line is stored in the register D00, the second data of the first line is stored in the register D10.
The register D01 stores the first data of the second line, and the register D88 stores the ninth data of the ninth line. The partial array thus reconstructed corresponds to a two-dimensional coefficient array (9 rows and 9 columns). That is, the convolution processing can be performed in the convolution processing circuit 104 by using the data and coefficient array stored in the shift register array 103. Then, the scan conversion circuit 10 for returning the result to the original raster scan
Can be output via 5.

[0006]

[Problems to be Solved by the Invention] In the field of processing image data, which is a typical two-dimensional data, the data size to be handled is large and there is a strong tendency for it to become larger and larger. Further, in fields such as recording of image data and communication, conversion coding has come to be widely used for compressing the amount of data, and block scanning has become a general scanning order of data.

However, in the conventional signal processing apparatus for performing the convolution processing shown in FIG. 4, since the input data is required to be in the raster scanning order, the raster scanning is required to process the data in the block scanning order. A scan conversion circuit that converts to order is essential. Further, depending on the configuration of the latter stage, a scan conversion circuit for returning to the original scan format after the convolution processing is also required.

From block scan order to raster scan order,
Alternatively, in order to convert from the raster scanning order to the block scanning order, it is necessary to use a randomly accessible storage means such as SRAM. For example, LSI-LOGI
In L64765, which is an LSI manufactured by Company C, this processing is realized with a minimum capacity by devising the control method of SRAM, but the number of data forming one column of one block × 1 line You need as much capacity as the number of data. That is, the capacity of this storage means depends on the size of the two-dimensional data to be processed, and particularly when processing image data, a very large capacity is required. Since it is difficult to integrate this storage means together with other circuits, the storage means is often prepared separately. However, in addition to the increased number of parts, many signal lines such as addresses and data are required, which reduces the space factor.

Further, a line buffer for simultaneously obtaining data in the column direction is required to have a large scale depending on the data size. Therefore, a general-purpose data buffer such as a FIFO is used. I often do it. But,
As many as -1 (8 in the conventional example shown in FIG. 4) constituting one column of the coefficient array are required, which significantly reduces the space factor. Therefore, measures such as reducing the number of rows in the coefficient array have been taken at the expense of the convolution processing characteristics.

The present invention has been made in order to solve the above problems in a signal processing device for performing conventional convolution processing. The invention according to claim 1 is a block other than the column format as shown in FIG. In a device for performing a convolution process of data input in a scanning order and a two-dimensional coefficient array, a signal processing device capable of reducing the number of components constituting a circuit without sacrificing the characteristics of the convolution process. The purpose is to provide. A second aspect of the present invention aims to provide a signal processing device capable of omitting a scan conversion circuit, and the third aspect of the invention provides a signal processing device capable of omitting a shift register array. An object of the present invention is to provide a signal processing device capable of reducing the number of multiplications in convolution processing.

[0011]

In order to solve the above problems, the invention according to claim 1 divides a two-dimensional digital data array into a plurality of blocks of a predetermined size, and for each block. In a signal processing device that performs convolution processing of time-series input data obtained by scanning and a predetermined two-dimensional coefficient array, a scan conversion circuit that converts the scan order of the input data into a scan order of a column format. , The number of pieces of data forming one row of the two-dimensional digital data array and the number of pieces of data forming one column of the block having a predetermined size are set as one stage, and the scan conversion is performed. A delay unit capable of delaying the data output from the circuit by a predetermined number of stages and outputting the delay data of each stage, and the delay data of each stage of the delay unit and The serial / parallel conversion circuit that inputs the output data from the scan conversion circuit and outputs the column data in the same block in parallel, and the data output in parallel from the serial / parallel conversion circuit have the same row address. A shift register array for storing a predetermined number of data while shifting for each data, and a data register for extracting a plurality of data necessary for convolution processing from the data stored in the shift register array.
A signal processing device is configured by a selector and a convolution processing circuit that performs convolution processing using a plurality of data extracted by the data selector and the predetermined two-dimensional coefficient array.

By adopting such a configuration, it becomes possible to perform convolution processing on the block-scanned data without conversion into the raster scanning order, and therefore the input data is in the column format. If it is block-scanned, the scan conversion circuit itself can be omitted, and if it is block-scanned in another format, it is a much smaller circuit than in the case of conversion to raster scan. Can be configured. For example, the conversion from the block scan of the row format to the block scan of the column format can be realized by the storage means having the same capacity as the number of data forming one block by using the same processing method as the conventional one. Also, the number of delay means for obtaining data in the column direction can be significantly reduced.

According to a second aspect of the present invention, in the signal processing apparatus according to the first aspect, the scanning direction of the input data is defined in the block scanning order of the column format.
Characterized in that the scan conversion circuit is omitted,
Thus, when the input data is in the scanning order of the column format, the scan conversion circuit can be omitted. According to a third aspect of the present invention, in the signal processing device according to the first or second aspect, when the number of columns forming the two-dimensional coefficient array is 1, the serial / parallel conversion circuit includes a shift register array. It is configured to integrate the functions. When the coefficient array is composed of only one column as described above, the output of the serial / parallel conversion circuit can be directly supplied to the data selector, and the shift register array can be omitted. The invention according to claim 4 is
The signal processing device according to any one of claims 1 to 3, wherein a circuit that performs filter processing in the row direction is added to the output from the convolution processing circuit. This can reduce the number of multiplications in the convolution process.

[0014]

EXAMPLES Next, examples will be described. 1 is a block diagram showing an embodiment of a signal processing device according to the present invention. In this embodiment, two-dimensional digital data is divided into blocks of 4 rows and 4 columns, and convolution of time-series data obtained by scanning each block and a 2-dimensional coefficient array of 9 rows and 9 columns. The present invention is applied to a signal processing device configured to perform processing.

In FIG. 1, the input data is time-series data obtained by scanning a two-dimensional digital data array in a block scanning order in synchronization with the rising of a predetermined reference clock. Unless otherwise specified, data processing is performed in synchronization with this reference clock (note that the reference clock is omitted in FIG. 1).

First, the input data is converted by the scan conversion circuit 1 into a block scan order of a column format. When the data in the order of block scanning in the column format is obtained from the beginning, the scan conversion circuit 1 can be omitted. The data converted to the column format block scan order is
The data is supplied to the serial / parallel (S / P) conversion circuit 2-1 and the number of data of one line × 1 of one block.
It is delayed by the delay means having the delay amount of the number of data forming the column (4 in the case of this embodiment), that is, the data buffer 3-1. The data delayed by the data buffer 3-1 is supplied to the S / P conversion circuit 2-2 and
Further, a data buffer 3-2 having a delay amount of 4 lines
Will be delayed by. Two data buffers 3-1 and 3-2
The data delayed by a total of 8 lines is supplied to the S / P conversion circuit 2-3.

As shown in FIG. 2, the S / P conversion circuits 2-1 to 2-3 have the number of stages corresponding to the number of data (4 in the present embodiment) forming one column of one block. shift·
It is composed of a register 11 and output registers 12-1 to 12-4, and when all the data for one column in the same block is stored in the shift register, the stored data is output to the output register 12-1. Transfer to ~ 12-4. That is, S
12 from the / P conversion circuits 2-1 to 2-3 arranged in the column direction.
The data are output in parallel and supplied to the shift register array 4.

The shift register array 4 has a plurality of shift registers D00 to D88 having the same number of stages (9 in this embodiment) as the number of coefficients constituting one row of the coefficient array.
And stores the data output from the S / P conversion circuits 2-1 to 2-3 while shifting the data. Since the data arranged in the column direction is supplied from the S / P conversion circuits 2-1 to 2-3, a partial array (9 rows and 12 columns) of the original data array is provided on the shift register array 4. Reconstructed.

On the other hand, the address counter 5 counts the reference clock based on the synchronizing signal synchronized with the input data, detects the address of the input data, and outputs it. The address decoder 6 generates the timing of data transfer in the S / P conversion circuits 2-1 to 2-3 and the shift register array 4 based on the address from the address counter 5, and performs convolution processing. The control signal for selecting the data required for is output. This control signal designates which data stored in the registers of D44 to 47 is to be the center of the convolution processing. As shown in FIG. 3, with respect to the timing of S / P conversion. Stipulated.

The data selector 7 selects a plurality of necessary data from the data stored in the shift register array 4 based on the control signal input from the address decoder 6, and the convolution processing circuit. Output to the convolution filter of 8. For example, when the control signal designates the register D44, the registers D00 to
D08, D10 to D18, D20 to D28, D30 to D38, D40 to D
48, D50 ~ D58, D60 ~ D68, D70 ~ D78, D80 ~ D88
If the control signal designates the register D46, the data stored in the register D02 to D0A, D12 is read.
~ D1A, D22 ~ D2A, D32 ~ D3A, D42 ~ D4A, D52 ~
The data stored in D5A, D62 to D6A, D72 to D7A, D82 to D8A are read. Convolution processing circuit 8
Performs convolution processing using the data output from the data selector 7 and a predetermined coefficient array, and outputs the result via the scan conversion circuit 9 that converts the result into the original scan format.

By using the signal processing device having such a configuration, the convolution processing can be performed without converting the data input in the block scanning order into the raster scanning order, and therefore the scale of the scan conversion circuit. Can be reduced. Further, the number of delay means for obtaining the data in the column direction is significantly reduced. For example, in this embodiment, the number required in the conventional example, which is eight, is reduced to two. Therefore, it is possible to perform convolution processing of required characteristics without being bound by the space factor. On the other hand, the storage capacity per data buffer, which is a delay unit, is required to be larger than that of the conventional one, but a general-purpose data buffer has a large capacity such as a frame buffer for images. Things are supplied relatively cheaply, and there is no cost disadvantage.

In the above embodiment, if the input data is in the column format block scan order from the beginning, the scan conversion circuit itself can be omitted. Also,
In the above embodiment, the number of stages of the shift register array is the same as the number of coefficients forming one row of the coefficient array, but the output of the S / P conversion circuit is directly used for convolution processing. , The size of the shift register array can be reduced by one stage. Therefore, if the coefficient array is a one-dimensional column matrix, the shift
The register array can be omitted.

Further, when the two-dimensional coefficient array is equivalent to that obtained by multiplying a certain column matrix by a certain row matrix, the two-dimensional convolution processing is performed in the column direction and the row direction. It can be divided into two steps. That is, two-dimensional convolution processing can be performed with a configuration in which a processing circuit in the row direction is added to the configuration of the above embodiment. With this configuration, the number of multiplications in the convolution process can be reduced. For example, in the convolution process using a 9 × 9 coefficient array, the number of required multiplications can be reduced from 81 to 18.

[0024]

As described above on the basis of the embodiments,
According to the first aspect of the present invention, the data input in the block scanning order is not converted into the raster scanning order,
Since the convolution processing can be performed, the scale of the scan conversion circuit and the number of components can be reduced, which can reduce the cost and improve the reliability of the device, and further reduce power consumption and radiation. Effects such as noise reduction and processing time reduction are also obtained. According to the second aspect of the invention, the scan conversion circuit itself can be omitted by setting the input data in the block scanning order of the column format from the beginning. According to the invention of claim 3, when the number of columns forming the two-dimensional coefficient array is 1,
The shift register array can be omitted by providing the serial / parallel conversion circuit with the function of the shift register array. According to the invention described in claim 4, the number of multiplications in the convolution processing can be reduced by adding a circuit for performing the filter processing in the row direction on the output from the convolution processing circuit.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a signal processing device according to the present invention.

2 is a block diagram showing a configuration example of an S / P conversion circuit in the embodiment shown in FIG.

FIG. 3 is a diagram showing timings of output signals of the address decoder in the embodiment shown in FIG.

FIG. 4 is a block diagram showing a configuration example of a conventional signal processing device.

FIG. 5 is an explanatory diagram showing aspects of a raster scanning order.

FIG. 6 is an explanatory diagram showing a mode of a block scanning order of a column format.

[Explanation of symbols]

 1,9 Scan conversion circuit 2-1, 2-2, 2-3 S / P conversion circuit 3-1, 3-2 Data buffer 4 Shift register array 5 Address counter 6 Address decoder 7 Data selector 8 Convolution processing circuit 11 Shift register 12-1, 12-2, 12-3, 12-4 Output register 101,105 Scan conversion circuit 102-1 to 102-8 Line buffer 103 Shift register array 104 Convolution Processing circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 7/30

Claims (4)

[Claims] 1. A two-dimensional digital data array is divided into a plurality of blocks of a predetermined size, and time-series input data obtained by scanning each block and a predetermined two-dimensional coefficient array are combined. In a signal processing device for performing a volatility process, a scan conversion circuit for converting the scan order of the input data into a scan order of a column format, the number of data constituting one row of the two-dimensional digital data array, and the predetermined number. The data output from the scan conversion circuit is delayed by a predetermined number of stages, with the number of data obtained by multiplying the number of data forming one column of a block of size as one stage, and the delay data for each stage is Inputting the delay means capable of outputting, the delay data of each stage of the delay means and the output data from the scan conversion circuit, the column data in the same block are arranged in parallel. A serial / parallel conversion circuit for outputting to a column and a shift register array for storing a predetermined number of data while shifting data output in parallel from the serial / parallel conversion circuit for each data having the same row address A data selector for extracting a plurality of data necessary for convolution processing from the data stored in the shift register array, the plurality of data extracted by the data selector, and the predetermined two-dimensional coefficient And a convolution processing circuit that performs convolution processing using an array. 2. The signal processing apparatus according to claim 1, wherein the scan conversion circuit is omitted by defining a scanning direction of the input data in a block scanning order of a column format. 3. The serial / parallel conversion circuit is configured to integrate the functions of the shift register array when the number of columns forming the two-dimensional coefficient array is one. The signal processing device according to claim 1. 4. The signal processing device according to claim 1, further comprising a circuit that performs a filtering process in a row direction on an output from the convolution processing circuit.