JPH08137749A - Cache memory device - Google Patents

Abstract

PURPOSE: To improve efficiency by flexibly allocating cache capacity among the processors on a cache memory device in the computer of a multiprocessor system. CONSTITUTION: The cache memory device of the multiprocessor system is provided with plural cache controllers 2 which exist in corresponding to the processors 1 and which are provided with hit rate measurement means 7, plural cache memory units 3, switch means 6 controlling a connection relation between the respective cache controllers 2 and the respective cache memory units 3 and a hit rate comparison means 5 comparing the outputs of the hit rate measurement means 7 in the respective cache controllers 2. The switch means 6 changes over the respective cache memory units 3 so that the hit rates of the respective cache controllers are averaged in corresponding to the output of the hit rate comparison means 5 at a prescribed period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device in a multiprocessor computer.

A high-speed memory device is arranged between a processor and a memory, and the locality of memory access is used to speed up access. This high speed memory device is a cache memory device. In order to improve the processing capacity of the computer system, in a multiprocessor system using a plurality of processors, it is necessary to prepare a cache memory device for each processor.

[0003]

2. Description of the Related Art In a conventional multiprocessor system,
The cache memory device existed independently for each processor and therefore its capacity was fixed.

FIG. 5 is a conceptual view of the configuration of the prior art. This system has m (# 1 ~ #m) processors 1 and m (# 1 ~ #)
m) cache controller 2, n (# 1 to #n) cache memory units 3, processor 1
A fixed cache controller 2 and a fixed cache memory unit 3 are connected to. That is, the processor 1 can access only the predetermined cache memory unit 3. Generally, the cache capacity provided in the processor 1 is constant. In the example shown in FIG. 5, each unit is composed of two units.

When the processor 1 accesses its own cache memory device (cache controller 2 and cache memory unit 3) and there is no necessary data, the cache controller 2 will store data in the main memory device 4. To get the data you need. If the required data exists (hits) in the cache memory device, the data can be obtained quickly, but if it does not exist, the performance of the main memory device is much slower than that of the cache, and the performance decreases. .

[0006]

In a multiprocessor system, the contents of processing differ for each processor. Therefore, depending on the processing contents of the processor, the hit rate is high because the cache capacity provided by one processor is sufficient, but the cache capacity provided by other processors is insufficient, and the performance will drop because there will be no hits. The situation occurs. In this case, the performance of the entire system also deteriorates. Moreover, since the processing contents of the processor change with time, such a state changes with time.

According to the present invention, the connection of the cache memory unit is changed according to the situation such as the load of the processor,
The purpose is to increase the hit rate as a whole, that is, to improve the efficiency of the system, by allowing the processors in the system to be flexible.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention is a cache memory device in a multiprocessor system, which exists corresponding to the processor 1 and has a plurality of cache controllers 2 provided with a hit rate measuring means 7, and a plurality of cache memory devices.
The hit ratio comparing means 5 for comparing the output of the unit 3, the switch means 6 for controlling the coupling relationship between each cache controller 2 and each cache memory unit 3, and the output of the hit rate measuring means 7 of each cache controller 2. Have and.

The cache memory unit 3 is mainly composed of a data memory holding a plurality of data blocks for copying blocks of the main memory and a tag memory holding address correspondence information of these blocks.

The switch means 6 is means for deciding which cache controller each cache memory unit 3 is connected to. At a predetermined time, according to the output of the hit ratio comparison means 5, the cache controller with the high hit ratio is switched to the cache controller with the low hit ratio.

The switch means 6 does not necessarily need to switch all the cache memory units 3.
You may comprise so that a part may be switched.

[0012]

According to the present invention, the cache memory unit 3 is assigned to each processor 1 (actually, the cache controller 2
To) Assign according to the operation status. That is, the cache memory capacity is dynamically changed so as to be allocated to a processor that requires a large amount.

The cache hit rate for each processor is used as an index for determining the operating status of the cache memory device. The hit rate is the rate at which the data is present in the cache memory device when the processor 1 accesses the memory data. Since the cache memory device can be accessed faster than the main memory device, the higher the hit rate, the higher the performance.

The hit rate measuring means 7 of the cache controller 2 calculates the cache hit rate from the value obtained by integrating the memory access count and the value obtained by integrating the cache hit count from the response of the cache memory unit 3 for each memory access. Can be calculated.

The hit rate comparing means 5 compares the hit rates calculated by the hit rate measuring means 7 of each cache controller 2. As a result, the processor (cache controller) with a low hit rate, the processor with a high hit rate (cache controller), the difference between them, and the like are determined and output.

The switch means 6 is configured to operate the cache memory unit 3 at a predetermined time (for example, periodically, when the difference between the hit ratios exceeds a certain value, or when a specific event occurs). The cache memory assigned to the cache controller with the highest hit ratio by controlling the switch that switches the signals (address line, data line, and control line) between the cache controller 2 and the cache controller 2.
Switch one of the units to assign it to the cache controller with the lowest hit rate. As a result, after that, the hit rate of the highest processor decreases, but the hit rate of the lowest processor improves, and the hit rate for each processor is averaged. Therefore, the overall system performance is high.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a structural explanatory view showing the essential parts of an embodiment of the present invention. It should be noted that this figure is mainly shown at the time of reading from the memory, and is omitted at the time of writing.
The same functions as those in FIG. 1 are designated by the same reference numerals.
Embodiments of the present invention will be described below with reference to the drawings.

This embodiment is a multiprocessor system consisting of two processors, and each of the two processors 1a and 1b has one cache controller 2a and 2b, and four cache memory units 3a, 3b and 3c. , 3d
Occupies one of the two (3a and 3d) respectively, but the remaining two
Share 3b, 3c. Cache memory unit 3a
~ 3d judges cache hit / miss for each access and notifies the result to the cache controller (extends from cache memory units 3a-3d in the figure)
H "line). A switch circuit 61 is provided between the cache memory units 3b and 3c and the cache controllers 2a and 2b.
Therefore, the cache controller 2 switches which cache controller 2 the judgment result in the cache memory unit 3 is applied to. Similarly, the address line, the data line and other signal lines are switched by the switch circuit 61.

FIG. 3 shows the cache memory of this embodiment.
It is explanatory drawing of a structure and operation | movement of a unit. The cache memory unit 3 copies the main memory data in block units with 64 bytes as one block. It has a data memory 32 for storing copy data and a tag memory 31 for storing the correspondence information between the data and the main memory block. The data memory 32 divides the 16 KB address space into 256 areas by the lower 8 bits of the block address, and stores one data block in each area. Further, the tag memory 31 holds information about which block of the main memory is recorded for each area. Besides, the input block address and tag memory 31
Comparator 33 for comparing with the block address recorded in
And a selection circuit 34 for switching whether to output the data stored in the data memory 32 (and selecting the data according to the in-block address).

The operation of the cache memory unit will be described below. When an address (block address + intra-block address) is given to the cache memory unit 3, it is determined which area is accessed from the lower 8 bits of the block address.

Next, the tag memory 31 is referenced to read out which block address is stored in the area. The comparator 33 compares the upper value of the block address with the output value of the tag memory 31.

If they match, there is a cache hit, the data is read from the data memory 32, and the data specified by the lower address (intra-block address) is cached.
Output to the controller 2. At the same time, notify that there is a cache hit.

If they do not match, the data is not output from the data memory 32. The cache controller 2 is notified of the cache miss. In this case, the cache controller 2 performs a process of reading data from the main storage device 4.

In FIG. 2, as the hit rate measuring means 7 in the cache controller 2, a counter 71 for accumulating the number of accesses to the memory and a counter 72 for accumulating the number of cache hits sent from the cache memory unit 3 are included. With and. When the access count reaches a certain value, the access count integration counter 71 sends a signal to the hit number integration counter 72 and the register 73. This signal holds the value of the hit number integration counter 72 in the register 73 and clears the hit number integration counter 72. After this,
Recount new hits. The number of cache hits held in the register 73 is sent to the comparator 5. Here, the value sent to the comparator 5 is the number of cache hits with respect to a fixed number of memory accesses, which corresponds to the cache hit rate. With this mechanism, the cache hit rate is updated every time each processor makes a certain number of memory accesses.

The comparator 5 compares the cache hit rates of the cache controllers 2 at appropriate intervals. This interval may be a fixed cycle or an appropriate event. It may be set independently of the interval at which the hit rate is updated in each cache controller 2.

The comparison result of the hit ratios obtained by the comparator 5 is transmitted to the switch means 6. In this example, two cache memory units 3b and 3c out of the four cache memory units 3a to 3d are connected to the cache controller 2 through the switch means 6. The switch means 6, according to the result from the comparator 5,
The cache controller 2 to which the memory units 3b and 3c are connected is determined.

The switch means 6 comprises a 2-bit shift register 60 and a switch circuit 61. If the absolute value of the difference between the hit rates of the cache controllers 2a and 2b is greater than or equal to a predetermined value and is a positive value, an'L '(logical' 0 ') value is given; if a negative value, an'H' (logical value is given. '1') value shift register
Shift in to 60. Otherwise, leave it as is. Switch circuit 61 of cache memory unit 3b
Is connected to the cache controller 2a if the high-order bit of the shift register 60 is'H ', and if it is'L',
Connect to cache controller 2b. Similarly, the switch circuit 61 of the cache memory unit 3c is connected to the cache controller 2a if the lower bit of the shift register 60 is'H ', and is connected to the cache controller 2b if it is'L'. .

FIG. 4 shows the structure of the switch circuit. (1)
Is an output switching circuit, which internally branches the signal from the cache memory unit and stops the signal to one cache controller according to the signal from the shift register 60. (2) is an input switching circuit, which switches the signals input from the two cache controllers 2 to the cache memory unit by the signals from the shift register 60. Therefore, in this embodiment, the processor is dynamically allocated with a maximum of 3 units and a minimum of 1 cache memory unit depending on the processing status.
It should be noted that the configuration may be such that all cache memory units are switched.

Since the cache controller needs to control a plurality of cache memory units, it must be able to handle the maximum number of units. For example, in this embodiment, it is a set associative, 3-way control circuit.

Even when the number of processors (cache controllers) and the number of cache memory units are different from those of this embodiment, the same configuration can be adopted.

[0031]

As described above, according to the present invention,
Dynamic control of cache memory unit (cache capacity) allocation according to the cache hit rate in a multi-processor system increases the cache hit rate of the entire system and improves system performance. it can.

[Brief description of drawings]

[Figure 1] Principle configuration diagram

FIG. 2 is a structural explanatory view showing a main part of the embodiment.

FIG. 3 is an explanatory diagram of the configuration and operation of a cache memory unit.

FIG. 4 is a configuration example of a switch circuit.

FIG. 5 is a conceptual diagram of a configuration of a conventional technique.

[Explanation of symbols]

1, 1a, 1b Processor 2, 2a, 2b Cache controller 3, 3a, 3b, 3c, 3d Cache memory unit 4 Main memory 5 Comparison means (comparator) 6 Switch means 60 Shift register 61 Switch circuit 7 Hits Rate measuring means 71 Access count integration counter 72 Hit count integration counter 73 Register 74 OR circuit

Claims (1)

[Claims] 1. A cache memory device in a multi-processor system, comprising a plurality of cache controllers which are provided corresponding to a processor and which are provided with hit ratio measuring means, a plurality of cache memory units, and each cache memory device. Controller and each cache memory
It has a switch means for controlling the coupling relationship with the unit and a hit rate comparing means for comparing the outputs of the hit rate measuring means, and the switch means responds to the output of the hit rate comparing means at a predetermined time. Cache controller and cache
A cache memory device, characterized in that it is configured to change a coupling relationship with a memory unit.