JPH08137747A - Internal register circuit - Google Patents

Abstract

PURPOSE: To facilitate access by initializing a logical state stored in a first/last flip flop when an address stored in a previous address register and the type of access do not match with the address of present access and the type of access. CONSTITUTION: An address comparator 16 compares the address stored in the previous address register 12 and the type of access (read or write access) with the address of an address signal on an address bus A, which is inputted at present access, and the type of access (read or write access). When they are judged to be dissident as the result of comparison, the address comparator 16 initializes a logical state stored in the first/last flip flop 14 by a control signal 26B. Thus, write access and read access to an internal register 3A can easily be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of internal registers including at least one internal register having a bit length longer than the bit length n of an external data bus, and any one of these internal registers. Address and select
Further, the present invention relates to an internal register circuit for accessing the selected internal register having a bit length longer than the bit length n in units of the bit length n, in particular, write access to the internal register. And an internal register circuit that makes read access easier.

[0002]

2. Description of the Related Art CP as the center of computer systems
U (central processing unit) is mainly composed of
An ALU (arithmetic logical unit), various registers, and a control circuit for controlling the overall timing are provided. In addition, in the register, for example, the AL
There is a program counter as well as an accumulator and a general-purpose register used for operations in U.

A general computer is usually a CP.
A predetermined system bus is used when the U accesses various peripheral devices such as a main storage device and an input / output device. According to such a system bus, it is possible to share the program command and data transmission paths in the computer, and to unify the interfaces of the peripheral devices in the computer. Further, with such a system bus, the scale of the interface portion occupying the entire computer hardware can be reduced.

An input / output device connected to such a system bus is provided with a register such as a control register (CR: control resister) which is accessed from the CPU via the system bus for setting an operation and a function. Is.

For example, MPU (micro processor unit)
Because it is a microcomputer system mainly composed of PIO (progra
mmedinput output) chip and USART (universal s
ynchronous asynchronous receiver transmitter) chip is prepared. Furthermore, DMA (direct memory)
access) Controller chip etc. are also prepared.

Such a PIO chip, a USART chip, a DMA controller chip, etc. usually have various internal registers for setting operation patterns and functions. For example, in a PIO chip, each I / O (inpu
t / output) has an internal register for setting the input / output direction of the signal of the port, the number of bits, and the like. Also, USART
The chip has internal registers for setting operation patterns and functions when converting serial data to parallel data or parallel data to serial data. For example, in a USART chip, a kind of internal register called a control register for setting serial communication asynchronously or synchronously, setting a data transfer rate in serial communication, setting an interrupt at the time of data reception, etc. I have it.

Further, in the DMA controller chip, D
In addition to a register (source address register) that stores a transfer source address and a register (destination address register) that stores a transfer destination address at the time of MA transfer, an internal register for setting various operation patterns is provided. . Also, there are some which have what is called a first last flip-flop, such as the "8237" chip manufactured by Intel Corporation in the United States.

FIG. 3 shows a conventional first last
It is a block diagram centering on an internal register circuit of a DMA controller having a flip-flop.

In FIG. 3, especially the internal register circuit of the DMA controller is a source address register SR.
, Destination address register DR, control register CR, first last flip-flop 14C, and upper / lower selection selector 24A to
24C, an internal register selection decoder 18C, and register selection buffers 22A to 22C.

First, the 16-bit source address register SR stores the start address of the transfer source in the DMA transfer. The source address register SR is composed of source address registers SR0 and SR1 each having an 8-bit length. The source address register SR0 is on the LSB (least significant bit) side,
The source address register SR1 is the MSB (most sig
nificant bit) side.

The 16-bit destination address register DR stores the start address of the transfer source at the time of DMA transfer. The destination address register DR is composed of destination address registers DR0 and DR1 each having an 8-bit length. The destination address register DR0 is on the LSB side, and the destination address register DR1 is on the MSB side.

The control register CR having a 16-bit length is a register for setting an operation pattern and a function at the time of DMA transfer. Further, the number of data (word number) to be transferred at the time of DMA transfer is also set in the control register CR. The control register C
R is also composed of control registers CR0 and CR1 each having an 8-bit length.

The internal register selection decoder 18C is
The signal of the address bus A from the outside is decoded. That is, according to the signal of the address bus A, the internal register selection decoder 18C selects any one of the register selection buffers 22A to 22C.

The first last flip-flop 14C is supplied with a control signal 26A which is in the H state when accessing any one of the internal registers shown in FIG. The first last
The flip-flop 14C inverts the stored logic state at the fall of the logic state of the control signal 26A.

According to the internal register circuit of such a DMA controller, any one of the internal registers SR, BR, CR, ... Is selected according to the address signal from the address bus A which is input while the control signal 26A is being input. You can select and access one. At this time, in the first access, the output of the first last flip-flop 14C is set to the L state, and the 8 bits on the LSB side of any of the internal registers SR, DR, CR ... The internal registers SR0, DR0, C
Any one of R2 ... Can be accessed by switching the upper / lower selection selectors 24A to 24C by a control signal 27A.

After this, at the time of the second access, the L stored in the first last flip-flop 14C by the fall just before the control signal 26A.
The logical state of the state is inverted to the H state. For this reason,
In this second access, the internal registers SR, DR, CR ...
MSB side, that is, the internal registers SR1 and DR
Any of 1, CR1, ... Can be accessed.

According to such an internal register circuit, 8
In the data bus D of bit length, longer than 16
It is possible to easily access the internal registers SR, DR, CR ... Of bit length.

Regarding the addresses assigned to such internal register circuits, the internal registers SR,
8 bits on the LSB side of DR, CR, ... And 8 bits on the MSB side are common. For example, the address of the source address register SR0 and the address of the source address register SR1 are common. Therefore, according to such an internal register circuit, the internal registers SR0, DR0,
The number of addresses assigned to CR0 ... SR1, DR1, CR1 ... Can be halved.

For example, the source address register SR
Alternatively, the bit length of the destination address register DR may be made longer than the bit length n of the data bus D, and the number of internal registers may be increased. For example, the source address register SR and the destination address register DR may have 32-bit length. In such a case, when accessing in units of 8 bits, if four addresses are set for each internal register, it becomes necessary to allocate a very large number of addresses as a whole. However, according to the internal register circuit as shown in FIG. 3, one I / O address is shared by 16 bits on the LSB side of each internal register and 16 bits on the MSB side are shared.
If one bit is shared, the assigned I
/ O address can be reduced. Further, it is possible to allocate a plurality of internal registers that may be continuously accessed to the same address space.

[0020]

In the internal register circuit of the DMA controller, in principle, the LSB side of the source address register SR is updated and the MSB is updated.
Side updates are generally done in pairs. or,
The same applies to the destination address register DR and the control register CR.

However, depending on the method of use, it may be sufficient to update only the 8 bits on the LSB side of the source address register SR or the destination address register DR, for example.

In such a case, in the internal register circuit shown in FIG. 3, it is necessary to perform a procedure for initializing the logic state stored in the first last flip-flop 14C. For example, LSB
When the destination address register DR0 on the LSB side is also accessed after accessing only the source address register SR0 on the side of the first address, the first last. Flip-flop 14
In order to initialize the logic state of C to the L state, for example, in the above-mentioned "8237" chip, "clear first.
It was necessary to execute the "last flip-flop command".

Since such a "clear first last flip-flop command" is required, for example, the setting program of the DMA controller performed prior to the DMA transfer becomes long and complicated.
In addition, in the case where the "clear first last flip-flop command" is used in this way,
The mistake is that this command is dropped even though it originally needs this command. In this case, an unexpected internal register is accessed, causing an erroneous operation. If you accidentally drop a command in this way, finding this out can be relatively difficult.

The present invention has been made to solve the above-mentioned conventional problems, and has a plurality of internal registers including at least one internal register having a bit length longer than the bit length n of the external data bus, One of a plurality of these internal registers is addressed and selected, and the selected internal register having a bit length longer than the bit length n is accessed in units of the bit length n. It is an object of the present invention to provide an internal register circuit configured so that write access and read access to the internal register can be performed more easily.

[0025]

SUMMARY OF THE INVENTION The present invention has a plurality of internal registers including at least one internal register having a bit length longer than the bit length n of an external data bus. In the internal register circuit, one of which is selected by addressing, and the selected internal register having a bit length longer than the bit length n is accessed in units of the bit length n. A previous address register that stores an address and a type of access (a read access or a write access) of the immediately previous access to any one of the plurality of internal registers, and an address and an access stored in the immediately previous address register Type (read access or write access) and one of the internal registers One of the internal comparator having a bit length longer than the bit length n and an address comparator for determining whether the address and the type of access this time (read access or write access) are performed On the other hand, when accessing each part in units of the bit length n, an incremental register that stores the position of the accessed part is provided, and if the comparator determines that they do not match, the incremental register is reset. By doing so, the above-mentioned problems are achieved.

Further, in the internal register circuit, at least one of the internal registers stores some address, and further, the selected internal register has a bit length longer than the bit length n. On the other hand, when accessing each part in the unit of the bit length n, the internal register is accessed in order from the LSB side, thereby achieving the above-mentioned problems and, for example, address setting of a DMA controller or the like. The configuration is more adapted and access is easier.

[0027]

In the conventional internal register circuit shown in FIG. 3, if only the internal register on the LSB side is accessed and the internal register on the MSB side is not accessed, the first last flip-flop 14C is used.
The present invention is made paying attention to the fact that it is necessary to initialize.

Conventionally, as described above, for example, the "clear first last flip-flop command" or the like is used. Here, in the present invention, a structure for automatically initializing the first last flip-flop 14C without using such a command has been found.

If the address of the access performed this time in the internal register circuit matches the address of the access immediately before and the type of access (read access or write access), the previous access is L.
It is an access to the internal register on the SB side, and this access is generally an access to the internal register on the MSB side. On the other hand, when the address of the immediately preceding access or the type of access (read access or write access) does not match the address of the current access, the meaning of the logical state stored in the first last flip-flop 14C becomes meaningless. . Therefore, in the case of such a mismatch, it is generally necessary to initialize the first last flip-flop 14C prior to the second access.

Focusing on such a point, in the present invention, one of the plurality of internal registers in the internal register circuit is used.
The address of the immediately preceding access and the type of access (read access or write access) made to one of the two are stored in the immediately preceding address register. Further, in the present invention, the address and access type (read access or write access) stored in the immediately preceding address register, and the address and access type of the current access performed to one of the plurality of internal registers. A match is determined by the comparator with (read access or write access). When the comparator determines that they do not match, the first last flip-flop 14C is reset (initialized) in the present invention.

As described above, in the present invention, when the internal register different from the address accessed immediately before is accessed this time, or when the type of access different from the previous access is performed, the first last The flip-flop 14C is automatically reset (initialized). This kind of access different from the immediately preceding access means that the read access is performed last time and the write access is performed this time, or the write access is performed the last time and the read access is performed this time. is there. Therefore, as described above,
Since the last flip-flop 14C is automatically reset, there is no need for the "clear first last flip-flop command" as in the conventional case shown in FIG. 3, and write access and read access to the internal register can be further performed. It can be done easily.

In the prior art of FIG. 3, the 16-bit length source address register SR and the like are accessed in two 8-bit units.
However, the present invention is not limited to such a case, and may be one in which the access is sequentially performed in two or more times. For example, an internal register having a length of 32 bits may be divided into four 8-bit units and sequentially accessed. In such a case, it is necessary to provide at least a counter that corresponds to the first last flip-flop 14C and can store at least the number of times of sequential access in units of bit length of the data bus. is there.

For example, it is necessary to provide the partial address register 14a and the incrementer 14b of the second embodiment described later. Even in such a case, the present invention is applied to the address stored in the immediately preceding address register and the type of access (read access or write access) and one of the plurality of internal registers. If the access address and the type of access (read access or write access) do not match, the partial address register 14
It suffices to initialize a.

[0034]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of an internal register circuit to which the present invention is applied, which is used in a DMA controller.

As shown in FIG. 3, the internal register circuit of the first embodiment comprises an internal register group 3A, an internal register selection decoder 18A and an address comparator 16. Further, the internal register group 3A is
A source address register SR, a destination address register DR, a control register CR,
I / O access digitizing circuit 5, immediately preceding address register 12, and first last flip-flop 14A
It is composed of

First, the source address register SR,
Each of the destination address register DR and the control register CR has the same structure as the conventional one shown in FIG.

The I / O access digitizing circuit 5 has an I
O read signal IORD and IO write signal IOWR
Has been entered. The source address register SR
Or the destination address register DR,
The IO read signal IORD is in the H state during a read access to the control register CR, and the IO write signal IOWR is in the H state during a write access. Further, the I / O access digitizing circuit 5 is "0 (L state)" at the time of read access.
Signal B of “1 (H
The signal B of "state)" is output.

The immediately preceding address register 12 is input from the outside via the address bus A, the source address register SR, the destination address register DR or the control register C.
Inputting from the I / O access digitizing circuit 5 which stores the address of the immediately preceding I / O access for selecting any one of R and digitizes the type of the immediately preceding I / O access, The logic state of the signal B is stored. Here, by storing the logical state of the signal B, the immediately preceding I /
A logical state (bit data) indicating the type of O access is stored.

The first last flip-flop 14A corresponds to the first last flip-flop 14C. When accessing any one of the source address register SR, the destination address register DR, or the control register CR, depending on the logic state stored in the first last flip-flop 14A, the access is performed on the LSB side. Or 8 bits on the MSB side are selected.

Specifically, in the initial state where the L state is stored in the first last flip-flop 14A, the source address register SR0 and the destination address are responded to according to the address signal input from the address bus A. Either the register DR0 or the control register CR0 is selected by the internal register selection decoder 18A. On the other hand, when the H state is stored in the first last flip-flop 14A, the source address register SR
1. Either the destination address register DR1 or the control register CR1 is selected by the internal register selection decoder 18A.

Here, the immediately preceding address register 12
Stores the address signal input from the address bus A and the type of access (read access or write access). The timing of updating the address stored in the immediately preceding address register 12 and the type of access (read access or write access) is immediately after the access to the source address register SR, the destination address register DR, or the control register CR. Moreover, it is the timing before the next access. Specifically, it is the timing of the fall of the control signal 26A.

Further, the address comparator 16 inputs the address stored in the immediately preceding address register 12 and the type of access (read access or write access) and the address signal of the address bus A inputted at the time of this access. And the type of access (read access or write access). If it is determined that they do not match during the comparison, the address comparator 16 initializes the logic state stored in the first last flip-flop 14A by the control signal 26B. That is, the logic state stored in the first last flip-flop 14A is initialized to the L state. When it is determined that they do not coincide with each other, at least one of the I / O access address and the I / O access type (read access or write access, which is the access type) does not match. This is the case.

As described above, according to the first embodiment, the LS
After accessing any internal register of the source address register SR0, the destination address register DR0 or the control register CR0 on the B side, the LS of another internal register different from this is accessed.
When the source address register SR0, the destination address register DR0, or the control register CR0 on the B side is accessed, or the type of access different from the previous one while accessing the same address (write access after read access,
(Or vice versa), the control signal 26B from the address comparator 16 automatically initializes the first last flip-flop 14A. Therefore, unlike the conventional one shown in FIG. 3, for example, the "clear first last flip-flop command" is unnecessary. Therefore, the first
According to the embodiment, the present invention can be applied to more easily perform write access and read access to the internal register.

FIG. 2 is a block diagram of a second embodiment of an internal register circuit to which the present invention is applied, which is used in a DMA controller.

As shown in FIG. 2, in the second embodiment, each of the source address registers SR has an 8-bit length.
It is composed of R2. Further, the destination address register DR is composed of destination address registers DR0 to DR2 each having an 8-bit length. Further, the partial address register 14a and the incrementer are provided as the one corresponding to the conventional first last flip-flop 14C of FIG. 3 or the one corresponding to the first last flip-flop 14A of the first embodiment. An incremental register 14b is provided.

Further, the internal register selection decoder 18B is
The internal register selection decoder 18A of the first embodiment.
Is equivalent to The internal register selection decoder 1
Reference numeral 8B denotes one of the source address registers SR0 to SR2 and the destination address according to an address signal externally input via the address bus A and a partial address A3 input from the partial address register 14a. Any one of the registers DR0 to DR2, or the control register CR0,
Either one of CR1 is selected.

In the second embodiment as described above, the internal register selection decoder 18B responds to the address signals from the two address lines from the address bus A taking the values of "0" to "2". The source address register SR, the destination address register DR,
Alternatively, one of the control registers CR is selected. When an address of “0” is input from the address bus A, the internal register selection decoder 18
B selects any one of the source address registers SR0 to SR2. When "1" is input from the address bus A, the internal register selection decoder 18B
Are the destination address registers DR0 to DR0.
Select any one of DR2. Further, the internal register selection decoder 18B receives the control register C when "2" is input from the address bus A.
Select R0 or CR1.

Here, the partial address register 14a
The initial value of is 0. The partial address register 14
The value a is sequentially incremented (value is incremented every time the source address register SR0 to SR2 is accessed, the destination address register DR0 to DR2 is accessed, or the control registers CR0 and CR1 are accessed. Is increased by “1”). This increment is performed by the incrementer 14b.

Here, the internal register selection decoder 1
8B is the source address register S selected by an address signal externally input to the address bus A.
One of R, the destination address register DR, or the control register CR selected from these internal registers is selected from the LSB side portion, the central portion, or the MSB side portion.

For example, when the address of the address bus A is "1" and the address A3 stored and output to the partial address register 14a is "1", the destination address register DR1 is selected. Alternatively, if the address of the address bus A is “2”,
When the address A3 is "0", the control register CR0 is selected. Also, the address A
If 3 is 2, the register SR2 or DR2 is selected according to the address of the address bus A.

The operation of the second embodiment will be described below using a specific example.

First, the source aldeus register SR0.
Consider a case where the 3 bytes of SR2 are sequentially read and accessed byte by byte.

Here, the partial address register 14A
The initial value stored in is set to "0". At this time, if an address "0" is input to the address bus A and read access is performed, the source address register SR0 is selected and read access can be performed. After the access, the address stored in the partial address register 14a is incremented by the incrementer 14b.

When a read access is made while inputting "0" from the address bus A, the value of the partial address register 14a is "1". Therefore, the source address register SR1 is selected and the read access is made. it can. Next, when accessing while inputting "2" to the address bus A, since the value of the partial address register 14a is "2" this time, the source address register SR2 is selected and the read access is performed. it can. After that, the value of the partial address register 14a is reset to "0". Specifically, the partial address register 14a is reset at this timing when the stored value is "2" and the control signal 26A falls, and the stored value becomes "0".

Here, the above description of the source address registers SR0 to SR2 is about the read access, but the source address registers SR0 to SR are the same.
The same applies to the write access to 2. That is, the above-mentioned "read access" is replaced with "write access".

Next, the source address register SR0
The following is a case of accessing the destination address register DR0 after the above access.

That is, first, the partial address register 14
It is assumed that the value of a is “0”. When an address "0" is input from the address bus A, the source address register SR0 is selected by the internal register selection decoder 18B or the like and can be accessed.

Thereafter, in order to access the destination address register DR0, the address bus A
Enter the address of "1". At this time, the address of "1" is different from the address of the immediately preceding access, that is, the address "0" at the time of access to the source address register SR0. Therefore, the address comparator 16 detects such an address mismatch and resets the value of the partial address register 14a to "0" by the control signal 26B.

For this reason, at the time of this access, the partial address A3 of "0" stored in the partial address register 14a and "1" of the address bus A is stored.
Accordingly, the internal register selection decoder 18B selects the destination address register DR0. At the time of this access, the partial address register 14a, that is, the one corresponding to the conventional first last flip-flop 14C shown in FIG. 3 is automatically reset. It is not necessary to execute the "Clear First Last Flip-Flop Command".

Next, the source address register SR0
When the source address register SR0 is read-accessed after the write-access, the following is performed.

That is, first, the partial address register 14
It is assumed that the value of a is “0”. Here, when an address "0" is input from the address bus A, the source address register SR0 is selected by the internal register selection decoder 18B or the like, and write access is possible.

Thereafter, the source address register SR0
Address bus A for read access to
Input the address of "0". At this time, the type of access is read access, which is different from the type of access immediately before, that is, write access. For this reason,
The address comparator 16 detects such a mismatch in access types and resets the value of the partial address register 14a to "0" by the control signal 26B.

Therefore, at the time of this access, the internal register selection decoder 18B selects the source address register SR0 according to the detection of the mismatch of the access types. At the time of this access, the partial address register 14a, that is, the one corresponding to the conventional first last flip-flop 14C shown in FIG. 3 is automatically reset. It is not necessary to execute the "Clear First Last Flip-Flop Command".

As described above, the present invention is applied to the second embodiment as well, and write access and read access to the internal registers, that is, the source address register SR, the destination address register DR, and the control register CR are performed. Can be made easier. Also, in the second embodiment, unlike the first embodiment, the source address register SR and the destination address register D are included.
R has a particularly 3-byte structure. The second embodiment can cope with such a case by using the incremental register to which the present invention is applied, which is composed of the partial address register 14a and the incrementer 14b.

The present invention is not limited to the internal register circuit used in the DMA controller as in the first embodiment and the second embodiment. However, it is more effective for an internal register circuit used in such a DMA controller or an internal register circuit incorporated in various timers and counters. This is because the DMA controller, the timer, the counter, and the like generally have an internal register longer than the bit length accessed through the data bus or the like.
This is because such an internal register stores, for example, an address and the like, and an internal register having such a long bit length is often accessed sequentially for each predetermined bit length.

Here, 1 is set for each predetermined bit length in this way.
When sequentially accessing one internal register, it is preferable to sequentially access the LSB side of the internal register. This is because the internal register accessed in a predetermined bit length unit is updated more frequently on the LSB side than on the MSB side when only a part of the internal register is updated.

Further, as described above, the conventional internal register circuit shown in FIG.
The one that uses the "flip-flop command" has the mistake of dropping this command even though it originally needs this command. In this case, an unexpected internal register is accessed, causing an erroneous operation. If you accidentally drop a command in this way, finding this out can be relatively difficult. However, in the present invention, since such a command is not used, there is an advantage that the reliability of the program can be further improved.

Further, according to the present invention, since there is no "clear first last flip-flop command" as described above, the program for setting data in the internal register can be shortened. For example, it is possible to make many accesses only to the source address register SR0 and the destination address register DR0 on the LSB side of the source address register SR and the destination address register DR. In this case, according to the present invention, the "Clear First Last Flip-Flop Command" which has been conventionally performed each time is not necessary, so that the length of the program can be greatly shortened.

Generally, in the DMA controller, the memory space as a transfer source or a transfer destination is a limited range to some extent. Therefore, the change range of the transfer source address and the transfer destination address is also limited. That is, M
The frequency of updating the source address register SR1 and the destination address register DR1 on the SB side is relatively low. Therefore, it is considered that access only to the source address register SR0 and the destination address register DR0 on the LSB side frequently occurs. In such a case, the present invention is more effective, a program for accessing the internal register can be more easily performed, and such a program is further shortened. Further, it is possible to shorten the execution time of the program for accessing such internal registers.

[0071]

As described above, according to the present invention,
Write access and read access to the internal register can be performed more easily, and further, the program for such access can be simplified, the program length can be shortened, and the program execution time can be shortened. An excellent effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of an internal register circuit to which the present invention is applied, which is used in a DMA controller or the like.

FIG. 2 is a block diagram of a second embodiment of an internal register circuit to which the present invention is applied, which is used in a DMA controller or the like.

FIG. 3 is a block diagram of a conventional internal register circuit used in a DMA controller or the like.

[Explanation of symbols]

3A, 3B ... Internal register group 12 ... Previous address register 14A, 14C ... First last flip-flop 14a ... Partial address register 14b ... Incrementer 16 ... Address comparator 18A-18C ... Internal register selection decoder 22A-22C ... Register selection Buffers 24A to 24C ... Higher / lower selection selectors 26A, 26B, 27A ... Control signal A ... Address bus CR ... Control register D ... Data bus DR ... Destination address register SR ... Source address register

Claims (2)

[Claims] 1. A plurality of internal registers including at least one internal register having a bit length longer than a bit length n of an external data bus, and any one of these internal registers is addressed and selected. And the bit length n
In the internal register circuit configured to access the selected internal register having a longer bit length in units of the bit length n, immediately before performing any one of the plurality of internal registers. Address register for storing the access address and the access type of the address, the address and the access type stored in the immediately previous address register, and the address for the current access to any one of the plurality of internal registers And an address comparator for determining a match with the type of access, and when accessing one of the selected internal registers having a bit length longer than the bit length n in units of the bit length n, Incremental registers that store the position of the part to be accessed. In this case, the internal register circuit is characterized in that the incremental register is reset. 2. The method according to claim 1, wherein at least one of the internal registers stores some address, and further, for at least one of the selected internal registers having a bit length longer than the bit length n. When accessing each part in units of the bit length n, the LSB of the internal register
An internal register circuit, which is configured to be accessed sequentially from the side.