JPH0813191B2 - Inverter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device, and more particularly to a built-in inverter power IC in which a drive circuit and a high voltage, high current output stage semiconductor element are monolithically integrated. It relates to a power supply means for a suitable drive circuit.

[Conventional technology]

A power IC in which a drive circuit and a high withstand voltage, high current output stage semiconductor element are monolithically integrated, preferably on one semiconductor substrate, is supplied to the drive circuit as a first power source to be applied to the output stage as an input power source. , And requires a second power supply whose voltage is lower than that of the first power supply. The second power source is
For example, in the case where the output stage element is an N-channel MOS transformer and has a three-phase inverter configuration, four voltage sources with different drive voltage reference voltages are required. Conventionally, a photocoupler or an isolation transformer is used for isolation. Each voltage source was input. However, since such a method is inconvenient, it is conceivable to make a power supply for the drive circuit inside the IC.

As a power supply means created inside such an IC, Japanese Patent Laid-Open No.
There is an example shown in Japanese Patent No. 59-15331. In this example, CMO
In order to prevent the latch-up of the S circuit, two power supply circuits are provided inside the integrated circuit, and the substrate terminal and the source terminal of the N and P channel MOS transistors are biased by four kinds of voltages supplied by the respective power supplies.

[Problems to be solved by the invention]

However, the method of this example is not suitable for an inverter whose output stage is composed of NMOS transistors, because the reference potentials of the voltages generated by the power supply circuits are equal. Also, with a kind of resistance voltage divider circuit using the voltage drop of the diode
Because the input voltage to the CMOS circuit is divided to create the desired voltage, if the power supply voltage applied to the output stage is much higher than the voltage created by the power supply circuit inside the IC, like a power IC, The temperature rise becomes a problem due to an excessive power loss caused by the resistance voltage division.

As described above, the conventional method does not consider that a plurality of voltage sources having different potential references are realized by a low-loss circuit, and when applied to a power IC, it causes a temperature rise as described above. There was a problem.

An object of the present invention is to realize a plurality of voltage sources having different reference potentials used in a drive circuit for positive and negative arms of an inverter device from an inverter main power source easily and with low loss.

[Means for solving problems]

The present invention relates to an inverter device in which positive and negative arm power switch elements are connected in series between DC power supply terminals, and switching control signal lines from corresponding drive circuits are connected to the control electrodes of both power switch elements. In, a series circuit having a first switch element sandwiched between the first and second capacitors is connected between both terminals of the DC power supply, and the first switch element is switched by the switching operation.
A capacitance dividing means for charging the first and second capacitors, and a charge pump means for charging the first capacitor to the third capacitor by a second switch element that performs a switching operation complementary to the above switching, Third
Is used as a power source for the drive circuit on the positive side and the second capacitor is used on the negative side.

[Action]

In the capacitive voltage dividing method used in the present invention, the period during which the charging current of the capacitor flows is short, and the loss generated by the resistance component is small. Further, when a charge pump is used to supply charges to another capacitor having a different reference potential and the second voltage source is charged by charging the capacitor, normally two capacitors are required. , One of the capacitors used for discharging the electric charges can also be used as the capacitor on the side that discharges electric charges, and simplification can be achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows a power supply circuit according to the present invention, the structure of which is shown below. First, 1 is a voltage source whose voltage value is a predetermined value E, and this voltage source 1 includes a switching means 5, a capacitor 2 having a capacitance value of C1, a switching means 6, and a capacitor having a capacitance C2. They are connected in series to form a closed circuit. The potential reference for this closed circuit is the negative terminal of the voltage source 1.

Next, switch means 7 is connected in parallel between the connection point of the voltage source 1 and the switch means 5 and the connection point of the capacitor 2 and the switch means 6. Between the connection point between the switch means 5 and the capacitor 2 and the positive terminal of the voltage source 1, the capacitor 4 having the electrostatic capacity C3 is connected in series.

Further, the current I ₁ is given to the capacitors 2 and 3 when the switch means 5 and 6 are closed and the switch means 7 is opened.
Current I ₂ is a current that supplies the charge accumulated in the capacitor 2 to the capacitor 4 when the switching means 5 and 6 are opened and the switching means 7 is closed. Voltages V ₁ , V ₂ and V ₃ are
Charge voltages of 3 and 4. Here, with respect to the capacitor 4, the potential reference is the voltage E of the voltage source 1.

Next, the operation of this embodiment will be described with reference to FIG. This figure shows the states of the above-mentioned switch means 5, 6, and 7 and the time charts of the charging voltages V ₁ , V ₂ and V ₃ of the capacitors 2, 3 and 4.

First, in the period t _{0 to} t ₁ , the switch means 5 and 6 are closed and the switch means 7 is opened. During this period, the charging voltage V ₂ of the capacitor 3 is expressed by the following equation from the partial voltage of the electrostatic capacitances C1 and C2.

V ₂ (t) = (C1 × E + C2 × V ₂₀ −C1 × V ₁₀ ) / (C1 + C2)
_{-C1 (V 10 + V 20 -E} ) / (C1 + C2) EXP [- (t-t ₀₎
/ T ₁ ] (1) where T ₁ = 2 × C1 × C2 × R / (C1 + C2) where R is the resistance of the switch means and V ₁₀ and V ₂₀ are capacitors at time t ₀ respectively. It is the initial voltage of C1 and C2.

The charging voltage V ₁ of the capacitor 2 is expressed by the following equation.

V ₁ (t) = C 2 × V ₂ (t) / C 1 (2) The charging period of the capacitors 2 and 3 is almost T ₁ , and the current I ₁ also flows only during this period, as shown in the following formula.

I ₁ (t) = C 2 × dV ₂ (t) / dt (3) The loss during the charging period is determined by the above I ₁ and the resistance R, but if the charging period T ₁ is short, the loss is sufficiently small. No problem. The period t _{0 to} t ₁ is referred to as a capacitive voltage dividing period.

In the period t ₁ ~t ₂ Next, switch means 5 and 6 are open, switch means 7 is closed. During this period, the capacitor 4
At time t ₁ , the voltage V ₁ (t ₁ ) is charged, and the switch means 5 and 6 are opened to be insulated.
Then, the switch means 7 is closed to supply the accumulated charge to the capacitor 4. At this time, the reference of the potential changes to the voltage E of the voltage source 1.

Considering the above, the capacitor 4 during this period
The voltage V _{3 of} is expressed by the following equation.

V ₃ (t) = _{[C3 × V 30 + C1 × V} 1 (t 1) ] / (C1 + C3)
+ C1 × [V ₃₀ -V ₁ (t _1)] / (C1 + C3) EXP [- (t-
t ₁ ) / T ₂ ] ... (4) where T ₂ = C1 × C3 × R / (C1 + C3) where V ₃₀ is the initial voltage of the capacitor C3 at time t ₁ .

The reference of the potential of the voltage V ₃ is E, and the reference voltage E is added in FIG.

As described above, the insulated capacitor 2 supplies electric charges to capacitors having different potential references, but such an operation is generally called a charge pump.

A feature of the present invention is that the capacitor 2 used for capacitive partial pressure can also be used as a charge pump.

The period t _{1 to} t ₂ is called a charge supply period.

In the next period t ₂ ~t _3, switch means 5, 6, and 7 will all open, the capacitor 3 and 4 act as a voltage source having different reference voltages. The values of the drops ΔV ₂ and ΔV ₃ of the voltage V ₂ and V ₃ during this period vary depending on the loads connected to the capacitors 3 and 4, but the above-mentioned drop exceeds the allowable value. It is necessary to shift to the charging period.

By periodically repeating the above period t _{0 to} t ₃ , the voltage V ₂
And V ₃ can be stably supplied.

As another embodiment of the present invention, there is a configuration as shown in FIG. In the figure, switch means 5 and 6 are connected between the voltage source 1 and the capacitor 2 and between the capacitor 2 and the capacitor 3, respectively, as in the embodiment of FIG. Here, the switch means 7 is connected in parallel to the path including the switch means 5 and the capacitor 2, and the switch means 8 is connected in parallel to the path including the capacitor 2 and the switch means 6. Switch means 5-8
Is repeatedly closed or opened by the oscillation circuits 9-1 and 9-2 at predetermined intervals.

Diodes D1 and D2 are connected from both electrodes of the capacitor 2 to one of the electrodes of the capacitor 4 in the energizing direction shown in FIG. The other electrode of the capacitor 4 is connected to the positive electrode of the voltage source 1 as in FIG.

The circuit operation of FIG. 3 will be described with reference to the time chart shown in FIG.

In FIG. 4, during the period t _{0 to} t ₂ , the switch means 5 is in the closed state (hereinafter, referred to as ON), and the switch means 6 is in the period.
Open state from t _{0 to} t ₁ (hereinafter referred to as OFF), period t ₁
Turns on at ~ t ₂ . Here, in the period t _{0 to} t ₁ , the discharge current of the capacitor 2 flows through the closed circuit composed of the capacitor 2, the diode D2, the capacitor 4, and the switch means 5. Due to this current, the capacitor 4 is supplied with electric charge and the voltage increases. This period corresponds to the charge supply period in the embodiment of FIG.

Next, in the period t ₁ ~t _2, the switch means 6 is turned on, the capacitive division of the capacitor 2 and 3, these capacitors are charged. At this time, the charging voltage of the capacitor 2 has the polarity shown in FIG. 3, which is reversed from the polarity in the charge supply period described above. Hereinafter, in the same figure, the polarity in the above periods t _{1 to} t ₂ is treated as a positive direction.
It should be noted that this period corresponds to the capacitive voltage dividing period of the embodiment shown in FIG.

In the next period t ₂ ~t _3, all switch means is turned off, acts as a voltage source to the capacitor 3 and 4 external load, respectively, correspond to the voltage supply period of the first FIG embodiment.

Period from the time t ₃ ~t ₆ serves the switch means 5 and 6 in to the time t ₀ ~t ₃ is replaced by switch means 7 and 8, respectively. That is, switch means 7 is turned on at time t ₃ ~t _5, and switch means 8 at time t ₄ ~t ₅ is turned on,
At time t ₅ ~t ₆ turned off both switches. Here, the capacitance component pressure period of time t ₄ ~t _5, the polarity of the charging voltage of the capacitor 2 is inverted again. However, with respect to the capacitors 3 and 4, the polarity of the charged voltage does not change.

The voltages of the capacitors 2, 3, and 4 in each of the above-mentioned periods can be expressed by using the above-mentioned equations (1) to (4). However, as described above, it is necessary to consider the polarity of the voltage V _{1 of the} capacitor 2 for each period.

Up to the above-described embodiment, the capacitors 3 and 4 are not connected to the load for supplying the charged voltage. Therefore,
The next embodiment shown in FIG. 5 shows a configuration including a circuit for supplying a voltage from the above capacitor.

FIG. 5 shows N channel MOS transistors 17-1 to 17-8.
Of a three-phase inverter, which is an example of a power conversion device configured with the above, each phase (only two phases are shown in the example of FIG. 5) of
This is an example in which the power supply circuit according to the embodiment of the present invention is suitable as a power supply for a drive circuit that supplies a drive voltage to a MOS. A region 20 surrounded by a broken line is a power supply circuit according to the present invention, and other circuit configurations are not directly related to the present invention, and therefore description thereof will be omitted.

In FIG. 5, 10-1, 10-2, ... 10-4 are N-channel MOS transistors, 11-1, 11-2, ... 11-8 are resistors, 12
Is a control circuit, 13 is an input signal, 14-1, 14-2, 14-3, ... 14-
9 is a P channel MOS transistor, 15-1, ... 15-8 is N
Channel MOS transistors 16-1, 16-2, ... 16-4 are Zener diodes, 17-1, 17-2, ... 17-8 are N channel MOS transistors constituting the output stage, 18-1, 18-2 … 18-4
Is a diode and 19 is a load. One-dot chain line 21-1, 21-2
The regions surrounded by are preferably integrated on a single semiconductor substrate. In some cases, at least one, and preferably all of the capacitors 2, 3, and 4 in the region 21-1 may be externally attached without being integrated on the semiconductor substrate.

The arrangement of the voltage source 1, the capacitors 2, 3, and 4, and the diodes D1, D2 is the same as that of the embodiment of FIG. Next, the switch means 5-8 in the embodiment of FIG.
Are P channel MOS transistors 5 to 8 in this embodiment.
And a resistor 11-1 connecting the source and gate of the transistor.
It is composed of 11-4. In addition, the P channel MOS
The transistors are turned on and off by the oscillator circuits 9-1 and 9-2.
N-channel MOS transistors 10-1 to 10- connected to
4 and resistors 11-5 to 11-8.

The difference from the embodiment shown in FIG. 3 is that one of the electrodes of the capacitor 4 is connected to the source electrodes of the P-channel MOS transistors 5 and 7. As a result, the closed circuit for dividing the capacitance of the capacitors 2 and 3 does not change. However, in the closed circuit for supplying the charges from the capacitor 2 to the capacitor 4, in the example shown in FIG. , A capacitor 4, a P channel MOS transistor 5, and a diode 18-1. However, the operation time charts of the P-channel MOS transistors 5 to 8 are the same as those shown in FIG.

The reason for changing the path for supplying electric charges as described above is
This is because current is supplied from the voltage source 1 to the three-phase inverter in addition to the power supply circuit 20, so that the current is prevented from being mixed in the path for supplying the electric charge.

The diodes 18-1 and 18-2 are P-channel MO
This is to prevent the influence of the parasitic diode of the S transistor.

The other circuit operations inside the power supply circuit 20 are the same as those in FIG.

In the above-described embodiments, the reference voltage for the charging voltage of the capacitor 4 is the voltage E of the voltage source 1, but as shown in the embodiment of FIG. It may be the negative electrode terminal.

In the embodiment shown in FIG. 6, in the embodiment shown in FIG. 1, the switch means 5 and 6 are arranged in the same manner as in the embodiment shown in FIG. 5 so that the P-channel MOS transistors 5 and 6 and the oscillation circuits 9 and N are provided.
Channel MOS transistors 10-1 and 10-2 and resistor 11-
It is composed of 1 to 11-4. The switch means 7 of FIG. 1 has its function performed by two transistors of a P channel MOS7 and an N channel MOS8 in FIG. 2 above
The two transistors respectively connect the capacitors 2 and 4 and form a closed circuit for charge supply. Further, the reference potential of the capacitor 4 is common to that of the capacitor 3, as shown in FIG.

When the reference potential is the same as in the present embodiment, there is a method of using the capacitors 3 and 4 as voltage sources having different voltage values by selecting the capacities of the capacitors 2, 3 and 4.

〔The invention's effect〕

According to the present invention, a plurality of voltage sources having different reference potentials used for the drive circuit of the positive and negative arms of the inverter device can be easily realized from the inverter main power source with low loss by the capacitance voltage dividing method and the charge pump method. effective.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a power supply circuit according to the present invention, FIG. 2 is a time chart showing the operation of the first embodiment, and FIG. 3 is a diagram showing a second embodiment of the present invention. FIG. 4 is a time chart showing the operation of the second embodiment, FIG. 5 is a view showing a third embodiment of the present invention, and FIG. 6 is a view showing a fourth embodiment of the present invention. . 1 ... Voltage source, 2-4 ... Capacitor, 5-8 ... Switch means, or specific P channel MOS transistor, 9 ... Oscillation circuit, D1, D2, and 18 ... Diode, 10 ... … N-channel MOS transistor, 11 …… Resistance, 1
2 ... Control circuit, 13 ... Input signal, 14, 15 ... P and N channel MOS transistors, 16 ... Zener diode, 1
7 ... Output stage N-channel MOS transistor, 19 ... Load,
20 ... Power supply circuit of the present invention, 21 ... Power IC incorporating the power supply circuit of the embodiment of the present invention.

Claims (3)

[Claims] 1. A power switch element for positive and negative arms is connected in series between both terminals of a DC power supply, and switching control signal lines from corresponding drive circuits are connected to control electrodes of both power switch elements. In the inverter device, a series circuit in which a first switch element 6 is sandwiched between first and second capacitors 2 and 3 is connected between both terminals of the DC power supply, and a switching operation of the first switch element 6 is performed. And means for charging the first and second capacitors, and means for charging the first capacitor 2 to the third capacitor 4 by the second switch element 7 that performs a switching operation complementary to the above switching, An inverter device characterized in that the third capacitor 4 is used as a power source for the drive circuit on the positive side and the second capacitor 3 is used on the negative side. 2. A power switch element of positive and negative arms is connected in series between both terminals of a DC power source, and switching control signal lines from corresponding drive circuits are connected to control electrodes of both power switch elements. In the inverter device, a bridge is formed by the first to fourth switching elements 5 to 8, the first capacitor 2 is connected to the output terminal of the bridge, and the series circuit of the bridge and the second capacitor 3 is connected to the direct current. Of the first to fourth switch elements that are connected between both terminals of the power source and that form the bridge, the first and second switch elements 5 and 6 that are connected in series via the first capacitor 2. And a means for charging the first capacitor 2 with an AC voltage by periodically repeating the operation of turning on the switch and then turning on the third and fourth switch elements 7, 8. Means for supplying the electric charge charged in the capacitor 2 to the third capacitor through a diode, and the third capacitor 4 as a positive side power source and the second capacitor 3 as a negative power source for the drive circuit. An inverter device characterized in that 3. The device according to claim 1, wherein at least the power switch element, the drive circuit, the switch element and the capacitor are formed on a single semiconductor substrate. Inverter device.