JPH08130297A - Infrared detector and manufacture thereof - Google Patents
Infrared detector and manufacture thereofInfo
- Publication number
- JPH08130297A JPH08130297A JP6267932A JP26793294A JPH08130297A JP H08130297 A JPH08130297 A JP H08130297A JP 6267932 A JP6267932 A JP 6267932A JP 26793294 A JP26793294 A JP 26793294A JP H08130297 A JPH08130297 A JP H08130297A
- Authority
- JP
- Japan
- Prior art keywords
- infrared
- detecting element
- infrared detecting
- layer
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000003776 cleavage reaction Methods 0.000 claims abstract description 34
- 230000007017 scission Effects 0.000 claims abstract description 34
- 150000001875 compounds Chemical class 0.000 claims abstract description 26
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims abstract description 20
- 238000001514 detection method Methods 0.000 claims description 38
- 239000013078 crystal Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 239000007788 liquid Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000005336 cracking Methods 0.000 description 5
- 229910004613 CdTe Inorganic materials 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は赤外線検出装置及びその
製造方法に関するものであり、特に、１０μｍ帯の赤外
線を検出する高感度のＨｇＣｄＴｅ赤外線検出装置、及
び、ＨｇＣｄＴｅ赤外線検出装置とシリコン信号処理回
路基板とを一体化させた赤外線検出装置及びその製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infrared detector and a method of manufacturing the same, and more particularly to a highly sensitive HgCdTe infrared detector for detecting infrared rays in the 10 μm band, and an HgCdTe infrared detector and a silicon signal processing circuit. The present invention relates to an infrared detection device integrated with a substrate and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、赤外線検出装置としてはＳｉをは
じめとして、各種の化合物半導体が用いられているが、
１０μｍ帯の赤外光を高感度に検出するためには、Ｈｇ
ＣｄＴｅ結晶が用いられていた。 図５参照 この従来の赤外線検出装置（赤外線固体撮像装置）は、
ＣｄＴｅ基板１１上にエピタキシャル成長させた厚さ１
０〜２０μｍのＨｇＣｄＴｅ層７に不純物の拡散等によ
り、多数のｐｎ接合を形成して赤外線検出素子８からな
るアレイを形成し、この赤外線検出素子アレイと、赤外
線検出素子８からの検出信号を処理する信号処理回路を
設けたシリコン半導体基板からなるシリコン信号処理回
路基板９とをＩｎバンプ１０を介して貼り合わせて形成
していた。2. Description of the Related Art Conventionally, various compound semiconductors such as Si have been used as an infrared detector.
In order to detect infrared light in the 10 μm band with high sensitivity, Hg
CdTe crystals have been used. See FIG. 5. This conventional infrared detection device (infrared solid-state imaging device)
Thickness 1 epitaxially grown on CdTe substrate 11
A large number of pn junctions are formed in the HgCdTe layer 7 of 0 to 20 μm by diffusion of impurities or the like to form an array of infrared detection elements 8 and the detection signals from the infrared detection element array and the infrared detection elements 8 are processed. And a silicon signal processing circuit board 9 made of a silicon semiconductor substrate provided with a signal processing circuit for forming the signal processing circuit.
【０００３】しかし、赤外線固体撮像装置の解像度の向
上が要求されるにつれて、画素数の増加が必要となり、
画素数の増加に伴ってチップサイズも大きくなっていっ
た。そして、チップサイズが大きくなるにつれて、赤外
線固体撮像装置の動作時において信号処理回路基板を構
成するＳｉと赤外線検出素子アレイを構成するＨｇＣｄ
Ｔｅとの熱膨張係数の差に起因する熱歪みの絶対量も大
きくなり、この熱歪みにより基板の反り等が生じてＩｎ
バンプの剥がれが発生し、赤外線固体撮像装置の信頼性
が低下する原因となっている。However, as the resolution of the infrared solid-state image pickup device is required to be improved, the number of pixels must be increased,
As the number of pixels increased, so did the chip size. Then, as the chip size increases, Si forming the signal processing circuit board and HgCd forming the infrared detection element array during operation of the infrared solid-state imaging device.
The absolute amount of thermal strain caused by the difference in thermal expansion coefficient from Te also increases, and the thermal strain causes warpage of the substrate and the like.
Peeling of the bumps is a cause of deterioration in reliability of the infrared solid-state imaging device.
【０００４】そこで、この問題を解決するために、成長
基板としてシリコン半導体基板を用い、このシリコン半
導体基板上にＨｇＣｄＴｅ結晶からなる赤外線検出素子
アレイを形成することや、信号処理回路を形成したシリ
コン半導体基板上にＨｇＣｄＴｅ赤外線検出素子を選択
的に形成することが提案されている。In order to solve this problem, therefore, a silicon semiconductor substrate is used as a growth substrate, and an infrared detection element array made of HgCdTe crystal is formed on the silicon semiconductor substrate, and a silicon semiconductor having a signal processing circuit is formed. It has been proposed to selectively form an HgCdTe infrared detection element on a substrate.
【０００５】図６（ａ）参照 まず、提案の一つは、シリコン半導体基板１上にヘテロ
エピタキシャル成長させたＨｇＣｄＴｅ層７に不純物の
拡散等により、多数のｐｎ接合を形成して赤外線検出素
子８からなるアレイを形成し、この赤外線検出素子アレ
イと、信号処理回路を形成したシリコン信号処理回路基
板９とをＩｎバンプ１０を介して貼り合わせるもので、
成長基板としてＣｄＴｅ基板の代わりにシリコン半導体
基板１を用いることによって赤外線検出素子アレイと、
シリコン信号処理回路基板９との熱膨張係数を略等しく
させるものであり、この構成によりＩｎバンプの剥がれ
を防止するものである。Referring to FIG. 6A, one of the proposals is to form a large number of pn junctions in the HgCdTe layer 7 heteroepitaxially grown on the silicon semiconductor substrate 1 by diffusing impurities, etc. The infrared detection element array and the silicon signal processing circuit board 9 on which the signal processing circuit is formed are bonded to each other via the In bumps 10.
By using the silicon semiconductor substrate 1 as the growth substrate instead of the CdTe substrate, an infrared detection element array,
The coefficient of thermal expansion of the silicon signal processing circuit board 9 is made substantially equal, and this configuration prevents the peeling of the In bump.
【０００６】図６（ｂ）参照 次に、もう一つの提案は、シリコン信号処理回路基板９
の信号処理回路を形成した側の面にＨｇＣｄＴｅ赤外線
検出素子１２を選択的に形成し、信号処理回路要素とＨ
ｇＣｄＴｅ赤外線検出素子１２とをボンディングワイヤ
等により電気的に接続するものであり、この場合にはＩ
ｎバンプを用いていないので、Ｉｎバンプの剥がれの問
題は生じないものである。なお、選択的に形成する方法
としては、成長阻止マスクを用いた選択エピタキシャル
成長法を用いれば良いものである。[0006] Next, another proposal is a silicon signal processing circuit board 9
HgCdTe infrared detection element 12 is selectively formed on the surface on which the signal processing circuit of FIG.
The gCdTe infrared detecting element 12 is electrically connected with a bonding wire or the like. In this case, I
Since the n-bump is not used, the problem of peeling the In-bump does not occur. As a selective formation method, a selective epitaxial growth method using a growth prevention mask may be used.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記の
２つの改良提案によって、Ｉｎバンプの剥がれの問題は
解消できるものの、前者においては成長基板としてシリ
コン半導体基板を用いているので、シリコン半導体基板
とＨｇＣｄＴｅ層の熱膨張係数の差によりＨｇＣｄＴｅ
層自体に剥離や割れが生じ、やはり信頼性に問題があっ
た。However, although the problem of peeling of the In bump can be solved by the above two proposals for improvement, since the silicon semiconductor substrate is used as the growth substrate in the former, the silicon semiconductor substrate and HgCdTe are used. HgCdTe due to the difference in the thermal expansion coefficient of the layers
Peeling and cracking occurred in the layer itself, and there was still a problem with reliability.
【０００８】このＨｇＣｄＴｅ層の剥離や割れの問題を
解決するためには、エッチングにより分離溝を設けてＨ
ｇＣｄＴｅ層を複数の小領域に分割して、ＨｇＣｄＴｅ
層にかかる歪みを低減すれば良いが、ウェット・エッチ
ングによってもドライ・エッチングによっても急峻な細
い溝を形成することが困難であるので、集積度の向上の
妨げとなり、また、分離溝部には赤外線検出素子を配置
できないので、解像度も低下することになる。In order to solve the problem of peeling or cracking of the HgCdTe layer, a separation groove is provided by etching to form H
The gCdTe layer is divided into a plurality of small regions, and HgCdTe is
Although it is sufficient to reduce the strain applied to the layer, it is difficult to form a sharp narrow groove by wet etching or dry etching, which hinders the improvement of the integration degree. Since the detection element cannot be arranged, the resolution is also reduced.
【０００９】一方、後者の場合には、信号処理回路要素
とＨｇＣｄＴｅ赤外線検出素子１２との電気的接続が非
常に困難であり、また、信号処理回路を形成したシリコ
ン半導体基板表面に選択エピタキシャル成長させること
も実際には非常に困難なものである。On the other hand, in the latter case, the electrical connection between the signal processing circuit element and the HgCdTe infrared detecting element 12 is very difficult, and selective epitaxial growth is performed on the surface of the silicon semiconductor substrate on which the signal processing circuit is formed. Is actually very difficult.
【００１０】したがって、本発明は、簡単な構造及び製
造工程によりＩｎバンプの剥がれ及びＨｇＣｄＴｅ層の
割れ・剥離をなくし、チップサイズの大きな高解像度の
赤外線検出装置の信頼性を高めることを目的とする。Therefore, it is an object of the present invention to eliminate the peeling of the In bump and the cracking / peeling of the HgCdTe layer by a simple structure and manufacturing process, and to enhance the reliability of a high resolution infrared detecting device having a large chip size. .
【００１１】[0011]
【課題を解決するための手段】図１は、本発明の原理的
構成の説明図であり、また、図２は本発明の第２の実施
例の原理的構成の説明図であり、この図１及び図２を用
いて課題を解決するための手段を説明する。FIG. 1 is an explanatory diagram of the principle configuration of the present invention, and FIG. 2 is an explanatory diagram of the principle configuration of the second embodiment of the present invention. Means for solving the problems will be described with reference to FIGS.
【００１２】図１（ａ）乃至（ｃ）参照 本発明は、赤外線検出装置において、シリコン等の単結
晶半導体基板１上に赤外線検出素子形成用化合物半導体
層２をエピタキシャル成長させたのち、赤外線検出素子
形成用化合物半導体層２の一辺にキズ３（図においては
３箇所）をつけ、このキズ３を起点とした劈開線４を形
成することにより赤外線検出素子形成用化合物半導体層
２のみを小領域に分割することを特徴とするものであ
る。1 (a) to 1 (c), the present invention relates to an infrared detecting device in which an infrared detecting device forming compound semiconductor layer 2 is epitaxially grown on a single crystal semiconductor substrate 1 such as silicon, and then the infrared detecting device is used. Scratches 3 (three places in the figure) are formed on one side of the compound semiconductor layer 2 for forming, and a cleavage line 4 starting from these scratches 3 is formed, so that only the compound semiconductor layer 2 for forming the infrared detection element is formed in a small region. It is characterized by division.
【００１３】また、本発明は、単結晶半導体基板１上に
赤外線検出素子形成用化合物半導体層２をエピタキシャ
ル成長させた半導体ウェハに周期的熱サイクルを加え、
単結晶半導体基板と赤外線検出素子形成用化合物半導体
層２との熱膨張係数の差に基づく歪みにより、赤外線検
出素子形成用化合物半導体層２のみに劈開を生じさせる
ことを特徴とする。また、本発明は、半導体ウェハを急
冷することによって歪みを与え、劈開を生じさせること
を特徴とする。Further, according to the present invention, a periodic thermal cycle is applied to a semiconductor wafer in which a compound semiconductor layer 2 for forming an infrared detection element is epitaxially grown on a single crystal semiconductor substrate 1.
It is characterized in that only the infrared detecting element forming compound semiconductor layer 2 is cleaved by the strain due to the difference in thermal expansion coefficient between the single crystal semiconductor substrate and the infrared detecting element forming compound semiconductor layer 2. Further, the present invention is characterized in that the semiconductor wafer is rapidly cooled to be distorted and cleaved.
【００１４】図２（ｂ）参照 また、本発明は、単結晶半導体基板１上にエピタキシャ
ル成長させた赤外線検出素子形成用化合物半導体層２の
複数の赤外線検出素子アレイ形成領域５を分離溝６によ
って互いに分離し、赤外線検出素子アレイ形成領域５ご
とにキズ３を設けて劈開し、劈開線４を形成することを
特徴とする。Further, according to the present invention, the plurality of infrared detecting element array forming regions 5 of the infrared detecting element forming compound semiconductor layer 2 epitaxially grown on the single crystal semiconductor substrate 1 are separated from each other by the separating groove 6. It is characterized in that the infrared ray detecting element array forming region 5 is separated, and a scratch 3 is provided for each infrared ray detecting element array forming region 5 for cleavage to form a cleavage line 4.
【００１５】[0015]
【作用】本発明においては、赤外線検出素子形成用化合
物半導体層のみを劈開線によって複数の小領域に分割す
るので、単結晶半導体基板との熱膨張係数の差に基づく
赤外線検出素子形成用化合物半導体層の剥離や割れが生
じなくなる。In the present invention, since only the compound semiconductor layer for forming the infrared detecting element is divided into a plurality of small regions by the cleavage line, the compound semiconductor for forming the infrared detecting element based on the difference in thermal expansion coefficient from the single crystal semiconductor substrate. No layer peeling or cracking occurs.
【００１６】また、半導体ウェハにキズを付けたのち、
周期的熱サイクルや急冷等の熱処理を加えることによっ
て劈開を発生させるので、プレスによる押圧等の機械的
力を加える必要がなく、赤外線検出素子の特性に悪影響
を与えることがなくなる。After scratching the semiconductor wafer,
Since cleavage is generated by applying a heat treatment such as a periodic heat cycle or rapid cooling, it is not necessary to apply a mechanical force such as pressing by a press, and the characteristics of the infrared detection element are not adversely affected.
【００１７】図２（ａ）参照 また、単結晶半導体基板上にエピタキシャル成長させた
赤外線検出素子形成用化合物半導体層の複数の赤外線検
出素子アレイ形成領域を劈開前に分離溝によって互いに
分離しておくので、図２（ａ）の場合のように劈開の影
響が他の赤外線検出素子アレイ形成領域に及ぶことがな
く、したがって、劈開線４が他の赤外線検出素子アレイ
形成領域に形成した赤外線検出素子を分断して素子不良
を起こすことがなくなる。Also, as shown in FIG. 2A, since a plurality of infrared detecting element array forming regions of the infrared detecting element forming compound semiconductor layer epitaxially grown on the single crystal semiconductor substrate are separated from each other by separation grooves before cleavage. As in the case of FIG. 2A, the influence of the cleavage does not extend to other infrared detecting element array forming regions, so that the cleavage line 4 can detect the infrared detecting elements formed in other infrared detecting element array forming regions. There is no possibility of device failure due to division.
【００１８】[0018]
【実施例】図３は本発明の第１の実施例の説明図であ
り、図３（ａ）は赤外線検出素子アレイの上面図であ
り、図３（ｂ）は図３（ａ）の一点鎖線で示すａ−ａ’
間において切断した場合の断面図であり、図３（ｃ）は
シリコン信号処理回路基板を一体化した場合の赤外線検
出装置の断面図である。FIG. 3 is an explanatory view of the first embodiment of the present invention, FIG. 3 (a) is a top view of an infrared detecting element array, and FIG. 3 (b) is one point of FIG. 3 (a). Aa 'shown by a chain line
FIG. 3C is a cross-sectional view in the case of being cut in between, and FIG. 3C is a cross-sectional view of the infrared detection device in which the silicon signal processing circuit board is integrated.
【００１９】図３（ａ）及び（ｂ）参照 まず、（１００）面のシリコン半導体基板１上に、（１
１１）面を主面とするｐ型Ｈｇ0.8 Ｃｄ0.2 Ｔｅ層７を
エピタキシャル成長させたのち、ボロン（Ｂ）等のｎ型
不純物をイオン注入等により導入してｐｎ接合を形成し
て多数の赤外線検出素子８からなる赤外線検出素子アレ
イを形成する。Referring to FIGS. 3A and 3B, first, (1) is formed on the (100) plane silicon semiconductor substrate 1.
11) After epitaxially growing the p-type Hg 0.8 Cd 0.2 Te layer 7 having the plane as the main surface, an n-type impurity such as boron (B) is introduced by ion implantation or the like to form a pn junction and a large number of infrared rays are detected. An infrared detection element array including the elements 8 is formed.
【００２０】次いで、安全剃刀の刃により赤外線検出素
子アレイの少なくとも一つの上辺の劈開を開始したい場
所にキズ３（図の場合には４箇所）を設けたのち、シリ
コン半導体基板１とＨｇ0.8 Ｃｄ0.2 Ｔｅ層７とからな
る半導体ウェハを、液体Ｎ2中へ浸漬して液体Ｎ2 温度
（７７°Ｋ）まで冷却し、次いで、半導体ウェハを液体
Ｎ2 中から引き上げて乾燥Ｎ2 を吹きつけることによっ
て室温まで昇温する熱サイクル、即ち、室温−液体Ｎ2
温度−室温の熱サイクルを１サイクルの周期を５分とし
て５サイクル行なってシリコン半導体基板１とＨｇ0.8
Ｃｄ0.2 Ｔｅ層７との熱膨張係数の差に基づく歪みによ
って劈開線４に沿った劈開を発生させ、Ｈｇ0.8 Ｃｄ
0.2 Ｔｅ層７のみを複数の小領域（図の場合には５個）
に分割する。Next, a scratch 3 (4 in the case of FIG. 3) is provided at a position where cleavage of at least one upper side of the infrared detection element array is to be started by a blade of a safety razor, and then the silicon semiconductor substrate 1 and Hg 0.8 Cd are formed. a semiconductor wafer consisting of 0.2 Te layer 7 for, by immersing into liquid N 2 in cooling to liquid N 2 temperatures (77 ° K), then blown dry N 2 by pulling the semiconductor wafer from the liquid N 2 By heat cycle, that is, room temperature-liquid N 2
A temperature-room temperature thermal cycle is performed for 5 cycles with a cycle of 5 minutes, and the silicon semiconductor substrate 1 and Hg 0.8
The cleavage along the cleavage line 4 is generated by the strain based on the difference in the coefficient of thermal expansion from the Cd 0.2 Te layer 7, and Hg 0.8 Cd
0.2 Te layer 7 only in multiple small areas (5 in the figure)
Split into.
【００２１】なお、この場合、シリコン半導体基板１と
Ｈｇ0.8 Ｃｄ0.2 Ｔｅ層７との劈開方向・劈開面は異な
るので、劈開線４の形成の際にシリコン半導体基板１に
劈開線４が走ることはない。また、劈開線４が赤外線検
出素子８を分断しないように、劈開の方向と赤外線検出
素子の配列方向との位置関係をオリエンテーションフラ
ットやＸ線回折を利用して確認しておく必要がある。In this case, since the cleavage direction and the cleavage plane of the silicon semiconductor substrate 1 and the Hg 0.8 Cd 0.2 Te layer 7 are different, the cleavage line 4 runs on the silicon semiconductor substrate 1 when the cleavage line 4 is formed. There is no. Further, it is necessary to confirm the positional relationship between the cleavage direction and the arrangement direction of the infrared detection elements by using orientation flat or X-ray diffraction so that the cleavage line 4 does not divide the infrared detection elements 8.
【００２２】図３（ｃ）参照 次いで、Ｉｎからなるバンプ１０を用いて赤外線検出素
子アレイを信号処理回路を形成したシリコン信号処理回
路基板９にアップサイドダウンにしてマウントし、赤外
線検出装置を完成する。この場合、シリコン半導体基板
１は１０μｍ帯の赤外線に対して透明であるので、シリ
コン半導体基板１側から入射した赤外線はシリコン半導
体基板１に吸収されることなくＨｇ0.8 Ｃｄ0.2 Ｔｅ層
７に設けたｐｎ接合に達することができる。Next, as shown in FIG. 3C, the infrared detecting element array is mounted upside down on the silicon signal processing circuit board 9 on which the signal processing circuit is formed using the bumps 10 made of In to complete the infrared detecting device. To do. In this case, since the silicon semiconductor substrate 1 is transparent to infrared rays in the 10 μm band, infrared rays incident from the silicon semiconductor substrate 1 side are provided on the Hg 0.8 Cd 0.2 Te layer 7 without being absorbed by the silicon semiconductor substrate 1. The pn junction can be reached.
【００２３】この様にして完成した赤外線検出装置を、
液体Ｎ2 温度に冷却して使用した場にも、シリコン半導
体基板１とシリコン信号処理回路基板９の熱膨張係数は
同じなのでＩｎバンプ１０の剥がれは発生せず、また、
Ｈｇ0.8 Ｃｄ0.2 Ｔｅ層７は劈開線４によって既に小領
域に分離されているので、分離された各Ｈｇ0.8 Ｃｄ
0.2 Ｔｅ層にかかる歪みは少なくなり、新たな割れ・剥
離は発生しない。The infrared detecting device thus completed is
Liquid N2Even when used after cooling to temperature, the silicon semiconductor
The thermal expansion coefficients of the body substrate 1 and the silicon signal processing circuit substrate 9 are
Since it is the same, peeling of the In bump 10 does not occur,
Hg0.8Cd0.2The Te layer 7 is already covered by the cleavage line 4.
Since it is separated into regions, each separated Hg0.8Cd
0.2The strain applied to the Te layer is reduced, and new cracks and peeling occur.
No separation occurs.
【００２４】なお、上記第１の実施例においては、キズ
３は安全剃刀の刃により形成しているが、このような方
法に限られるものではなく、ドライ・エッチング等のエ
ッチング法によって形成しても良いし、また、結晶面も
（１００）面と（１１１）面の組み合わせに限られるも
のではなく、例えば、（２１１）面のシリコン半導体基
板上に（２１１）面のＨｇＣｄＴｅ層を形成するように
しても良いものである。In the first embodiment, the scratches 3 are formed by the blade of a safety razor, but the invention is not limited to such a method, and the scratches 3 may be formed by an etching method such as dry etching. The crystal plane is not limited to the combination of the (100) plane and the (111) plane. For example, a (211) plane HgCdTe layer may be formed on a (211) plane silicon semiconductor substrate. However, it is good.
【００２５】図４は、本発明の第２の実施例の説明図で
ある。 図４（ａ）参照 まず、上記第１の実施例と同様に、（１００）面のシリ
コン半導体基板上に、（１１１）面を主面とするｐ型Ｈ
ｇ0.8 Ｃｄ0.2 Ｔｅ層７をエピタキシャル成長させたの
ち、複数の赤外線検出素子アレイ形成領域５にボロン
（Ｂ）等のｎ型不純物をイオン注入等により導入してｐ
ｎ接合を形成して多数の赤外線検出素子からなる赤外線
検出素子アレイを形成する。FIG. 4 is an explanatory diagram of the second embodiment of the present invention. Refer to FIG. 4A. First, as in the first embodiment, a p-type H having a (111) plane as a main surface is formed on a (100) plane silicon semiconductor substrate.
After the g 0.8 Cd 0.2 Te layer 7 is epitaxially grown, an n-type impurity such as boron (B) is introduced into the plurality of infrared detecting element array forming regions 5 by ion implantation or the like to p.
An n-junction is formed to form an infrared detection element array including a large number of infrared detection elements.
【００２６】図４（ｂ）参照 次いで、ドライ・エッチングにより、シリコン半導体基
板に達する分離溝６を形成して複数の赤外線検出素子ア
レイ形成領域５を互いに分離する。Next, referring to FIG. 4B, a plurality of infrared detecting element array forming regions 5 are separated from each other by forming a separation groove 6 reaching the silicon semiconductor substrate by dry etching.
【００２７】図４（ｃ）参照 次いで、ドライ・エッチングによって赤外線検出素子ア
レイ形成領域５の少なくとも一つの上辺における劈開を
開始したい場所にキズ３（図の場合には２箇所）を設け
たのち、シリコン半導体基板とＨｇ0.8 Ｃｄ0.2 Ｔｅ層
７とからなる半導体ウェハを、液体Ｎ2 中へ浸漬して液
体Ｎ2 温度まで冷却し、次いで、半導体ウェハを液体Ｎ
2 中から引き上げて乾燥Ｎ2 を吹きつけることによって
室温まで昇温する熱サイクル、即ち、室温−液体Ｎ2 温
度−室温の熱サイクルを１サイクルの周期を５分として
５サイクル行なって、シリコン半導体基板とＨｇ0.8 Ｃ
ｄ 0.2 Ｔｅ層７との熱膨張係数の差に基づく歪みによっ
て劈開線４に沿った劈開を発生させ、Ｈｇ0.8 Ｃｄ0.2
Ｔｅ層７のみを複数の小領域（図の場合には３個）に分
割する。なお、この場合、劈開の位置を確実にするため
に、キズ３は先端が鋭角の楔状の形状が望ましい。Next, as shown in FIG. 4C, the infrared detection element array is dry-etched.
Cleavage on at least one upper side of the ray forming region 5
Provide scratches 3 (2 places in the figure) at the place you want to start
After that, silicon semiconductor substrate and Hg0.8Cd0.2Te layer
And a semiconductor wafer consisting of2Liquid immersed in
Body N2The semiconductor wafer is cooled to a temperature, and then the semiconductor wafer is cooled with liquid N.
2Pull out from the inside and dry N2By blowing
Thermal cycle of raising temperature to room temperature, that is, room temperature-liquid N2Warm
Degree-room temperature thermal cycle with one cycle of 5 minutes
After performing 5 cycles, silicon semiconductor substrate and Hg0.8C
d 0.2Due to strain due to the difference in coefficient of thermal expansion from the Te layer 7,
Cleavage along the cleavage line 4 to generate Hg0.8Cd0.2
Divide only the Te layer 7 into a plurality of small areas (3 in the figure).
Divide. In this case, in order to ensure the cleavage position
In addition, it is desirable that the scratch 3 has a wedge-like shape with an acute tip.
【００２８】次いで、分離溝６に沿って半導体ウェハを
複数の赤外線検出素子アレイ形成領域５に分割してチッ
プ化した後、信号処理回路を形成したシリコン信号処理
回路基板９にＩｎからなるバンプ１０を用いて赤外線検
出素子アレイをアップサイドダウンにしてマウントし
て、赤外線検出装置を完成する。Next, the semiconductor wafer is divided into a plurality of infrared detecting element array forming regions 5 along the separation groove 6 to be made into chips, and then the bumps 10 made of In are formed on the silicon signal processing circuit substrate 9 on which the signal processing circuit is formed. The infrared detection element array is mounted upside down by using to complete the infrared detection device.
【００２９】この場合には、一つの赤外線検出素子アレ
イ形成領域５に走る劈開線４が、隣接する他の赤外線検
出素子アレイ形成領域５に及ぶことがないので、劈開の
方向と赤外線検出素子の配列方向との位置関係は、隣接
する他の赤外線検出素子アレイ形成領域５とは無関係に
一つの赤外線検出素子アレイ形成領域５内においてのみ
劈開線４が赤外線検出素子を分断しないように考慮すれ
ば良いので、劈開の方向と赤外線検出素子の配列方向と
の位置関係を極端に高精度に決める必要はなくなり、製
造が容易になる。In this case, the cleavage line 4 running in one infrared detecting element array forming region 5 does not reach the other infrared detecting element array forming regions 5 adjacent to each other, so that the cleavage direction and the infrared detecting element The positional relationship with the arrangement direction should be considered so that the cleavage line 4 does not divide the infrared detecting elements only in one infrared detecting element array forming area 5 regardless of the other adjacent infrared detecting element array forming areas 5. Since it is good, it is not necessary to determine the positional relationship between the cleavage direction and the array direction of the infrared detection elements with extremely high accuracy, and the manufacturing becomes easy.
【００３０】なお、上記の第１及び第２の実施例におい
ては、１０μｍ帯の赤外線を検出するために赤外線検出
素子をＨｇ0.8 Ｃｄ0.2 Ｔｅ結晶で構成しているが、検
出対象の赤外線の波長に応じてその混晶比を任意に変化
させても良いものである。また、上記の第１及び第２の
実施例においては、劈開を発生させる熱処理として、室
温−液体Ｎ2 温度−室温の熱サイクルを１サイクルの周
期を５分として５サイクル行なっているが、この１サイ
クルの周期及び回数はこれらの数値に限られるものでは
なく、且つ、上下の温度も室温と液体Ｎ2 温度に限られ
るものではない。In the above first and second embodiments, the infrared detecting element is composed of Hg 0.8 Cd 0.2 Te crystal for detecting infrared rays in the 10 μm band. The mixed crystal ratio may be arbitrarily changed according to the above. In the first and second embodiments described above, as a heat treatment for generating the cleavage, room temperature - Liquid N 2 temperature - but performed 5 cycles of thermal cycling at room temperature, the cycle of one cycle as 5 minutes, the The cycle and the number of times of one cycle are not limited to these numerical values, and the upper and lower temperatures are not limited to the room temperature and the liquid N 2 temperature.
【００３１】また、上記の第１及び第２の実施例におい
ては、信号処理回路基板として単結晶シリコンを用いて
いるが、より高速処理をするために単結晶ＧａＡｓ等の
単結晶化合物半導体を用いても良いものであり、その場
合には、Ｈｇ0.8 Ｃｄ0.2 Ｔｅ層の成長基板としてもＧ
ａＡｓ基板を用いて、信号処理回路基板と成長基板との
熱膨張係数を合わせる必要がある。In the first and second embodiments described above, single crystal silicon is used as the signal processing circuit board, but a single crystal compound semiconductor such as single crystal GaAs is used for higher speed processing. In this case, G may be used as a growth substrate for the Hg 0.8 Cd 0.2 Te layer.
It is necessary to match the coefficient of thermal expansion between the signal processing circuit substrate and the growth substrate using the aAs substrate.
【００３２】[0032]
【発明の効果】本発明によれば、シリコン等の単結晶半
導体基板の上に成長させたＨｇＣｄＴｅ等の化合物半導
体エピタキシャル層を用いた赤外線検出装置において、
チップサイズを大きくして画素数の多い高解像度の赤外
線検出装置を構成する場合に、ＨｇＣｄＴｅ等の化合物
半導体エピタキシャル層にのみ劈開線を形成して複数の
領域に分割することにより、熱膨張係数の差に起因する
熱歪みの影響を低減させて、Ｉｎバンプの剥がれ及びＨ
ｇＣｄＴｅ等の化合物半導体エピタキシャル層の割れ・
剥離をなくし、高解像度の赤外線検出装置の信頼性を高
めることができる。According to the present invention, in an infrared detecting device using a compound semiconductor epitaxial layer such as HgCdTe grown on a single crystal semiconductor substrate such as silicon,
When a high-resolution infrared detection device having a large chip size and a large number of pixels is configured, a cleavage line is formed only in a compound semiconductor epitaxial layer such as HgCdTe to divide it into a plurality of regions, thereby increasing the thermal expansion coefficient. In bump peeling and H
Cracking of compound semiconductor epitaxial layers such as gCdTe
It is possible to eliminate peeling and improve the reliability of the high-resolution infrared detection device.
【図１】本発明の原理的構成の説明図である。FIG. 1 is an explanatory diagram of a principle configuration of the present invention.
【図２】本発明の第２の実施例の原理的構成の説明図で
ある。FIG. 2 is an explanatory diagram of a principle configuration of a second embodiment of the present invention.
【図３】本発明の第１の実施例の説明図である。FIG. 3 is an explanatory diagram of the first embodiment of the present invention.
【図４】本発明の第２の実施例の説明図である。FIG. 4 is an explanatory diagram of a second embodiment of the present invention.
【図５】従来の赤外線検出装置の断面図である。FIG. 5 is a sectional view of a conventional infrared detection device.
【図６】従来の他の赤外線検出装置の断面図である。FIG. 6 is a cross-sectional view of another conventional infrared detection device.
１ シリコン半導体基板（単結晶半導体基板） ２ 赤外線検出素子形成用化合物半導体層 ３ キズ ４ 劈開線 ５ 赤外線検出素子アレイ形成領域 ６ 分離溝 ７ ＨｇＣｄＴｅ層 ８ 赤外線検出素子 ９ シリコン信号処理回路基板 １０ バンプ １１ ＣｄＴｅ基板 １２ ＨｇＣｄＴｅ赤外線検出素子 1 Silicon Semiconductor Substrate (Single Crystal Semiconductor Substrate) 2 Compound Semiconductor Layer for Forming Infrared Detecting Element 3 Scratch 4 Cleavage Line 5 Infrared Detecting Element Array Forming Area 6 Separation Groove 7 HgCdTe Layer 8 Infrared Detecting Element 9 Silicon Signal Processing Circuit Board 10 Bump 11 CdTe substrate 12 HgCdTe infrared detector
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/301 31/0264 Ｈ０１Ｌ 31/08 Ｎ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/301 31/0264 H01L 31/08 N
Claims (7)
素子形成用化合物半導体エピタキシャル層に複数の赤外
線検出素子からなる赤外線検出素子アレイを少なくとも
一つ設けると共に、前記赤外線検出素子形成用化合物半
導体エピタキシャル層にのみ劈開線を設けて複数の領域
に分割したことを特徴とする赤外線検出装置。1. An infrared detecting element array comprising a plurality of infrared detecting elements is provided on an infrared detecting element forming compound semiconductor epitaxial layer provided on a single crystal semiconductor substrate, and the infrared detecting element forming compound semiconductor epitaxial layer is provided. An infrared detection device characterized in that a cleavage line is provided only on a layer and divided into a plurality of regions.
素子形成用化合物半導体エピタキシャル層とからなる赤
外線検出部を、信号処理回路を設けた信号処理回路基板
と導電体バンプを用いて貼り合わせたことを特徴とする
請求項１記載の赤外線検出装置。2. An infrared detecting section comprising the single crystal semiconductor substrate and the compound semiconductor epitaxial layer for forming an infrared detecting element is bonded to a signal processing circuit board provided with a signal processing circuit by using a conductor bump. The infrared detection device according to claim 1, wherein:
基板であり、また、上記赤外線検出素子形成用化合物半
導体エピタキシャル層がＨｇＣｄＴｅ層であることを特
徴とする請求項１または２記載の赤外線検出装置。3. The infrared detecting device according to claim 1, wherein the single crystal semiconductor substrate is a silicon semiconductor substrate, and the compound semiconductor epitaxial layer for forming an infrared detecting element is a HgCdTe layer.
成用化合物半導体層をエピタキシャル層成長させたの
ち、前記赤外線検出素子形成用化合物半導体層に不純物
を導入して複数の赤外線検出素子からなる赤外線検出素
子アレイ形成領域を少なくとも一つ形成し、次いで、前
記赤外線検出素子形成用化合物半導体層のみを劈開して
前記赤外線検出素子アレイ形成領域を複数の領域に分割
したことを特徴とする赤外線検出装置の製造方法。4. An infrared ray comprising a plurality of infrared ray detecting elements by epitaxially growing an infrared ray detecting element forming compound semiconductor layer on a single crystal semiconductor substrate, and introducing impurities into the infrared ray detecting element forming compound semiconductor layer. An infrared detecting device characterized in that at least one detecting element array forming region is formed, and then only the infrared detecting element forming compound semiconductor layer is cleaved to divide the infrared detecting element array forming region into a plurality of regions. Manufacturing method.
外線検出素子形成用化合物半導体層に設けた複数の赤外
線検出素子アレイ形成領域を分離溝によって互いに分離
し、前記赤外線検出素子アレイ形成領域ごとに劈開する
ことを特徴とする請求項４記載の赤外線検出装置の製造
方法。5. A plurality of infrared detection element array formation regions provided in the infrared detection element formation compound semiconductor layer are separated from each other by separation grooves prior to the cleavage formation step, and each infrared detection element array formation region is separated. The method for manufacturing an infrared detection device according to claim 4, wherein the cleavage is performed.
と上記赤外線検出素子形成用化合物半導体層とからなる
赤外線検出部の赤外線検出素子アレイ形成領域の周辺を
構成する一辺に少なくとも一つのキズを形成し、熱処理
を加えることにより前記キズを起点とした劈開を行うこ
とを特徴とする請求項４または５記載の赤外線検出装置
の製造方法。6. The cleaving step has at least one flaw on one side which constitutes a periphery of an infrared detecting element array forming region of an infrared detecting section composed of the single crystal semiconductor substrate and the infrared detecting element forming compound semiconductor layer. The method for manufacturing an infrared detection device according to claim 4 or 5, wherein cleavage is performed by forming and performing heat treatment as a starting point.
検出部に周期的な熱サイクルを加える工程であることを
特徴とする請求項４乃至６のいずれか１項に記載の赤外
線検出装置の製造方法。7. The infrared detecting apparatus according to claim 4, wherein the step of applying the heat treatment is a step of applying a periodic thermal cycle to the infrared detecting section. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267932A JPH08130297A (en) | 1994-11-01 | 1994-11-01 | Infrared detector and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6267932A JPH08130297A (en) | 1994-11-01 | 1994-11-01 | Infrared detector and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08130297A true JPH08130297A (en) | 1996-05-21 |
Family
ID=17451614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6267932A Withdrawn JPH08130297A (en) | 1994-11-01 | 1994-11-01 | Infrared detector and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08130297A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729020A (en) * | 1995-08-25 | 1998-03-17 | Kabushiki Kaisha Toshiba | Hybrid type infrared detector |
| KR20030048543A (en) * | 2001-12-12 | 2003-06-25 | 주식회사 케이이씨 | upper chip fabricating method in infrared detector and the chip structure |
-
1994
- 1994-11-01 JP JP6267932A patent/JPH08130297A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729020A (en) * | 1995-08-25 | 1998-03-17 | Kabushiki Kaisha Toshiba | Hybrid type infrared detector |
| KR20030048543A (en) * | 2001-12-12 | 2003-06-25 | 주식회사 케이이씨 | upper chip fabricating method in infrared detector and the chip structure |
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|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020115 |