JPH0813028B2 - Data communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention is used for a data communication device having a dual configuration of a working and a standby. In particular, it relates to synchronization between a working transmitter and a spare transmitter. INDUSTRIAL APPLICABILITY The present invention is suitable for use in a base station transmitter of a mobile radio communication device.

〔Overview〕

The present invention relates to a data communication device having two transmitters, an active transmitter and a spare transmitter, and these two transmitters are connected by a synchronous pulse common line, and the active transmitter transmits a synchronous signal to the synchronous pulse common line. However, by synchronizing both of them with each other, the operation of the active transmitter and the backup transmitter is always synchronized.

[Conventional technology]

In a data communication device equipped with an active transmission device and a backup transmission device, the synchronization of the backup transmission device is always synchronized so that the output data is not out of synchronization when the active and standby data are switched. Must match.

In the conventional data communication device, a host device is provided separately from the active transmitter and the spare transmitter, and the output timings of the two transmitters are synchronized by this host device.

[Problems to be solved by the invention]

However, the conventional synchronization method is not economical because not only the host device is required, but also each transmitter requires a synchronization circuit with the host device. In addition, there is a high risk that both the working transmitter and the spare transmitter will be obstructed when a failure occurs in the above device.

The present invention solves the above problems, and provides a data communication device which has a simple and inexpensive circuit configuration and which can synchronize the synchronization of the working and standby transmitting devices without requiring a host device. With the goal.

[Means for solving problems]

The data transmission apparatus of the present invention includes two transmitters, a means for setting one of these two transmitters as an active side and a second for the spare side, and two transmitters respectively synchronizing data output timings. In a data communication device provided with a sync pulse common line for supplying a common sync pulse for, a sync pulse of the transmitter set to the sync pulse common line from the working set side of the two transmitters. Is provided.

[Work]

The data communication apparatus of the present invention connects two transmitters with a sync pulse common line, and operates both transmitters in synchronization with the sync pulse on this common line. Therefore, the two transmitters are in sync. The sync pulse is supplied from the current transmitter.

The spare transmitter internally creates output data and generates sync pulses, but does not output them until switched to the current one. When the spare transmitter is switched to the active mode, it is possible to output the data and generate the sync pulse while maintaining the synchronization up to that point.

〔Example〕

FIG. 1 is a block diagram of a data communication device according to an embodiment of the present invention. Here, the configuration of the second transmitting device 2 is the same as that of the first transmitting device 1, and thus is omitted.

The selection signal from the outside is supplied to the first transmission device 1 via the state line 11 and is supplied to the second transmission device 2 via the state line 11 and the inverter 3. Clock oscillator circuit 4
Is provided in one of the transmitters and supplies the clock signal CLK1 to the transmitters 1 and 2 via the clock line l2.

The transmitter 1 includes a frequency divider circuit 11, a control unit 12, a parallel serial shift register 13, a synchronization pulse generation circuit 14, and NAND gate circuits 15 and 16. The transmitting device 2 is also the same.

The clock line 12 is connected to the frequency dividing circuit 11, the control unit 12, and the parallel / serial shift register 13. The state line l1 is connected directly to the first inputs of the NAND gate circuits 15 and 16 respectively in the case of the first transmitter 1 and via the inverter 3 in the case of the second transmitter 2. .

The frequency dividing circuit 11 is connected to the control unit 12 and the synchronization pulse generating circuit 14. The control unit 12 is connected to the synchronization pulse generation circuit 14 and the parallel / serial shift register 13. The synchronization pulse generation circuit 14 is connected to the second input of the NAND gate circuit 15.
The output of the NAND gate circuit 15 is connected to the sync pulse common line 13 and the control unit 12. The output of the parallel-series shift register 13 is connected to the second input of the NAND gate circuit 16. NAND
The output of the gate circuit 16 is connected to the output data line l4.

The output of the NAND gate circuit 15 of the two transmitters 1 and 2 is
They are connected to each other via a sync pulse common line l3. Also,
The outputs of the NAND gate circuit 16 are connected to each other via the output data l4.

A voltage of + 5V is supplied to the sync pulse common line 13 via the pull-up resistor 5. A voltage of + 5V is supplied to the output data line 14 via the pull-up resistor 6.

When the selection signal of the status line l1 is "1", the first transmission device 1 is in use, and when the selection signal is "0", the second transmission device 2 is in use. In the following, the first transmitter 1
Will be described as an example.

The clock oscillating circuit 4 supplies a common clock signal CLK1 to both the active and standby transmitters 1 and 2. The frequency dividing circuit 11 outputs a clock signal CLK2 obtained by dividing the clock signal CLK1 by 8, and generates an interrupt to the control unit 12 at the falling edge of the clock signal CLK2. This clock signal CL
In one cycle of K2, the transmitter 1 outputs 8-bit (1 byte) data.

When the control unit 12 receives an interrupt from the frequency dividing circuit 11,
It is determined whether or not it is a timing to generate a synchronization pulse, and when it is determined that timing, the synchronization pulse of the synchronization pulse generation circuit 14 is validated. When the sync pulse common line l3 is valid, the sync information is stored in the parallel / serial shift register 13. Therefore, the sync pulse common line
The synchronization information is transmitted as output data in the cycle of the clock signal CLK2 after l3 becomes valid.

The spare transmitter 2 also performs the same operation, and when the sync pulse common line 13 is valid, it stores data in the parallel-serial shift register at the same timing as the transmitter 1.

The synchronization pulse generation circuit 14 generates a synchronization pulse at the falling edge of the clock signal CLK2 under the control of the control unit 12. The parallel / serial shift register 13 converts the parallel data accumulated in 1-byte units from the control unit 12 into serial data.

The NAND gate circuit 15 is an open collector circuit, and outputs the output of the sync pulse generation circuit 14 to the sync pulse common line 13 when the transmitter 1 is in use. The spare transmitter 2 similarly generates a sync pulse, but the sync pulse common line
The output to l3 is prohibited by the NAND gate circuit. Therefore, the sync pulse of the active transmitter 1 is valid (in the inverted state) on the sync pulse common line l3.

The NAND gate circuit 16 is an open collector circuit and outputs the output of the parallel / serial shift register 13 to the output data line l4 when the transmitter 1 is in use. Similarly, in the spare transmitter 2, the parallel / serial shift register 13 outputs data, but the output to the output data line 14 is prohibited by the NAND gate circuit.

 FIG. 2 shows a time chart of this embodiment.

The clock signal CLK1 is common to the two transmitters 1 and 2, and its frequency is 2.4 kHz in this example. This clock signal CLK1 is divided by 8 to generate a 300 Hz clock signal CLK.
2 generates a byte interrupt to the control unit 12 at the fall.

The control unit 12 sets the byte interrupt signal to "1" and requests the central processing unit in the control unit 12 for an interrupt. The central processing unit receives an interrupt, and outputs an interrupt acknowledge signal to reset the byte interrupt signal to "0", stores the data D ₀ to D ₇ in parallel serial shift register 13. Further, the central processing unit determines the output timing of the sync pulse from the number of interrupts, and outputs the sync set signal to the sync pulse generation circuit 14.

The sync pulse generation circuit 14 outputs a sync pulse at the next falling edge of the clock signal CLK2 and enables the sync pulse common line 13 when the transmitter 1 is in use. The spare transmitter 2 cannot activate the sync pulse common line l3.

The central processing unit of the control unit 12 determines whether or not the synchronization pulse common line 13 is valid each time an interrupt is accepted. When this is valid, the synchronization information is stored in the parallel / serial shift register 13. Similarly, the spare transmitter also monitors the sync pulse common line 13 and stores the sync information in the parallel / serial shift register 13 when it is valid.

The 1-byte data accumulated in the active parallel-serial shift register 13 is output to the output data line 14 in the next cycle of the clock signal CLK2. Data on the spare side is not output, but it is always synchronized with the working side. Therefore, even when switching is performed between the active transmission device and the backup transmission device, the synchronization of the output data coincides with each other, and the switching failure does not occur.

〔The invention's effect〕

As described above, in the data communication device of the present invention,
The spare transmitter does not output data and sync pulse to the outside, but internally it always operates in synchronization with the active transmitter. Therefore, the synchronization does not deviate at the time of switching between the active and standby. In addition, even if the backup transmitter is removed and reattached, or if the backup transmitter is out of synchronization due to a momentary interruption, etc., it should be synchronized with the active side when the sync pulse on the sync pulse common line becomes valid. You can

Since the data communication device of the present invention does not require a host device, it is possible to match the synchronization of the two transmission devices with a simple circuit configuration, which has the effect of improving the reliability of data transmission.

[Brief description of drawings]

FIG. 1 is a block diagram of a data communication device according to an embodiment of the present invention. FIG. 2 is an operation time chart. 1, 2 ... Transmitting device, 3 ... Inverter, 4 ... Clock oscillation circuit, 5, 6 ... Pull-up resistor, 11 ... Dividing circuit, 12 ... Control unit, 13 ... Parallel series shift register, 14
...... Synchronous pulse generation circuit, 15, 16 …… NAND gate circuit,
l1 ... Status line, l2 ... Clock line, l3 ... Sync pulse common line, l4 ... Output data line.

Front page continuation (72) Inventor Kenji Ito 1-2356 Takeshi, Yokosuka City, Kanagawa Pref. Naoyuki Yagami (56) ) JP-A-55-102952 (JP, A)

Claims (1)

[Claims] 1. Two transmitters, a means for setting one of these two transmitters as an active side and the other as a spare, and two transmitters for synchronizing the output timing of data respectively. In a data communication device having a sync pulse common line for supplying a common sync pulse, the sync pulse of the transmitter set to the sync pulse common line from the working set side of the two transmitters. A data communication device comprising means for supplying the data.