JPH0812908B2 - Light emitting thyristor element and manufacturing method thereof - Google Patents
Light emitting thyristor element and manufacturing method thereofInfo
- Publication number
- JPH0812908B2 JPH0812908B2 JP1058489A JP1058489A JPH0812908B2 JP H0812908 B2 JPH0812908 B2 JP H0812908B2 JP 1058489 A JP1058489 A JP 1058489A JP 1058489 A JP1058489 A JP 1058489A JP H0812908 B2 JPH0812908 B2 JP H0812908B2
- Authority
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- Japan
- Prior art keywords
- layer
- light
- type semiconductor
- gate layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
- H01S5/0262—Photo-diodes, e.g. transceiver devices, bidirectional devices
- H01S5/0264—Photo-diodes, e.g. transceiver devices, bidirectional devices for monitoring the laser-output
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
- H01S5/2231—Buried stripe structure with inner confining structure only between the active layer and the upper electrode
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光通信や光情報処理に用いられる発光サイリ
スタ素子に関するものである。TECHNICAL FIELD The present invention relates to a light emitting thyristor element used for optical communication and optical information processing.
光通信や光情報処理においては、発光素子は重要なキ
ーデバイスであるが、更に光の入力で制御できる光機能
発光素子の実現が期待されている。このような光機能発
光素子に要求される特性としては、光入力信号により光
出力のオン・オフが可能であること、その際できるだけ
小さな光入力高出力の光出力が得られること、高速に駆
動できることなどである。このような要求に対し、光入
力の有無により光出力のオン・オフができる素子を実現
する試みは、基本構造がpnpn形あるいはnpnp形の発光サ
イリスタ素子を用いてなされている。そのような素子は
例えば、ジャーナル・アプライド・フィジックス1986年
59巻596頁(G.W.Taylor et al.,J.Appl.Phys.59,596(1
986))に記載されている。この素子は、2つのn層の
間に、空乏化しているためチャージシート層と名付けら
れた薄い層を有するが、電流・電圧特性の振るまいはpn
pn形(又はnpnp形)サイリスタ素子のものと同じであ
る。従ってここではこの素子を発光サイリスタ素子とし
て議論する。また、アプライド・フィジックス・レター
ズ1988年52巻700頁(K.Kasahara et al.,Appl.Phys.Let
t.52,679(1988))に記載されたpnpn形の発光サイリス
タ素子においては、光入力信号により光出力をオン・オ
フできる機能の他に、光信号入力後一定時間に再びその
信号を電気出力ないし光出力の形で読み出すことができ
るダイナミックメモリー機能の検証がなされている。そ
して、これらの素子ユニットを半絶縁性基板の上にマト
リックス状に並べた集積素子も実現されつつある。The light emitting element is an important key device in optical communication and optical information processing, but it is expected to realize an optical functional light emitting element that can be controlled by light input. The characteristics required for such an optical functional light emitting device are that the optical output can be turned on and off by an optical input signal, that the smallest possible optical input and high output optical output can be obtained, and high speed driving is possible. What you can do. In response to such a demand, an attempt to realize an element capable of turning on / off the optical output depending on the presence / absence of the optical input is made by using a light emitting thyristor element having a basic structure of pnpn type or npnp type. Such devices are described, for example, in Journal Applied Physics, 1986.
Volume 59 596 (GWTaylor et al., J.Appl.Phys.59,596 (1
986)). This device has a thin layer called the charge sheet layer because it is depleted between two n layers, but the behavior of the current-voltage characteristics is pn.
It is the same as that of a pn type (or npnp type) thyristor element. Therefore, this element will be discussed here as a light emitting thyristor element. Also, Applied Physics Letters, 1988, 52, 700 pages (K.Kasahara et al., Appl.Phys.Let
t.52,679 (1988)), the pnpn-type light-emitting thyristor element has the function of turning on / off the optical output by an optical input signal, and the electrical output of the signal again at a certain time after the optical signal is input. The dynamic memory function that can be read out in the form of optical output has been verified. An integrated element in which these element units are arranged in a matrix on a semi-insulating substrate is also being realized.
第2図は、このような従来素子ユニットの模式断面図
である。第2図において、10はカソード電極、11は半絶
縁性基板、12はn形半導体クラッド層、13はp形半導体
ゲート層、14はn形半導体ゲート層、15はp形半導体ク
ラッド層、16はアノード電極である。これらの素子ユニ
ットを多数集積する際には、発光面積減少に見合う検出
感度の増加と、素子全体の消費パワーの低減が必要であ
る。すなわち、ユニットあたりの検出感度の改善とユニ
ットあたりの消費パワーの低減が必要である。しかし、
従来の素子構造ではこれらの改善が容易でない問題点が
あった。FIG. 2 is a schematic cross-sectional view of such a conventional element unit. In FIG. 2, 10 is a cathode electrode, 11 is a semi-insulating substrate, 12 is an n-type semiconductor clad layer, 13 is a p-type semiconductor gate layer, 14 is an n-type semiconductor gate layer, 15 is a p-type semiconductor clad layer, 16 Is an anode electrode. When a large number of these element units are integrated, it is necessary to increase the detection sensitivity commensurate with the reduction of the light emitting area and reduce the power consumption of the entire element. That is, it is necessary to improve the detection sensitivity per unit and reduce the power consumption per unit. But,
The conventional element structure has a problem that these improvements are not easy.
本発明は、上記の従来の問題点を改善し、入力信号を
効率よく検出し、かつ必要な光出力を保ちながら消費パ
ワーの少ない発光サイリスタ素子を提供することであ
る。An object of the present invention is to provide a light-emitting thyristor element that solves the above conventional problems, efficiently detects an input signal, and consumes less power while maintaining a required optical output.
本発明の発光サイリスタ素子は、n形半導体ゲート層
とp形半導体ゲート層の2層からなる光吸収・発光層
を、前記光吸収・発光層より禁制帯幅の大きなp形半導
体クラッド層とn形半導体クラッド層とで挟み、導体形
がpnpnまたはnpnpのうちのいずれかの順で半導体基板上
に積層した発光サイリスタ素子において、前記光吸収・
発光層の少なくとも一部がメサ状構造を備え、メサの両
脇に前記光吸収・発光層よりも禁制帯幅の大きな半導体
電流阻止層を設けた構成からなる。The light-emitting thyristor element of the present invention comprises a light-absorbing / light-emitting layer composed of two layers, an n-type semiconductor gate layer and a p-type semiconductor gate layer, and a p-type semiconductor clad layer having a band gap larger than that of the light absorbing / light-emitting layer and an n-type semiconductor clad layer. In the light-emitting thyristor element laminated on the semiconductor substrate in the order of either pnpn or npnp, sandwiched between the
At least a part of the light emitting layer has a mesa structure, and a semiconductor current blocking layer having a band gap larger than that of the light absorbing / light emitting layer is provided on both sides of the mesa.
また、もう一つの発明である発光サイリスタの製造方
法は、半導体基板上に第1導電形半導体クラッド層、第
2導電形半導体ゲート層、第1導電形半導体ゲート層を
順次積層し、光吸収・発光層である前記第1導電形半導
体ゲート層をメサ状に加工し、その上に、前記光吸収・
発光層より禁制帯幅の大きな半導体電流阻止層を形成す
る第1の工程と、前記第1導電形半導体ゲート層のメサ
上の前記半導体電流阻止層を反応性イオンビームエッチ
ングで除去した後、第2導電形半導体クラッド層でおお
う第2の工程とを少なくとも持つことが特徴である。In addition, another method of manufacturing a light-emitting thyristor according to the invention is a semiconductor substrate in which a first conductivity type semiconductor clad layer, a second conductivity type semiconductor gate layer, and a first conductivity type semiconductor gate layer are sequentially stacked to absorb light. The first conductivity type semiconductor gate layer, which is a light emitting layer, is processed into a mesa shape, and the light absorption /
A first step of forming a semiconductor current blocking layer having a band gap larger than that of the light emitting layer; and removing the semiconductor current blocking layer on the mesa of the first conductivity type semiconductor gate layer by reactive ion beam etching, It is characterized by having at least a second step of covering with a two-conductivity type semiconductor clad layer.
本発明の作用原理について、図面を参照しながら以下
に説明する。第1図は本発明の素子断面図である。発光
サイリスタ素子においては、素子がオフ状態のときn形
ゲート層中のキャリア密度は低い状態にある。このとき
光を入力してやるとn形ゲート層中に電子・正孔キャリ
アが発生し、npnヘテロバイポーラ中の電流利得発生と
同じ機構で、効率よく大きな素子電流を流すことができ
る。このとき、n形ゲート層の体積を小さくし、その小
さな部分に入力光のパワーを集中してやれば、入力信号
感度は上昇する。本発明は、このために、n形ゲート層
中の体積をメサ部17に限定し、素子を流れる電流も、n
形半導体電流阻止層18をメサ脇に設けることで、メサ部
17に狭搾するようにした。またメサ部の凸部をおおうよ
うにp形クラッド層15を成長することで、入力光をメサ
部17へ集光する構造を設けた。すなわち、本発明の構成
の作用は、従来構造に比べ入力信号感度が上昇するこ
と、一定光出力到達の電流値が低下すること、更に素子
ユニットサイズを十分小さくできることから、素子容量
も低減でき素子の高速化が可能であること等である。The operation principle of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an element of the present invention. In the light emitting thyristor element, the carrier density in the n-type gate layer is low when the element is in the off state. At this time, when light is input, electron / hole carriers are generated in the n-type gate layer, and a large device current can be efficiently supplied by the same mechanism as the current gain generation in the npn hetero bipolar. At this time, if the volume of the n-type gate layer is reduced and the power of the input light is concentrated on the small portion, the input signal sensitivity is increased. For this reason, the present invention limits the volume in the n-type gate layer to the mesa portion 17, and the current flowing through the element is also n.
By providing the semiconductor current blocking layer 18 beside the mesa,
I tried to squeeze it to 17. Further, a structure was provided in which the p-type clad layer 15 was grown so as to cover the convex portion of the mesa portion so that the input light was condensed to the mesa portion 17. That is, the operation of the configuration of the present invention is that the input signal sensitivity is increased, the current value for reaching a constant optical output is decreased, and the element unit size can be sufficiently reduced compared to the conventional structure, so that the element capacitance can be reduced. It is possible to speed up.
以下、本発明の実施例について更に詳しく説明する。 Hereinafter, examples of the present invention will be described in more detail.
第1図は本発明の一実施例を示す概略素子断面図であ
る。本実施例は、第1図のように先ず半絶縁性GaAs基板
11の上にn形AlGaAsクラッド層12、厚さ50オングストロ
ーム程度のp形GaAsゲート層13、厚さ約1ミクロンのn
形GaAsゲート層14、p形AlGaAsクラッド層15、及び電極
10,16を備えている点は従来と同じであるが、n形ゲー
ト層14の一部がメサ構造17を備えその両脇にn形AlGaAs
電流阻止層18を新たに設けてある点が従来と異なる点で
ある。この構造を設けることにより、素子内を流れる電
流は光吸収・発光層であるn形ゲート層14のメサ部17に
集中して流れるため、少量の電流をメサ部17に注入する
だけで従来より大きな光出力が得られるようになった。
また、第1図のようにメサ部17をおおうp形クラッド層
15の形状を凸状に成長できることから、この凸状p形ク
ラッド層によるレンズ作用により入射光19を光吸収領域
であるn形ゲート層のメサ部17へ集中でき、従来より低
い入力光強度で信号を検出できるようになった。FIG. 1 is a schematic element sectional view showing an embodiment of the present invention. In this embodiment, as shown in FIG. 1, first, a semi-insulating GaAs substrate is used.
N-type AlGaAs clad layer 12, p-type GaAs gate layer 13 having a thickness of about 50 Å, and n having a thickness of about 1 micron.
-Type GaAs gate layer 14, p-type AlGaAs cladding layer 15, and electrodes
10 and 16 are provided in the same manner as the conventional one, but part of the n-type gate layer 14 is provided with a mesa structure 17 and n-type AlGaAs is provided on both sides thereof.
The point that the current blocking layer 18 is newly provided is different from the conventional one. By providing this structure, the current flowing in the element concentrates on the mesa 17 of the n-type gate layer 14 which is a light absorption / light emitting layer, so that a small amount of current is injected into the mesa 17 compared to the conventional case. A large light output can be obtained.
In addition, as shown in FIG. 1, a p-type clad layer covering the mesa 17
Since the shape of 15 can be grown in a convex shape, the incident light 19 can be concentrated on the mesa portion 17 of the n-type gate layer, which is a light absorption region, by the lens action of the convex p-type cladding layer, and the input light intensity is lower than the conventional one. The signal can now be detected.
以下、本実施例素子の製造方法を図面を用い順に説明
する。Hereinafter, a method for manufacturing the device of this example will be described in order with reference to the drawings.
第3図は本発明の製造方法の一実施例を示す概略工程
図である。先ず、第3図(a)のように、半絶縁GaAs基
板11上にn形AlGaAsクラッド層12、p形GaAsゲート層1
3、厚さ1ミクロンのn形GaAsゲート層14を成長した
後、n形GaAsゲート層14を加工し、幅が約2μmのメサ
部17を形成した。次いで第3図(b)のように、n形Al
GaAs電流阻止層18を約0.2μm成長した。Alの組成比は
クラッド層の組成比と同じ0.4である。成長方法は分子
ビームエピタキシー(MBE)法を用いた。この後、メサ
部17の上部の電流阻止層18の除去は、次のような方法で
行った。先ず、フォトレジスト層31を第3図(b)によ
うに電流阻止層上に塗布し、次いで第3図(c)のよう
に反応性イオンビーム32、本実施例では塩素イオンを照
射してリアクティブイオンエッチング8を行なうこと
で、メサ部の上部の電流阻止層の除去を行った。FIG. 3 is a schematic process drawing showing an embodiment of the manufacturing method of the present invention. First, as shown in FIG. 3A, an n-type AlGaAs cladding layer 12 and a p-type GaAs gate layer 1 are formed on a semi-insulating GaAs substrate 11.
3. After growing the n-type GaAs gate layer 14 having a thickness of 1 micron, the n-type GaAs gate layer 14 was processed to form a mesa portion 17 having a width of about 2 μm. Then, as shown in FIG. 3 (b), n-type Al
The GaAs current blocking layer 18 was grown to about 0.2 μm. The Al composition ratio is 0.4, which is the same as the composition ratio of the cladding layer. The growth method was the molecular beam epitaxy (MBE) method. After that, the current blocking layer 18 above the mesa portion 17 was removed by the following method. First, a photoresist layer 31 is applied on the current blocking layer as shown in FIG. 3 (b), and then a reactive ion beam 32, chlorine ions in this embodiment, is applied as shown in FIG. 3 (c). By performing reactive ion etching 8, the current blocking layer above the mesa portion was removed.
最後に、第3図(c)に残るフォトレジスト層31を剥
離した後、p形AlGaAsクラッド層を成長し、第1図のよ
うななめらかな凸状半導体構造を形成した。なお、電極
とのコンタクト層および電極パターンなどは通常の光デ
バイス形成工程に従って形成した。Finally, after removing the photoresist layer 31 remaining in FIG. 3 (c), a p-type AlGaAs cladding layer was grown to form a smooth convex semiconductor structure as shown in FIG. The contact layer with the electrode, the electrode pattern, and the like were formed according to a normal optical device forming process.
上記の工程に従って形成した発光サイリスタ素子は、
光吸収・発光に与るメサ部の体積が従来素子の場合の数
10分の1に減少された。このため、この部分に光が集光
する分だけ光信号感度が改善され、更に光出力及びメモ
リー保持消費パワーを従来に比べ極めて減少させること
が出来た。また、素子の寄生容量の減少により高速駆動
特性のよい素子が得られた。The light emitting thyristor element formed according to the above process,
The volume of the mesa that contributes to light absorption and light emission is the number in the case of conventional elements
It was reduced to 1/10. For this reason, the light signal sensitivity is improved by the amount of light condensed on this portion, and further, the light output and the memory holding power consumption can be significantly reduced as compared with the conventional one. In addition, a device with good high-speed driving characteristics was obtained due to the reduction of the parasitic capacitance of the device.
尚、上記実施例で、光吸収・発光メサ部をおおった構
造の形状は、円筒レンズ状のものを形成したが、凸レン
ズ形状のものであればより高感度化と消費パワーの低減
が可能である。In the above example, the shape of the structure covering the light absorption / emission mesa portion was formed in the shape of a cylindrical lens, but if the shape is a convex lens, higher sensitivity and lower power consumption are possible. is there.
上記実施例では光吸収・発光層が厚膜のLED形の発光
素子について示したが、層中にウェルを設けたレーザ形
の発光素子についても同様に有効である。また、上記実
施例では、MBE法を用いたが、有機金属気相成長(MOCV
D)法などの他の方法を用いても構わない。また、GaAs/
AlGaAls系に限らずInP系の長波長レーザ素子に対しても
本発明は基本的に有効である。In the above embodiments, the LED type light emitting element having a thick light absorption / emission layer is shown, but the same can be applied to a laser type light emitting element having a well in the layer. In addition, although the MBE method was used in the above-mentioned examples, metal organic chemical vapor deposition (MOCV
Other methods such as method D) may be used. Also, GaAs /
The present invention is basically effective not only for AlGaAls-based long-wavelength laser devices, but also for InP-based long-wavelength laser devices.
以上に説明したように、本発明の発光サイリスタ素子
は、従来素子に比べ、入力信号に対する検出感度が高
く、かつ素子の消費電力が少ない特性を備え、光情報処
理素子への応用に適する。As described above, the light emitting thyristor element of the present invention has characteristics of higher detection sensitivity for an input signal and lower power consumption of the element than conventional elements, and is suitable for application to an optical information processing element.
第1図は本発明の一実施例の概略断面図、第2図は従来
の発光サイリスタ素子の概略断面図、第3図は本発明の
発光サイリスタ製造方法の概略工程図である。 10……カソード電極、11……基板、n……n形半導体ク
ラッド層、13……p形半導体ゲート層、14……n形半導
体ゲート層、15……p形クラッド層、16……アノード電
極、17……光吸収発光メサ部、18……電流阻止層、19…
…入射光、31……レジスト層、32……反応性イオンビー
ム。FIG. 1 is a schematic sectional view of an embodiment of the present invention, FIG. 2 is a schematic sectional view of a conventional light emitting thyristor element, and FIG. 3 is a schematic process diagram of a method for manufacturing a light emitting thyristor of the present invention. 10 ... Cathode electrode, 11 ... Substrate, n ... N-type semiconductor cladding layer, 13 ... P-type semiconductor gate layer, 14 ... N-type semiconductor gate layer, 15 ... P-type cladding layer, 16 ... Anode Electrodes, 17 ... Optical absorption and emission mesa, 18 ... Current blocking layer, 19 ...
… Incident light, 31 …… Resist layer, 32 …… Reactive ion beam.
Claims (2)
の2層からなる光吸収・発光層を、前記光吸収・発光層
より禁制帯幅の大きなp形半導体クラッド層とn形半導
体クラッド層とで挟み、導体形がpnpnまたはnpnpのうち
のいずれかの順で半導体基板上に積層した発光サイリス
タ素子において、前記光吸収・発光層の少なくとも一部
がメサ状構造を備え、メサの両脇に前記光吸収・発光層
よりも禁制帯幅の大きな半導体電流阻止層を設けたこと
を特徴とする発光サイリスタ素子。1. A p-type semiconductor clad layer and an n-type semiconductor clad having a light absorption / emission layer composed of two layers, an n-type semiconductor gate layer and a p-type semiconductor gate layer, having a band gap larger than that of the light absorption / emission layer. In a light-emitting thyristor element which is sandwiched between layers and has a conductor type of pnpn or npnp stacked on a semiconductor substrate in that order, at least a part of the light-absorbing / light-emitting layer has a mesa structure, and A light emitting thyristor element characterized in that a semiconductor current blocking layer having a band gap larger than that of the light absorbing / light emitting layer is provided aside.
ド層、第2導電形半導体ゲート層、第1導電形半導体ゲ
ート層を順次積層し、光吸収・発光層である前記第1導
電形半導体ゲート層をメサ状に加工し、その上に、前記
光吸収・発光層より禁制帯幅の大きな半導体電流阻止層
を形成する第1の工程と、前記第1導電形半導体ゲート
層のメサ部の上部の前記半導体電流阻止層を反応性イオ
ンビームエッチングで除去した後、第2導電形半導体ク
ラッド層でおおう第2の工程とを少なくとも備えたこと
を特徴とする発光サイリスタ素子の製造方法。2. A first conductivity type semiconductor cladding layer, a second conductivity type semiconductor gate layer, and a first conductivity type semiconductor gate layer are sequentially stacked on a semiconductor substrate to form a light absorption / light emission layer. A first step of processing the semiconductor gate layer into a mesa shape, and forming a semiconductor current blocking layer having a band gap larger than that of the light absorption / light emission layer on the semiconductor gate layer; and a mesa portion of the first conductivity type semiconductor gate layer A method for manufacturing a light-emitting thyristor element, comprising at least a second step of covering the upper part of the semiconductor current blocking layer by reactive ion beam etching and then covering with a second conductivity type semiconductor clad layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1058489A JPH0812908B2 (en) | 1989-01-18 | 1989-01-18 | Light emitting thyristor element and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1058489A JPH0812908B2 (en) | 1989-01-18 | 1989-01-18 | Light emitting thyristor element and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02189975A JPH02189975A (en) | 1990-07-25 |
JPH0812908B2 true JPH0812908B2 (en) | 1996-02-07 |
Family
ID=11754297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1058489A Expired - Lifetime JPH0812908B2 (en) | 1989-01-18 | 1989-01-18 | Light emitting thyristor element and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0812908B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4140358B2 (en) * | 2002-11-27 | 2008-08-27 | 富士ゼロックス株式会社 | Light emitting thyristor, light emitting thyristor manufacturing method, and light emitting element array chip |
-
1989
- 1989-01-18 JP JP1058489A patent/JPH0812908B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02189975A (en) | 1990-07-25 |
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