JPH08125659A - Optical buffer memory device - Google Patents

Abstract

PURPOSE: To obtain the optical buffer memory device with simple hardware configuration in which cell abort is suppressed sufficiently even in the case of a nonuniform traffic with a bias. CONSTITUTION: Path changeover means 31, 32 switching plural paths and plural delay element groups 41, 42 provided at output sides of the path changeover means 31, 32 and whose delay time differs in an arithmetic series are used for fundamental constituents and the plural fundamental constituents are connected in cascade for plural stages. Furthermore, the system is provided with a line concentration means 50 concentrating optical cell signals via a delay element group at a final stage and sending the result to an output port 14-i and with a control means controlling the changeover state of the path changeover means of each stage depending on an input state of optical cell signals from each of input ports 20-1-20-N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical buffer memory device, for example, an optical ATM (Asyncronous Transfer Mode).
) It is suitable for application to the buffer memory portion of the exchange.

[0002]

2. Description of the Related Art An optical ATM switching system has been proposed in which an optical switching technique is introduced into an ATM switching system which is a kind of packet switching system. Figure 2 shows the proposed optical AT
2 shows the configuration and operating principle of an exchange according to the M exchange method.

In FIG. 2, optical cell signals input from the respective input ports (optical fibers) 10-1, ..., 10-N are given to the corresponding input units 11-1 ,. The input section 11-1, ..., 11-N analyzes the header portion of the input optical cell signal to obtain the output port (output side optical fiber) of each optical cell signal, and the analysis result is used as routing information. It is sent to the control unit 15. The optical switch unit 12 performs N × N ² switching, and the optical switch unit 12 includes the input units 11-
Each of the optical cell signals sent from 1, ..., 11-N is switched to a desired output highway according to a control signal from the control unit 15. The output highways from the optical switch unit 12 are grouped by N (shown by black stars in the figure).
The optical cell signals output to the same set of output highways by switching are the optical buffer memory units (optical buffer memory devices) 13-1 to 13-corresponding to each set.
Input to N. Each optical buffer memory unit 13-1, ...
In 13-N, under the control of the control unit 15, competition control and buffering of optical cell signals between output highways for output to the corresponding optical fibers 14-1, ..., 14-N which are output ports are performed. Then the optical fiber 14-
, ..., 14-N to output optical cell signals.

Reference: "Takuji Maeda, Tetsuya Nishi, Satoshi Kuroyanagi,
"Optical ATM exchange buffer memory configuration method", IEICE Technical Research Report SSE93-145 "Optical buffer memory unit (optical buffering device) 13-i (i is 1 to N) having such an optical processing configuration. ), A configuration as shown on page 3 of the above document has been conventionally proposed, and FIG. 3 shows a detailed configuration of the optical buffer memory section 13-i.

In FIG. 3, the optical buffer memory unit 13-
As described above, i performs optical contention control and buffering of the optical cell signals from the N output highways 20-1 to 20-N related to itself, and then outputs the optical fiber to the optical fiber 14-i that is the output port. A cell signal is output, and the optical cell memory unit 25-j corresponding to each output highway 20-j (j is 1 to N) and all the optical cell memory units 25-1 to 25-N are output. An N: 1 optical coupler 24 that outputs an optical cell signal to an optical fiber 14-i that is an output port.

Each optical cell memory unit 25-j is formed by cascading r 1-cell delay control units, and each 1-cell delay control unit switches each cell under the control of the control unit 15. 1 × 2 optical switch 21-jk (k is 1 to 2)
r), a fiber delay line 22-jk for delaying by one cell signal time interposed in one output transmission path of the 1 × 2 optical switch 21-jk, and an optical cell signal via the fiber delay line 22-jk. Alternatively, it is composed of a 2: 1 optical coupler 23-jk that outputs the optical cell signal directly applied from the 1 × 2 optical switch 21-jk to a common output line.

Therefore, in each of the optical cell memory sections 25-j, r number of 1 × 2 optical switches 2 which are the constituent elements thereof.
0 by controlling the states of 1-j1 to 21-jr
The input optical cell signal can be delayed (stored) by any one of the delay times of ~ r cell times. Therefore, for each optical cell memory unit 25-j for the same output port 14-i, the control unit 15 appropriately controls the delay time for each optical cell signal according to the routing information of the optical cell signal. The optical cell signal can be output to the output port 14-i while maintaining the time order of the optical cell signal and avoiding the competition.

[0008]

However, the optical buffer memory unit (optical buffer memory device) 13 having the above-mentioned configuration is provided.
In -i, since the output highway 20-j and the optical cell memory unit 25-j are connected one-to-one, when there are many optical cell signals input from any output highway, that is, they are biased. In the case of traffic, the cell may be discarded even though the other optical cell memory unit is vacant, and there is a problem that the use efficiency of the optical buffer memory unit 13-i is poor.

Further, in the optical buffer memory unit (optical buffer memory device) 13-i having the above-mentioned configuration, if it is attempted to reduce the cell discard under high load, the 1-cell delay control unit (2
1-jk to 23-jk), it is necessary to increase the number of cascaded stages r, but with this, the number of 1 × 2 optical switches required increases, and the hardware amount of the device increases. For example, when configuring a 4 × 4 optical ATM switch, 16 optical cell memory units 25-j are required for the entire device. In this case, in order to reduce the cell discard rate to 10 ⁻⁸ or less when a load of 80% is applied, the delay time of each optical cell memory unit 25-j requires a delay time of about 40 cells (r is about 40), optical buffer memory unit 1
The number of 1 × 2 optical switches 21-jk required for the entire 3-i is 640, and the amount of hardware becomes very large.

Therefore, there is a demand for an optical buffer memory device capable of sufficiently suppressing cell discard even in the case of uneven traffic, and having a simple hardware configuration.

[0011]

In order to solve such a problem, according to the present invention, optical cell signals appropriately input from N input ports for each time slot are buffered and sent to one output port. An optical buffer memory device for the above is configured as follows.

That is, a route switching means for switching between a plurality of routes and a group of a plurality of delay elements provided at the output side of the route switching means and having different delay times in arithmetic series are basically used. As a constituent element, the basic constituent elements are cascaded in a plurality of stages. Further, a concentrating means for concentrating the optical cell signals via the delay element group at the final stage and sending them to the output port, and a route switching means for each stage according to the input condition of the optical cell signals from each input port. And a control means for controlling the switching state.

[0013]

In the optical buffer memory device of the present invention, the optical cell signal input from any of the input ports reaches the concentrator by being delayed by an arbitrary delay time by passing through the basic constituent elements of each stage. , And the lines are concentrated by this concentrator and sent to the output port. Here, the control means controls the switching state of the route switching means of each stage according to the input state of the optical cell signal from each input port, thereby preventing the optical cell signal from colliding with each other. It can be buffered and output to the output port without reversing the order of.

As described above, the optical buffer memory device of the present invention comprises a plurality of route switching means, a plurality of delay element groups,
Since it is composed of the concentrating means and the control means, a simple structure can be obtained. Further, since the route switching means is provided, even if there is a large amount of traffic from a certain input port, it is possible to reduce the amount of that traffic and prevent the optical cell signal from being discarded.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of an optical buffer memory device according to the present invention will be described in detail below with reference to the drawings. Here, FIG. 1 shows the configuration of the optical buffer memory device of the first embodiment, and the same or corresponding portions as those in FIGS. 2 and 3 described above are designated by the same reference numerals.

The optical buffer memory device of the first embodiment will be described below as being applied to the optical buffer memory unit 13-i of the optical ATM switch shown in FIG.

In FIG. 1, the optical buffer memory section (optical buffer memory device) 13-i of the first embodiment is arranged such that the first stage optical switch 31 and the first stage optical fiber delay line of N × L configuration are arranged from the input side. Group 41, second stage optical switch 3 of L × M configuration
2, the second-stage optical fiber delay line group 42 and the M: 1 optical coupler 50 are sequentially arranged, and the control unit 15 of the optical ATM switch also has an optical buffer memory unit (optical buffer memory device) 13-. It is an element of i.

A set of output highways 20-1 to 20-N relating to the same output port (optical fiber) 14-i from the optical switch section (see reference numeral 12 in FIG. 2) is connected to the first stage optical switch 31. The first-stage optical switch 31
Under the control of the control unit 15, the switching operation is performed,
The optical cell signals from the output highways 20-1 to 20-N are output to one of the optical fiber delay lines 41-1, ..., 41-L of the first stage optical fiber delay line group 41, respectively.

The L optical fiber delay lines 41-1 to 41-L constituting the first stage optical fiber delay line group 41 have different delay times, and each one cell signal time (T). Each optical fiber delay line 41 in different arithmetic progression
Delay times of -1, ..., 41-L are selected. That is, the a-th (a is 1 to L) optical fiber delay line 41-
The delay time of a is selected as (a-1) * T.

It should be noted that the number L of optical fiber delay lines 41-1 to 41-L constituting the first stage optical fiber delay line group 41 is L.
Is the number N of one set of output highways 20-1 to 20-N related to the same output port 14-i from the optical switch unit.
That is all output highways 20-1 and 20-2.
Even if optical cell signals are simultaneously input from 0 to N, the timing can be shifted through the first stage optical fiber delay line group 41, which is preferable.

Optical cell signals via the respective optical fiber delay lines 41-1, ..., 41-L of the first stage optical fiber delay line group 41 are input to the second stage optical switch 32. The second-stage optical switch 32 performs a switching operation under the control of the control unit 15, and each optical fiber delay line 41-1, ..., 41-.
The optical cell signals from L are input to any one of the optical fiber delay lines 42-1, ..., 4 of the second stage optical fiber delay line group 42.
Output to 2-M.

The M optical fiber delay lines 42-1 to 42-M forming the second stage optical fiber delay line group 42 are arranged so that their delay times are different from each other, and one cell signal time (T) (N-1) times as long as (N-1) * T different optical fiber delay lines 42-1 ...
A delay time of M has been selected. That is, b (b is 1
The delay time of the (-M) th optical fiber delay line 42-b is
It is selected as (b-1) * (N-1) * T.

The number M of optical fiber delay lines 42-1 to 42-M forming the second stage optical fiber delay line group 42.
Is arbitrary as long as it is 2 or more, but from the result of the simulation, it is preferable that the number of output highways is N or more. Also, M optical fiber delay lines 42-1
The delay time of 42-M is made different by the time (N-1) * T, because all the one set of output highways 20-1 to 20-N in two time slots which are adjacent to each other. Even if the optical cell signal is input from the optical fiber, the optical fiber delay line is changed to ensure that the optical cell signals of these two time slots arrive at the M: 1 optical coupler 50 at different timings. Because it is time.

The optical cell signals transmitted through the respective optical fiber delay lines 42-1, ..., 42-M of the second stage optical fiber delay line group 42 are given to the M: 1 optical coupler 50. The M: 1 optical coupler 50 collects all the optical cell signals transmitted through the respective optical fiber delay lines 42-1, ..., 42-M of the second stage optical fiber delay line group 42 and outputs them to the output port 14-i. To do.

The control unit 15 of the first embodiment uses the first-stage optical switch 31 according to the routing information of the optical cell signal.
By controlling the state of the second-stage optical switch 32, the delay time for each optical cell signal is appropriately controlled, and while maintaining the time sequence of the optical cell signal to the optical buffer memory unit 13-i, Output port 14 while avoiding competition
Output the optical cell signal to -i.

FIG. 4 is a flowchart showing an example of a control operation for the optical buffer memory unit 13-i (that is, the first-stage optical switch 31 and the second-stage optical switch 32) executed by the control unit 15 for each time slot. Is. In addition,
In the following description, the first-stage delay line candidate parameter y corresponds to the y-th optical fiber delay line 41-y of the first-stage optical fiber delay line group 41, and is the second-stage delay line candidate. The parameter z corresponds to the z-th optical fiber delay line 42-z of the first-stage optical fiber delay line group 42. These parameters y and z are both 1 when the optical ATM switch is activated.

When the time slot from the output highways 20-1 to 20-N becomes a new time slot, the control unit 15 starts the processing shown in FIG. 4, and first, from the output highways 20-1 to 20-N. Buffer memory unit 13-i
The number x of optical cell signals input to the optical buffer memory unit 13-i is checked to determine whether or not there is at least one optical cell signal input to the optical buffer memory unit 13-i in this time slot (step 1
00, 101).

When there is no optical cell signal input in the current time slot, the first stage delay line candidate parameter y is decremented by 1 and the first stage delay line candidate parameter y is decremented.
Is not 0 (steps 102, 10)
3). If the first stage delay line candidate parameter y is not 0,
A series of processing for this time slot is ended. On the other hand, if the first-stage delay line candidate parameter y is 0, it is determined whether or not the second-stage delay line candidate parameter z is 1, and if the second-stage delay line candidate parameter z is 1, the first When the stage delay line candidate parameter y is set to 1 and a series of processing for the current time slot is ended, and the second stage delay line candidate parameter z is 2 or more, the first stage delay line candidate parameter y can be taken. The maximum value L and the second
The stage delay line candidate parameter z is decremented by 1 and the series of processing for the current time slot is ended (steps 104 to 106). Such an operation corresponds to shortening the delay time for the next optical cell signal by one cell signal time from the largest delay time up to now.

When there is one or more optical cell signals input to the optical buffer memory unit 13-i in the current time slot, the maximum value L of the first stage delay line candidate parameter y can be set to the value at the present time. A value S obtained by subtracting y and adding 1 is obtained, and it is determined whether or not the value S is smaller than the number x of input cells (steps 107 and 108). The value S is the optical fiber delay line 42-defined by the second stage delay line candidate parameter z for all the optical cell signals input in this time slot.
It represents a margin of whether or not it can be sent to z.

When the number x of input cells is larger than the value S,
While confirming that the decision processing for all the optical cell signals has not been completed (step 113), steps 109 to 11 described later for each of the input optical cell signals of this time will be described.
First stage optical switch 31 and second stage optical switch 3
State 2 determination processing is performed.

It is determined whether or not it is the determination process of the first optical cell signal input in the current time slot (step 1).
09). In the case of the determination process of the first optical cell signal, the first stage delay line candidate parameter y is set to 1, the second stage delay line candidate parameter z is incremented by 1, and the first stage optical switch 31 is , The switching state is determined so as to connect the output highway related to the optical cell signal and the y-th optical fiber delay line 41-y. For the second-stage optical switch 32, the y-th optical fiber delay line 41-y. And the z-th optical fiber delay line 42-z are connected to determine the switching state (steps 110 and 112).
In the case of the determination processing of each optical cell signal after the first,
The stage delay line candidate parameter y is incremented by 1
For the stage optical switch 31, the switching state is determined so as to connect the output highway related to the optical cell signal and the y-th optical fiber delay line 41-y, and for the second stage optical switch 32, the y-th optical switch. Fiber delay line 41-y
And the z-th optical fiber delay line 42-z are connected to determine the switching state (steps 111 and 11).
2).

When the number x of input cells is equal to or less than the above-mentioned value S, one cell is input for this input optical cell signal while confirming that the decision processing for all optical cell signals is not completed (step 119). Step 114 to be described later
The state determination processing of the first-stage optical switch 31 and the second-stage optical switch 32 which is 118 is performed.

It is determined whether or not it is the determination process for the first optical cell signal input in the current time slot (step 1
14). In the case of the determination process of the first optical cell signal, the first-stage optical switch 31 is switched so as to connect the output highway related to the optical cell signal and the y-th optical fiber delay line 41-y. For the second stage optical switch 32, the y-th optical fiber delay line 41-
The switching state is determined so as to connect the y-th and the z-th optical fiber delay line 42-z (step 118). In the case of the determination processing of the second and subsequent optical cell signals, the first-stage delay line candidate parameter y is incremented by 1 and it is confirmed that the parameter y does not exceed its maximum value L, and the first Regarding the stage optical switch 31, the output highway relating to the optical cell signal and the y-th optical fiber delay line 41-
The switching state is determined so as to connect with y, and for the second stage optical switch 32, the y-th optical fiber delay line 4
The switching state is determined so as to connect the 1-y and the z-th optical fiber delay line 42-z (steps 115, 1).
16, 118). The first-stage delay line candidate parameter y
Is incremented by 1 and exceeds the maximum value L that can be taken, the first-stage delay line candidate parameter y is set to 2, and the second-stage delay line candidate parameter z is incremented by 1. As for 31, the output highway related to the optical cell signal and the y-th optical fiber delay line 4
The switching state is determined so as to connect 1-y and the second
The switching state of the stage optical switch 32 is determined so as to connect the y-th optical fiber delay line 41-y and the z-th optical fiber delay line 42-z (step 11).
0, 112).

The controller 15 controls the first-stage optical switch 3
For No. 1, the switching state is changed at the time slot of the determined timing, and for the second-stage optical switch 32, the optical cell signal related to the determination is changed to the second-stage optical switch 32.
The switching state is controlled by the time slot of the timing input to.

The optical buffering unit 1 of the first embodiment will be described below.
The buffering operation in 3-i will be specifically described with reference to FIG. FIG. 5 shows a case where N, L, and M are all 4, and the first stage delay line candidate parameter y and the second stage delay line candidate parameter z in the state before the time slot TS1.
Are both 1.

In the time slot TS1, all the output highways 20-1 to 20-4 from the optical switch section 12 to the optical buffer memory section 13-i are supplied with the optical cell signals A to.
Suppose D is output.

Since the number of input cells x is 4 and equal to the value S (negative result in step 101, negative result in step 108), the control unit 15 receives the first optical signal to be processed in the current time slot TS1. For the cell signal A, the first-stage switch 31 is switched so as to connect the output highway 20-1 related to the optical cell signal and the 1 (= y) th optical fiber delay line 41-1. For the second stage optical switch 32, the first optical fiber delay line 41-1 and the 1 (= z) th optical fiber delay line 4 are determined.
The switching state is determined so as to connect with 2-1.

With respect to the second optical cell signal B to be processed, the first-stage delay line candidate parameter y is incremented by 1 to 2, and the first-stage optical switch 31 is related to the optical cell signal. Output highways 20-2 and 2 (= y)
The switching state is determined so as to be connected to the second optical fiber delay line 41-2, and the second stage optical switch 32 has the second optical fiber delay line 41-2 and the 1 (= z) th optical fiber. The switching state is determined so as to connect with the delay line 42-1. Regarding the third and fourth optical cell signals C and D used for processing, the second optical cell signal B is also used.
The switching state is determined in the same manner as the case.

In this way, all four optical cell signals A to D in the time slot TS1 are passed through the first-stage optical switch 31 and different first-stage optical fiber delay lines 41-1.
To 41-4 to have different delay times, and further sequentially sent to the first optical fiber delay line 42-1 of the second stage via the optical switch 32 of the second stage,
It is assumed to be continuous.

At the end of the determination of the switching state of the optical cell signal of the time slot TS1, the first stage delay line candidate parameter y is 4 and the second stage delay line candidate parameter z is 1. .

In the next time slot TS2, the optical cell signals E to E are transmitted to the output highways 20-2 to 20-4 from the optical switch unit 12 to the optical buffer memory unit 13-i.
It is assumed that G is output.

Since the number of input cells x is 3 and is larger than the value S (= 1) in the control section 15 (negative result in step 101, positive result in step 108), the control section 15 uses this time slot TS2 for processing 1 For the second optical cell signal E, the first-stage delay line candidate parameter y is set to 1, and the second-stage delay line candidate parameter z is incremented by 1 to 2.
Regarding the switch 31 of the first stage, the switching state is determined so as to connect the output highway 20-2 related to the optical cell signal and the 1 (= y) th optical fiber delay line 41-1 and the switch 31 of the second stage The switching state of the optical switch 32 is determined so as to connect the first optical fiber delay line 41-1 and the second (= z) th optical fiber delay line 42-2.

For the second optical cell signal F to be processed, the first-stage delay line candidate parameter y is incremented by 1 to 2 and the first-stage optical switch 31 is converted to the optical cell signal. The output highways 20-3 and 2 (=
y) The switching state is determined so as to connect to the (y) th optical fiber delay line 41-2, and for the second stage optical switch 32, the second optical fiber delay lines 41-2 and 4 (=
The switching state is determined so as to connect the z) th optical fiber delay line 42-2. The switching state of the third optical cell signal G to be processed is determined in the same manner as in the case of the second optical cell signal F.

In this way, all the three optical cell signals E to G in the time slot TS2 are transmitted through the first-stage optical switch 31 and different first-stage optical fiber delay lines 41-1.
To 41-3 to have different delay times, and further sequentially sent to the second optical fiber delay line 42-2 of the second stage via the optical switch 32 of the second stage,
It is assumed to be continuous.

At the end of the determination of the switching state of the optical cell signal of the time slot TS2, the first stage delay line candidate parameter y is 3 and the second stage delay line candidate parameter z is 2. .

In the next time slot TS3, it is assumed that no optical cell signal is output from the optical switch unit 12 to the output highways 20-2 to 20-4 to the optical buffer memory unit 13-i. At this time, since the number x of input cells is 0 (affirmative result in step 101), the first-stage delay line candidate parameter y is decremented by 1 to 2, and the second-stage delay line candidate parameter z continues to have the value 2. To do.

In the next time slot TS4, the optical cell signal H is output to the output highways 20-1 and 20-3 from the optical switch section 12 to the optical buffer memory section 13-i.
And I are output.

Since the number of input cells x is 2 and is smaller than the value S (= 3) in the control section 15 (negative result in step 101, negative result in step 108), the control section 15 uses this time slot TS4 for processing 1 For the first optical cell signal H, for the switch 31 of the first stage, connect the output highway 20-1 related to the optical cell signal and the 2 (= y) th optical fiber delay line 41-2. And the switching state of the second-stage optical switch 32 is set so as to connect the second optical fiber delay line 41-2 and the 2 (= z) th optical fiber delay line 42-2. decide.

For the second optical cell signal I to be processed, the first stage delay line candidate parameter y is incremented by 1 to 3, and the optical switch signal 31 of the first stage is converted to the optical cell signal. The output highways 20-3 and 3 (=
The y) th optical fiber delay line 41-3 is connected to determine the switching state, and the second stage optical switch 32 has the third optical fiber delay lines 41-3 and 2 (=
The switching state is determined so as to connect the z) th optical fiber delay line 42-2.

In this way, all the two optical cell signals H and I in the time slot TS4 are transmitted through the first-stage optical switch 31 to different first-stage optical fiber delay lines 41-.
2 and 41-3 so that the delay times are made different from each other, and are further sequentially sent to the second optical fiber delay line 42-2 of the second stage via the optical switch 32 of the second stage. , Will be continuous.

The optical cell signals A to I that have passed through the second stage optical fiber delay line group 42 are concentrated by the 4: 1 optical coupler 50 and output without collision of optical cell signals and without reversal of the time sequence. It is output to the port 14-i.

As described above, according to the optical buffer memory device (optical buffer memory unit) of the first embodiment, the optical cell signals are buffered without colliding with each other and without reversing the order of the optical cell signals. Can be output.

Further, according to the optical buffer memory device of the first embodiment, cell discard can be prevented more than ever before even if the amount of optical cell signals in one output highway increases.
That is, even if there is a traffic bias, the first
Since the output highways share the second fiber delay line group, the traffic bias is dispersed, the buffer memory usage efficiency can be improved, and cell discard due to the traffic bias can be prevented.

Further, according to the optical buffer memory device of the first embodiment, the hardware scale can be reduced as compared with the conventional proposed device. For example, the 4 × 4 optical switch is applied, and when the four optical cell signals are continuously input to all four output highways, the optical buffer memory device according to the first embodiment that satisfies the cell discard rate of 0 is configured. If this is attempted, the number of switch elements made up of 2 × 2 optical switches required in the entire apparatus is 96, and in the prior art, the number of switch elements made up of 2 × 2 optical switches required to satisfy the same condition. The number is 192.

That is, according to the first embodiment, it is possible to realize an optical buffer memory device having a good characteristic with respect to the discard rate of optical cell signals with a small amount of hardware and capable of performing a basic operation as a buffer memory.

FIG. 6 shows the configuration of the second embodiment of the optical buffer memory device (optical buffer memory section) according to the present invention. Note that the same or corresponding portions as those in FIG. 1 are denoted by the same or corresponding reference numerals.

In the optical buffer memory device of the first embodiment, if the number of optical cell signals that can be buffered (hence the maximum delay time) is to be increased, the delay line number L of the first stage optical fiber delay line group 41 and It is necessary to increase the number M of delay lines of the two-stage optical fiber delay line group 42, and especially to increase the number M of delay lines of the second-stage optical fiber delay line group 42. Therefore, the second-stage optical switch 32 of L × M configuration
You have to apply a large one as this second
It may be difficult to realize the stepped optical switch 32.

The optical buffer memory device (optical buffer memory unit) 13-i of the second embodiment takes this point into consideration. The optical switch 3s (s is 1 to Z) and the optical fiber delay line group 4s are used. The following basic components are cascade-connected by more than two Z stages (Z is 3 or more), and a Z: 1 optical coupler 50 for concentrating is provided on the output side of the final stage optical fiber delay line group 4Z to output ports. The optical cell signal is transmitted to 14-i.

Also in this second embodiment, L optical fiber delay lines 4 constituting the first stage optical fiber delay line group 41 are formed.
The delay times of 1-1 to 41-L are different, and the delays of the respective optical fiber delay lines 41-1, ..., 41-L are arithmetically different and differ by 1 cell signal time (T). Time is selected. That is, the delay time of the a-th (a is 1 to L) optical fiber delay line 41-l is (a-1)
Selected as × T. In addition, M optical fiber delay lines 42-1 to 4-4 forming the second-stage optical fiber delay line group 42.
2-M has different delay times,
Time (N-1) times (N-1) times 1 cell signal time (T)
Each optical fiber delay line 42-
A delay time of 1, ..., 42-M is selected. That is, the b-th (b is 1 to M) optical fiber delay line 42-b
The delay time of is selected as (b-1) * (N-1) * T. For the optical fiber delay line groups 43 to 4Z in the third stage and thereafter, the delay time of each optical fiber delay line in that stage is
Similar to the second stage optical fiber delay line group 32, the differential time is selected in the arithmetic progression with (N-1) * T.

As described above, the optical switch 3s (s is 1 to
Z) and the number of stages Z of the basic constituent elements consisting of the optical fiber delay line group 4s is selected to be 3 or more, the number of delay lines of each of the optical fiber delay line groups 42 to 4Z after the second stage is reduced. However, the maximum delay time of the optical buffer memory unit 13-i can be made considerably long, and the optical switches 32 to 3Z in the second and subsequent stages can be easily implemented.

The control unit 15 of the second embodiment also uses the optical switch 31 of each stage according to the routing information of the input optical cell signal.
Control the switching state of ~ 3Z. The control method by the control unit 15 may be any method as long as the optical cell signals are output to the output port 14-i without collision and without reversing the order of the optical cell signals. Although illustration is omitted, the following example can be given.

The controller 15 determines the switching state of the first-stage optical switch 31 so that the optical cell signals of the same time slot are input to the second-stage switch 32 at different timings. The control unit 15 determines the switching states of the optical switches 32 to 3Z of the second and subsequent stages so that the input optical cell signals of the same time slot pass through the same optical fiber delay line. Here, in the case of increasing the delay time of the optical fiber delay line in the second and subsequent stages of the optical cell signal by (N−1) × T, the optical fiber delays at the same positions of the respective optical fiber delay line groups 32 to 3Z. Line 32
The number of passages of −u to 3Z−u is increased by 1, and the optical fiber delay lines 32- (u−1) to 3Z− (u− at the positions before that are increased.
The switching state is determined so that the number of passages in 1) is reduced by 1. Note that all the optical fiber delay lines 32 at that position
-U to 3Z-u is used for passing, the delay time is (N-
1) When increasing by T, one of the optical fiber delay lines 32-u to 3Z-u at that position, for example, 32-u, is replaced with the optical fiber delay line 32 at the next position u + 1 in the stage.
The switching state is defined so as to pass-(u + 1).

According to the second embodiment as well, similar to the first embodiment, an optical buffer memory having a good characteristic with respect to the discard rate of optical cell signals with a small amount of hardware and capable of executing the basic operation as a buffer memory. The device can be realized. Moreover, even when the maximum delay time is increased, the scale of the optical switch in each stage can be suppressed, and the feasibility can be improved.

In each of the above embodiments, the switching control is performed so that the input optical cell signals in the same time slot pass through the same optical fiber delay line for the optical fiber delay line groups of the second and subsequent stages. However, the switching control method is not limited as long as the optical cell signals can be buffered and output without collision and without reversing the order of the optical cell signals.

Further, in each of the above embodiments, the delay time of each optical fiber delay line is calculated by arithmetic progression with the 1-cell signal time (T) as the differential time for the first stage optical fiber delay line group. For the first-stage optical fiber delay line group, the delay time of each optical fiber delay line is shown as an arithmetic series with 1 cell signal time (T) as the equal time. If the cell signals can be buffered and output without collision and without reversing the order of the optical cell signals, the delay time between the optical fiber delay lines of the optical fiber delay line group at a certain stage is different. The difference time to be set may be arbitrarily selected. In addition, it is considered that switching control can be most easily performed by selecting the delay time as in the first and second embodiments.

Further, in each of the above embodiments, the optical switch is used as the route switching means, the optical fiber delay line is used as the delay element, and the optical coupler is used as the concentrating means. Of course, other elements to achieve may be applied. For example, an optical switch having one terminal on the output side may be applied as the concentrating means.

Furthermore, when the optical buffer memory device of the present invention is applied to an optical ATM switch, each optical buffer memory unit is configured so that the number of cascaded stages of its basic unit and the number of optical fiber delay lines of each stage are different. You may. For example, the maximum delay time (the number of optical cell signals that can be buffered) of the optical buffer memory part where the traffic is concentrated and the line usage rate is considered to be high is configured to be larger than other optical buffer memory parts. Just do it.

In the above embodiment, the optical buffer memory device of the present invention is applied to the output stage of the optical ATM switch, but it may be applied to the input side of the optical ATM switch, or other optical devices. It may be applied to a packet switch. Further, it may be applied to a buffer memory unit of an optical processing device other than the exchange, and the buffering unit may be a fixed-length signal other than a packet signal (a signal composed of a header and an information field). . In the claims, the term "optical cell signal" is used because there is no suitable term that comprehensively describes these buffering units.

[0069]

As described above, according to the optical buffer memory device of the present invention, the route switching means for switching between a plurality of routes and the delay time provided on the output side of the route switching means. A group of a plurality of delay elements that are different in arithmetic series is used as a basic constituent element, and the basic constituent elements are cascaded in a plurality of stages, and at the same time, an optical cell signal is concentrated through the delay element group in the final stage to output port. Since the line concentrating means for sending to, and the control means for controlling the switching state of the route switching means of each stage according to the input state of the optical cell signal from each input port are provided,
Even in the case of uneven traffic, cell discard can be sufficiently suppressed, and the hardware configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a block diagram showing a configuration of an optical ATM switch.

FIG. 3 is a block diagram showing a conventional configuration.

FIG. 4 is a flowchart showing an example of a control method of a control unit of the first embodiment.

FIG. 5 is an explanatory diagram showing a concrete buffering state of the first embodiment.

FIG. 6 is a block diagram showing a configuration of a second embodiment.

[Explanation of symbols]

13-i ... Optical buffer memory unit (optical buffer memory device), 14-i ... Output port, 15 ... Control unit (control means), 20-1 to 20-N ... Highway (input port), 31-3Z ... Optical Switch (route switching means), 41
4Z ... Optical fiber delay line group (delay element group), 50 ... Optical coupler (concentrator).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location H04L 13/08 9371-5K (72) Inventor Yukihiko Suzuki 1-12 No. 1 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (3)

[Claims] 1. An optical buffer memory device for buffering optical cell signals appropriately input from N input ports for each time slot and sending them to one output port, and switching between a plurality of routes. The route switching means and a group of a plurality of delay elements provided on the output side of the route switching means and having different delay times in arithmetic series are used as basic constituent elements, and the basic constituent elements are cascaded in a plurality of stages. At the same time, a concentrating means for concentrating the optical cell signals through the delay element group at the final stage and sending them to the output port, and the route of each stage depending on the input situation of the optical cell signal from each of the input ports. An optical buffer memory device comprising: a control unit for controlling a switching state of the switching unit. 2. The number of cascade connections of the basic structural unit is two, and the delay time of each delay element of the delay element group of the first stage starts from 0 where 1 cell signal time is an equal difference time. The difference is selected so as to be different in arithmetic series, and the delay time of each delay element of the delay element group of the second stage is set to (N-1) times the signal time of one cell as the equal difference time. 2. The optical buffer memory device according to claim 1, wherein the optical buffer memory devices are selected so as to differ in arithmetic series starting from. 3. The number of cascade connections of the basic structural unit is three or more, and the delay time of each delay element of the delay element group of the first stage is 1 cell signal time as an equal difference time, and from 0 to The delay time of each delay element of the delay element group of the s-th (s is 2 or more) stage is set to (N-1) times the one-cell signal time. 2. The optical buffer memory device according to claim 1, wherein the optical buffer memory device is selected so as to be arithmetically different starting from 0, which is an arithmetic time.