JPH08125462A - Cmos differential amplifier circuit and deltasigma circuit using it - Google Patents

Abstract

PURPOSE: To obtain the CMOS differential amplifier circuit in which fluctuation in an operating point is effectively suppressed. CONSTITUTION: Amplitude limit circuits 21, 22 are provided in a feedback circuit of a CMOS operational amplifier 20. The amplitude limit circuit 21 is made up of two PMOS TRs QP11, QP14 of diode connection which are connected between input and output in opposite polarity to each other and two NMOS TRs QN12, QN13 of diode connection which are connected between input and output in opposite polarity to each other similarly. The other amplitude limit circuit 22 is made up of two PMOS TRs QP21, QP24 of diode connection and two NMOS TRs QN22, QN23 of diode connection similarly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS differential amplifier circuit and a ΔΣ modulator using the same.

[0002]

2. Description of the Related Art Conventionally, a ΔΣ modulator has been known as a Δ modulator that obtains a noise shaping effect by concentrating quantization noise on the high frequency side. The ΔΣ modulator is a 1-bit D / A converter that requantizes a multi-bit digital signal and converts it into a 1-bit digital signal,
It is used for an A / D converter that converts an analog signal into a digital signal.

The ΔΣ modulator is a switched-capacitor integrator connected to a signal input terminal, a 1-bit quantizer that quantizes the integrator output and outputs the quantized output to a signal output terminal, and the output of this quantizer is 1 The delay circuit delays the sample and returns it to the signal input terminal. The switched capacitor integrator is configured, for example, by combining a differential amplifier circuit using a CMOS operational amplifier, a switch element and a capacitor. Basically, one switched capacitor integrator is enough. A combination of two or three stages is called a secondary or tertiary ΔΣ modulator, respectively.

[0004]

In a third-order or higher order ΔΣ modulator, a CM of a switched capacitor integrator is used.
When the output of the OS differential amplifier circuit fully swings to the power supply level, the phase delay of the feedback loop in the ΔΣ modulator exceeds 180 ° due to input over, and there is a problem that the oscillation state is entered.

The present invention has been made in view of the above points, and an object of the present invention is to provide a CMOS differential amplifier circuit in which fluctuations in the operating point are effectively suppressed. This invention also
An object of the present invention is to provide a ΔΣ modulator capable of stable operation by effectively limiting the output amplitude of a CMOS differential amplifier circuit.

[0006]

The present invention provides a differential amplifier circuit comprising a CMOS operational amplifier and a feedback circuit connected between the input and output ends of the CMOS operational amplifier, wherein a diode is provided in the feedback circuit. 2 Ps connected
It is characterized in that an amplitude limiting circuit including a MOS (p-channel MOS) transistor and two diode-connected NMOS (n-channel MOS) transistors is provided.

The present invention also relates to a switched-capacitor integrator having three or more stages connected to a signal input terminal, a 1-bit quantizer which quantizes the output of the integrator and outputs it to a signal output terminal, In the ΔΣ modulator having a delay circuit for delaying the output of the quantizer by one sample and feeding back to the signal input terminal side, the switched capacitor integrator is provided between the CMOS operational amplifier and the input / output terminal of the operational amplifier. Two PMOS transistors and a diode connected in the feedback circuit, which is composed of a differential amplifier circuit composed of connected feedback circuits, and is included in the feedback circuit of at least the third and subsequent stages of the switched capacitor integrator. It is characterized in that an amplitude limiting circuit composed of two connected NMOS transistors is provided.

[0008]

In order to prevent the fluctuation of the operating point due to the full swing of the output as described above, it is necessary to limit the output amplitude of the CMOS differential amplifier circuit. However, according to the experiments by the inventors, it is difficult to completely suppress the fluctuation of the operating point even if the diode is simply inserted in the feedback circuit to limit the amplitude. According to this invention, the amplitude limiting circuit in the feedback circuit is
By using individual PMOS transistors and NMOS transistors and setting their dimensions optimally, C
The operating point of the MOS differential amplifier circuit can be kept extremely stable. In addition, a CMOS whose operating point is stabilized in this way
By using the differential amplifier circuit in the switched capacitor integrator of at least the third stage of the high-order ΔΣ modulator, the oscillation caused by the slight fluctuation of the operating point is surely suppressed and stable operation is enabled. A ΔΣ modulator can be obtained.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a third-order Δ according to an embodiment of the present invention.
This is the configuration of the Σ modulator. The difference between the input signal and the feedback data from the 1-sample delay circuit 18 is calculated in the adder 11, and the difference is integrated in the first-stage integrator 12. Similarly, the output of the integrator 12 is subtracted from the feedback data by the adder 13 and integrated by the second-stage integrator 14. The output of the integrator 14 is further subtracted from the feedback data by the adder 15,
It is integrated by the third stage integrator 16. The output of the integrator 16 is
It is output as a serial bit signal string from the 1-bit quantizer 17 composed of a clocked comparator.

FIG. 2 shows a circuit configuration when the third stage integrator 16 of FIG. 1 is configured as a switched capacitor integrator. The CMOS operational amplifier 20 is used to configure a differential output differential amplifier circuit. Switch elements S11, S12, S13, S14 and capacitors C11, C12 are arranged on the non-inverting input terminal side, and similarly on the inverting input terminal side,
Switch elements S21, S22, S23, S24 and capacitor C2
1 and C22 are arranged to form a switched capacitor integrator.

An amplitude limiting circuit 21 is provided in the feedback circuit between the inverting output terminal and the non-inverting input terminal of the differential amplifier circuit.
Similarly, the amplitude limiting circuit 22 is provided in the feedback circuit between the non-inverting output terminal and the inverting input terminal. FIG. 3 is a CMO specifically showing the parts of the amplitude limiting circuits 21 and 22.
This is an S differential amplifier circuit configuration.

The amplitude limiting circuit 21 is composed of two PMOSs which are diode-connected and are connected between the input and the output in opposite polarities.
Transistors QP11 and QP14, and two Ns which are similarly diode-connected and connected in opposite polarities between the input and output
It is composed of MOS transistors QN12 and QN13. Similarly, the other amplitude limiting circuit 22 has two diode-connected PMOS transistors QP21 and QP24.
, And similarly, two diode-connected NMOS transistors QN22 and QN23. The input resistors R11, R21 and the feedback resistors R12, R22 determine the gain of the differential amplifier circuit.

Each MO constituting the amplitude limiting circuits 21 and 22
The S transistor has a ratio of gate width W to gate length L of W / L
Are relatively set as shown in Table 1 below.

[0014]

[Table 1]

The amplitude limiting circuit 2 configured as described above
Data obtained by measuring the input / output voltage characteristics of the CMOS differential amplifier circuit having 1 and 22 will be described below together with a comparative example. First, the characteristics when the amplitude limiting circuits 21 and 22 are not provided are shown in FIG.
Is. When the output voltage approaches the maximum amplitude, the input terminal potentials V1 and V2 are separated as shown in the figure, and the operating point becomes unstable. On the other hand, the case of this embodiment is shown in FIG. The input terminal potential V1 = V2 is extremely stably maintained at a constant value regardless of changes in the input / output voltage.

FIG. 5 shows a case where the pair of the NMOS transistor QN13 and the PMOS transistor QP14 and the pair of the NMOS transistor QN23 and the PMOS transistor QP24 in the amplitude limiting circuits 21 and 22 in FIG. 3 are omitted for comparison. Although the relationship of the input terminal potential V1 = V2 is maintained, it can be seen that the value is slightly raised to the positive side in the vicinity of the circuit threshold value as compared with FIG. That is, the operating point is slightly unstable. FIG. 6 also shows PM
OS transistor QP11 and NMOS transistor QN12
, And the pair of the PMOS transistor QP21 and the NMOS transistor QN22 are omitted. Also in this case, the operating point is slightly unstable as compared with FIG.

FIG. 7 shows NMOS transistors QN12 and QN.
This is a case in which N13, QN22, and QN23 are omitted and the amplitude limiting circuits 21 and 22 are configured by only PMOS transistors. FIG. 8 shows PMOS transistors QP11, QP14, Q
This is a case in which P21 and QP24 are omitted and the amplitude limiting circuits 21 and 22 are configured by only NMOS transistors. In these cases, the instability of the operating point is greater.

From the above data, the CMOS differential amplifier circuit of this embodiment having the amplitude limiting circuits 21 and 22 in which two PMOS transistors and two NMOS transistors are optimally set in size and combined, the operating point is extremely stable. It is possible to operate the circuit. By using such a CMOS differential amplifier circuit for at least the third stage switched-capacitor integrator 16 shown in FIG. 1, the ΔΣ modulator oscillates with a large shift in the operating point as in the conventional case. The situation is surely prevented.

As described above, in the third-order ΔΣ modulator, at least the third stage integrator 16 has the CMOS described in FIG.
Although it is effective to use the differential amplifier circuit, it is of course possible to use the same CMOS differential amplifier circuit for the first-stage integrator 12 and the second-stage integrator 14. In addition, the present invention provides a high-order ΔΣ modulator of the third order or higher in which a slight shift in the operating point leads to oscillation, and a C
The effect is obtained by using the MOS differential amplifier circuit.

In the embodiment, a CMOS differential amplifier circuit of differential output has been described, but the present invention is not limited to this, and as shown in FIG. 10, a single end type CM is used.
The present invention can be similarly applied to the OS differential amplifier circuit.

[0021]

As described above, according to the present invention, the amplitude limiting circuit including the two diode-connected PMOS transistors and the same two diode-connected NMOS transistors is provided in the feedback circuit. ,
It is possible to obtain a CMOS differential amplifier circuit that effectively suppresses fluctuations in the operating point. Further, by forming a switched capacitor integrator in the third and subsequent stages using such a CMOS differential amplifier circuit, a high-order ΔΣ modulator that reliably suppresses oscillation and secures stable operation is provided. Obtainable.

[Brief description of drawings]

FIG. 1 shows a configuration of a ΔΣ modulator according to an embodiment of the present invention.

FIG. 2 shows a configuration of a third stage integrator 16 in FIG.

FIG. 3 shows a CMOS differential amplifier circuit configuration used in the integrator of FIG.

FIG. 4 shows input / output characteristics of the CMOS differential amplifier circuit according to the embodiment.

FIG. 5 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 6 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 7 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 8 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 9 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 10 shows a configuration of a CMOS differential amplifier circuit according to another embodiment.

[Explanation of symbols]

11, 13, 15 ... Adder, 12, 14, 16 ... Switched capacitor integrator, 17 ... 1-bit quantizer, 1
8 ... 1 sample delay circuit, 20 ... CMOS operational amplifier,
21, 22 ... Amplitude limiting circuit, QP11, QP14, QP21,
QP24 ... PMOS transistor, QN11, QN14, QN2
1, QN24 ... NMOS transistor.

Claims (2)

[Claims] 1. A differential amplifier circuit comprising a CMOS operational amplifier and a feedback circuit connected between the input and output ends of the CMOS operational amplifier, wherein two diode-connected PMOs are provided in the feedback circuit.
S-transistor and diode-connected two NMOs
A CMOS differential amplifier circuit characterized in that an amplitude limiting circuit composed of S transistors is provided. 2. A switched-capacitor integrator having three or more stages connected to a signal input terminal, and a 1-bit quantizer which quantizes an output of the integrator and outputs the quantized signal to a signal output terminal.
In a ΔΣ modulator having a delay circuit for delaying the output of the quantizer by one sample and feeding back to the signal input terminal side, the switched capacitor integrator is provided between a CMOS operational amplifier and an input / output terminal of the operational amplifier. Two PMOS transistors, which are diode-connected, in the feedback circuit in the integrator of at least the third stage of the switched-capacitor integrator, the differential amplifier circuit including a feedback circuit connected to A ΔΣ modulator characterized in that an amplitude limiting circuit composed of two diode-connected NMOS transistors is provided.