JP2979982B2 - CMOS differential amplifier circuit and ΔΣ modulator using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS differential amplifier circuit and a .DELTA..SIGMA. Modulator using the same.

[0002]

2. Description of the Related Art Conventionally, a Δ 知 modulator has been known as a Δ modulator which obtains a noise shaping effect by concentrating quantization noise on a high frequency side. The ΔΣ modulator is a 1-bit D / A converter that requantizes a multi-bit digital signal and converts it into a 1-bit digital signal,
It is used for an A / D converter that converts an analog signal into a digital signal.

The ΔΣ modulator includes a switched capacitor integrator connected to a signal input terminal, a 1-bit quantizer that quantizes the output of the integrator and outputs the result to a signal output terminal, and outputs the output of the quantizer to 1 And a delay circuit that delays the sample and feeds it back to the signal input terminal. The switched capacitor integrator is configured by, for example, combining a differential amplifier circuit using a CMOS operational amplifier, a switch element, and a capacitor. Basically, only one switched capacitor integrator is required. Those connected to two or three stages are called secondary or tertiary ΔΣ modulators, respectively.

[0004]

In a third-order or higher order ΔΣ modulator, a switched capacitor integrator CM
When the output of the OS differential amplifying circuit fully swings to the power supply level, there is a problem in that an input state causes the phase lag of the feedback loop in the ΔΣ modulator to exceed 180 °, thus causing an oscillation state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a CMOS differential amplifier circuit in which operating point fluctuation is effectively suppressed. The invention also provides
It is an object of the present invention to provide a ΔΣ modulator that enables stable operation by effectively limiting the output amplitude of a CMOS differential amplifier circuit.

[0006]

SUMMARY OF THE INVENTION The present invention, in the differential amplifier circuit composed of a feedback circuit connected between the input and output terminal of the CMOS operational amplifier circuit and the CMOS operational amplifier, the feedback circuit, Two PMOS transistors (p-channel MOS transistors) which are diode-connected and connected between the input / output terminals in opposite polarities, and two NMOS transistors which are diode-connected and connected between the input / output terminals and have opposite polarities. An amplitude limiting circuit comprising transistors (n-channel MOS transistors), wherein the two PMOS transistors and the two NMOSs are provided.
The dimensions of the transistors are optimally designed so that the operating point of this differential amplifier circuit is more stable than when either pair of these two PMOS transistors and two NMOS transistors are missing. Features. In the present invention, preferably, the two NMOSs
The gate and the drain of the transistor are the CMOS
When the ratio W / L of the gate width W and the gate length L of the first NMOS transistor whose source is connected to the input terminal of the operational amplifier to the output terminal of the CMOS operational amplifier is 1, this first NMOS transistor The W / L of the second NMOS transistor diode-connected to the opposite polarity is 5, and of the two PMOS transistors, the gate and the drain are the input terminals of the CMOS operational amplifier and the source is the CM.
The W / L of the first PMOS transistor connected to the output terminal of the OS operational amplifier is 15, and the second PMOS diode-connected to the polarity of the first PMOS transistor is opposite to that of the first PMOS transistor.
The W / L of the transistor is set to 3 respectively.

The present invention also provides a switched capacitor integrator having three or more stages connected to a signal input terminal, a 1-bit quantizer for quantizing an output of the integrator and outputting the quantized output to a signal output terminal. A .DELTA..SIGMA. Modulator having a delay circuit for delaying the output of the quantizer by one sample and feeding back to the signal input terminal side, wherein the switched capacitor integrator comprises a CMOS operational amplifier and an input / output terminal of the CMOS operational amplifier. And a diode-connected input of the CMOS operational amplifier in a feedback circuit in at least the third and subsequent stages of the switched-capacitor integrators. Two PMOS transistors connected in opposite polarities between output terminals and a diode-connected two input / output terminals of the CMOS operational amplifier. An amplitude limiting circuit comprising two NMOS transistors connected in opposite polarities is provided, and the dimensions of the two PMOS transistors and the two NMOS transistors are the same as those of the two PMOS transistors.
It is characterized in that it is optimally designed so that the operating point of this differential amplifier circuit is more stable than when one of the pair of the S transistor and the two NMOS transistors is missing.

[0008]

In order to prevent the variation of the operating point due to the full swing of the output as described above, it is necessary to limit the output amplitude of the CMOS differential amplifier circuit. However, according to the experiments by the inventors, it is difficult to completely suppress the operating point fluctuation even if the amplitude is limited by simply inserting a diode in the feedback circuit. According to this invention, the amplitude limiting circuit in the feedback circuit is
By using each PMOS transistor and NMOS transistor and optimizing their dimensions, C
The operating point of the MOS differential amplifier circuit can be kept extremely stable. In addition, the CMOS which stabilizes the operating point in this way
By using a differential amplifier circuit for at least the third and subsequent stages of a switched capacitor integrator of a high-order ΔΣ modulator, oscillation caused by a slight change in operating point is reliably suppressed and stable operation is enabled. A ΔΣ modulator can be obtained.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a third-order Δ according to an embodiment of the present invention.
Σ This is the configuration of the modulator. The difference between the input signal and the feedback data from the one-sample delay circuit 18 is calculated in the adder 11, and the difference is integrated by the first-stage integrator 12. Similarly, the output of the integrator 12 is subtracted from the feedback data by the adder 13 and integrated by the second-stage integrator 14. The output of the integrator 14 is further subtracted from the feedback data by the adder 15,
It is integrated by the third stage integrator 16. The output of the integrator 16 is
It is output as a serial bit signal sequence from a 1-bit quantizer 17 constituted by a clocked comparator.

FIG. 2 shows a circuit configuration when the integrator 16 at the third stage in FIG. 1 is configured as a switched capacitor integrator. The CMOS operational amplifier 20 is used to constitute a differential output differential amplifier circuit. On the non-inverting input terminal side, switch elements S11, S12, S13, S14 and capacitors C11, C12 are arranged.
Switch elements S21, S22, S23, S24 and capacitor C2
1 and C22 are arranged to form a switched capacitor integrator.

An amplitude limiting circuit 21 is provided in a feedback circuit between the inverted output terminal and the non-inverted input terminal of the differential amplifier circuit.
Similarly, an amplitude limiting circuit 22 is provided in a feedback circuit between the non-inverting output terminal and the inverting input terminal. FIG. 3 is a CMO specifically showing the portions of these amplitude limiting circuits 21 and 22.
This is an S differential amplifier circuit configuration.

The amplitude limiting circuit 21 is composed of two PMOSs which are diode-connected and which are connected between input and output in opposite polarities.
Transistors QP11 and QP14, and two N diodes similarly diode-connected and connected in reverse polarity between the input and output.
It is composed of MOS transistors QN12 and QN13. Similarly, the other amplitude limiting circuit 22 has two diode-connected PMOS transistors QP21 and QP24.
, And two diode-connected NMOS transistors QN22 and QN23. The input resistors R11 and R21 and the feedback resistors R12 and R22 determine the gain of the differential amplifier circuit.

Each MO constituting the amplitude limiting circuits 21 and 22
The S transistor has a ratio W / L of a gate width W to a gate length L.
Are relatively set as shown in Table 1 below.

[0014]

[Table 1]

The amplitude limiting circuit 2 configured as described above
Data obtained by measuring the input / output voltage characteristics of the CMOS differential amplifier circuit having the first and second CMOS circuits will be described below along with a comparative example. First, the characteristics when the amplitude limiting circuits 21 and 22 are not provided are shown in FIG.
It is. When the output voltage approaches the maximum amplitude, the input terminal potentials V1 and V2 are separated as shown in the figure, and the operating point becomes unstable. In contrast, FIG. 4 shows the case of this embodiment. The input terminal potential V1 = V2 is very stably maintained at a constant value irrespective of a change in input / output voltage.

FIG. 5 shows a case where the pair of the NMOS transistor QN13 and the PMOS transistor QP14 and the pair of the NMOS transistor QN23 and the PMOS transistor QP24 in the amplitude limiting circuits 21 and 22 in FIG. 3 are omitted for comparison. Although the relationship of V1 = V2 of the input terminal potential is maintained, it can be seen that the value slightly rises to the positive side near the circuit threshold as compared with FIG. That is, the operating point is slightly unstable. FIG.
OS transistor QP11 and NMOS transistor QN12
And the pair of the PMOS transistor QP21 and the NMOS transistor QN22 are omitted. Also in this case, the operating point is slightly unstable compared to FIG.

FIG. 7 shows NMOS transistors QN12 and QN12.
This is a case in which N13, QN22, and QN23 are omitted, and the amplitude limiting circuits 21 and 22 are composed of only PMOS transistors. FIG. 8 shows PMOS transistors QP11, QP14, Q
P21 and QP24 are omitted, and the amplitude limiting circuits 21 and 22 are constituted only by NMOS transistors. In these cases, the operating point instability is greater.

Based on the above data, the CMOS differential amplifier circuit of this embodiment having the amplitude limiting circuits 21 and 22 in which two PMOS transistors and two NMOS transistors are optimally set in size and combined is extremely stable in operating point. Circuit operation can be performed. By using such a CMOS differential amplifying circuit for the switched capacitor integrator 16 of at least the third stage shown in FIG. 1, the ΔΣ modulator oscillates with the deviation of the operating point expanded as in the prior art. That situation is reliably prevented.

As described above, in the third-order ΔΣ modulator, at least the third-stage integrator 16 includes the CMOS described in FIG.
Although it is effective to use a differential amplifier circuit, it is of course possible to use similar CMOS differential amplifier circuits for the first-stage integrator 12 and the second-stage integrator 14. Further, the present invention provides a third-order or higher-order ΔΣ modulator in which a slight shift of the operating point leads to oscillation.
The effect can be obtained by using the MOS differential amplifier circuit.

In the embodiment, a CMOS differential amplifier circuit having a differential output has been described. However, the present invention is not limited to this, and as shown in FIG.
The present invention can be similarly applied to an OS differential amplifier circuit.

[0021]

As described above, according to the present invention, an amplitude limiting circuit including two diode-connected PMOS transistors and two diode-connected NMOS transistors is provided in a feedback circuit. ,
It is possible to obtain a CMOS differential amplifier circuit in which the operating point fluctuation is effectively suppressed. Further, by using such a CMOS differential amplifier circuit to constitute a switched capacitor integrator in the third and subsequent stages, a high-order ΔΣ modulator that reliably suppresses oscillation and secures stable operation is provided. Obtainable.

[Brief description of the drawings]

FIG. 1 shows a configuration of a ΔΣ modulator according to one embodiment of the present invention.

FIG. 2 shows a configuration of a third-stage integrator 16 of FIG.

FIG. 3 shows a configuration of a CMOS differential amplifier circuit used in the integrator of FIG. 2;

FIG. 4 shows input / output characteristics of the CMOS differential amplifier circuit according to the embodiment.

FIG. 5 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 6 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 7 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 8 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 9 shows input / output characteristics of a CMOS differential amplifier circuit of a comparative example.

FIG. 10 shows a configuration of a CMOS differential amplifier circuit according to another embodiment.

[Explanation of symbols]

11, 13, 15 ... adder, 12, 14, 16 ... switched capacitor integrator, 17 ... 1-bit quantizer, 1
8 ... 1 sample delay circuit, 20 ... CMOS operational amplifier,
21, 22 ... amplitude limiting circuit, QP11, QP14, QP21,
QP24: PMOS transistor, QN11, QN14, QN2
1, QN24 ... NMOS transistor.

Continuation of front page (56) References JP-A-2-53311 (JP, A) JP-A-4-32011 (JP, A) JP-A-3-22626 (JP, A) JP-A-3-96018 (JP) , A) Japanese Utility Model Showa 50-124842 (JP, U) IEEE Transactions on Circuits and Systems-IIII, 41 [1] (1994-1) p. 19-25 (58) Fields investigated (Int.Cl. ⁶ , DB name) H03F 3/45 H03G 11/02 H03M 3/02 H03H 19/00

Claims (3)

(57) [Claims] 1. A CMOS operational amplifier with differential amplifier circuit composed of the connected feedback circuit between the input and output terminal of the CMOS operational <br/> amplification unit, the feedback circuit, is diode-connected An amplitude limiting circuit including two PMOS transistors connected in opposite polarities between the input / output terminals and two NMOS transistors diode-connected and connected in opposite polarities between the input / output terminals is provided; The dimensions of the two PMOS transistors and the two NMOS transistors are the same as those of the two PMOS transistors and the two NMs.
A CMOS differential amplifier circuit, which is optimally designed so that an operating point of the differential amplifier circuit is more stable than a case where any pair of OS transistors is missing. 2. A switched capacitor integrator having three or more stages connected to a signal input terminal, a 1-bit quantizer for quantizing an output of the integrator and outputting the quantized output to a signal output terminal,
A delay circuit for delaying the output of the quantizer by one sample and feeding back to the signal input terminal side, wherein the switched capacitor integrator is a CMOS operational amplifier and an input / output terminal of the CMOS operational amplifier. The CMOS operational amplifier of the CMOS operational amplifier is connected to a diode in a feedback circuit of at least a third-stage integrator of the switched-capacitor integrator. An amplitude limiting circuit comprising two PMOS transistors connected in opposite polarities between input and output terminals and two NMOS transistors connected in diode and connected in opposite polarities between input and output terminals of the CMOS operational amplifier is provided. Provided and said two PMOs
The dimensions of the S transistor and the two NMOS transistors are such that the operating point of the differential amplifier circuit is more stable than when either pair of the two PMOS transistors or the two NMOS transistors is missing. A modulator characterized by being optimally designed for: 3. A gate width W and a gate of a first NMOS transistor having a gate and a drain connected to an input terminal of the CMOS operational amplifier and a source connected to an output terminal of the CMOS operational amplifier. Assuming that the ratio W / L of the length L is 1, the second NM is diode-connected to the first NMOS transistor in a reverse polarity.
The W / L of the OS transistor is 5, and of the two PMOS transistors, the gate and the drain of the first PMOS transistor are connected to the input terminal of the CMOS operational amplifier and the source is connected to the output terminal of the CMOS operational amplifier. /
L is 15, the W of the second PMOS transistor diode-connected to the first PMOS transistor in the opposite polarity.
2. The CMOS differential amplifier circuit according to claim 1, wherein / L is set to three.