JPH08125129A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device having a lifetime predicting function utilizing the HC deterioration of an LSI. CONSTITUTION: The semiconductor device comprises signal delay paths 1, 2, a comparison means 3, and an alarm signal generating means 4. The signal delay paths 1, 2 having different drift of delay are subjected to HC deterioration under actually operating state by means of a signal representative of the use frequency of an LSI for which the lifetime is predicted. The comparison means 3 monitors the delay of output or the phase variation thereof caused by deterioration of the signal delay paths 1, 2 and delivers a signal when the variation or the phase relationship exceeds a preset threshold value. The alarm signal generating means delivers an alarm signal in response to the signal. Consequently, a failure in the LSI can be predicted and a countermeasure can be taken.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an HC having semiconductor circuit characteristics.
The present invention relates to a semiconductor device having a life prediction function utilizing deterioration over time due to a phenomenon.

[0002]

2. Description of the Related Art An integrated circuit (hereinafter abbreviated as LSI) has a life span and causes a failure after operating for a certain period. The main cause of the failure is considered to be deterioration of circuit characteristics due to a hot carrier (hereinafter abbreviated as HC) phenomenon, electromigration, and wiring disconnection due to stress migration.
In recent years, the miniaturization of devices in LSI has been rapidly progressing, and it is becoming more and more difficult to secure reliability against the HC phenomenon and the like. As a technique that has been conventionally used to solve this problem, there has been adopted a method of designing with a margin including an appropriate margin when designing an LSI in order to guarantee operation for a certain period. This is to predict the circuit characteristic deterioration due to HC in the worst case and consider it as the margin of the signal propagation delay of the circuit that must be satisfied at the time of design.

[0003]

However, in the above method, even if the LSI design including the margin is performed, the LS
Since the state in which I is actually used, that is, the voltage, the temperature, the frequency of use, etc., is not necessarily the same as that at the time of assumption, even the LSIs of the same design have different lifespans. That is, it is difficult to accurately predict the life of the LSI.
On the contrary, it is necessary to set a large margin unnecessarily at the time of design.

The present invention has been made in view of the above circumstances of the prior art, and an object of the present invention is to provide a semiconductor device having a life prediction function utilizing a circuit characteristic deterioration phenomenon due to HC.

[0005]

In order to achieve the above object, the first invention comprises a plurality of signal delay paths having different delay time change rates, a comparison means, and an alarm signal generation means. There is. A signal is input to each of the signal delay paths, an output of each of the signal delay paths is input to each of comparison means, and the comparison means outputs a comparison result according to a phase relationship of outputs of the signal delay paths, and the comparison means. Is output to the alarm signal generating means, and the alarm signal generating means outputs an alarm signal according to the output of the comparing means.

A second invention is an N-channel MOS (Metal-
Oxide-Semiconductor) transistor, deterioration time load means, and deterioration amount detection time load means. The source terminal of the N-channel MOS transistor is grounded, the drain terminal of the N-channel MOS transistor is connected to the deterioration load means during deterioration, and the gate terminal of the N-channel MOS transistor is connected to the deterioration input signal during deterioration. When the deterioration amount is detected, the drain terminal of the N-channel MOS transistor is connected to the deterioration amount detecting load means, and when the deterioration amount is detected, the gate terminal of the N-channel MOS transistor is connected to the deterioration amount detecting input signal. It is output as a change in the drain terminal voltage of the N-channel MOS transistor.

A third invention has at least an A / D converter and the semiconductor device of the second invention. These A / D converter and the semiconductor device of the second invention are formed on one semiconductor substrate. The output of the semiconductor device of the second invention is input to the analog input of the A / D converter, and a digital output is obtained from the A / D converter.

A fourth invention is a system in which the semiconductor device of the first invention and at least one semiconductor integrated circuit are connected to a common bus. An operation signal of the semiconductor integrated circuit is input to the semiconductor device of the first invention via a common bus, and the operation signal is input to a signal delay path of the semiconductor device of the first invention.

[0009]

According to the present invention, the signal delay path operates to cause HC deterioration by reflecting the actual use state of the LSI, that is, the voltage, temperature, frequency of use and the like. When HC deterioration occurs, the delay value of the signal delay path changes (for example, increases) as the cumulative operating time increases. Therefore, by grasping the change of the delay value or the change of the phase of the waveform and outputting the alarm signal when the amount of change exceeds a certain amount, it becomes possible to know the life of the LSI before a failure actually occurs. Further, even when an N-channel MOS transistor is used, the change in the current drive capability of the transistor due to HC deterioration is converted into a change in voltage to capture the LSI life as in the former case.

According to the present invention, it becomes possible to eliminate the need to consider the difference in life depending on the usage state of each LSI as a margin at the time of design.

[0011]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing this embodiment.
As shown in FIG. 1, this embodiment uses two signal delay paths 1,
2, a comparing means 3, and an alarm signal generating means 4. Here, the two signal delay paths are set so that the rate of change of delay with time is different.

First, the flow of signals between the components will be described. The signal delay path 1 receives the signal A and outputs the signal C. The signal delay path 2 receives the signal B and outputs the signal D. The comparison means 3 receives the signal C and the signal D and outputs the signal E. The alarm signal generating means 4 receives the signal E and receives the signal F.
Is output.

Next, the operation will be described in detail. As the signals A and B, for example, a signal such as a clock signal of an LSI that represents the frequency of use of the LSI whose life is to be predicted is used. As the time during which the signals A and B are applied elapses, the signal delay paths 1 and 2 deteriorate in circuit characteristics due to the HC phenomenon. As a result, the delay value of the signal delay path changes. This state is shown in FIG. Here, t10 is the initial delay of the signal delay path 1, t20 is the initial delay of the signal delay path 2, and the relationship of t10> t20 is satisfied. As shown in FIG. 2, the aging rate of the delay of the signal delay path with respect to the accumulated operation time, that is, the slope of the straight line is different. Here, the aging rate is set so that the signal delay path 2 is larger than the signal delay path 1. are doing. As a method of obtaining the change rate of the circuit delay with time, there are, for example, a method of manufacturing a test circuit, evaluating HC deterioration characteristics and using the result, and a method of using a reliability simulator.

As the reliability simulator, for example, IEE Transactions on Computer Aided Design of Integrated Circuits and Systems (1993) No. 15
Pages 24 to 1534 (IEEE Transactions on Computer-AI
ded Deign of Integrated Circuits and Systems (199
3) Some are described in P.1524-1534).

As a method of designing a signal delay path by adjusting the change rate of the circuit delay with time, there is a method of changing the gate length of a MOS transistor forming the signal delay path and adjusting it. When the cumulative operation time increases, the delays of both signal delay paths increase, the delays become equal at a certain time point Y, and the delay magnitude relationship is reversed as time passes. The comparison means 3 captures and compares the change in the delay value of both signal delay paths, that is, the change in the phase of the waveform, and changes the output E when the phase relationship is reversed. As a result, the alarm signal generation means 4 outputs the signal F as an alarm signal.

As described above, in the semiconductor device of this embodiment, if the time Y at which the phase is reversed is set to a time slightly shorter than the life of the LSI in advance, the time when the individual LSIs are almost at the end of the life in actual use is obtained. It can be used up to the present and the deterioration status of the LSI can be grasped by the alarm signal before the failure of the LSI occurs.

In this embodiment, as shown in FIG. 2, the signal delay paths have different initial delays. However, as shown in FIG. 3, both signal delay paths may have the same initial delay. Here, t30 is the initial delay of both signal delay paths. As the cumulative operating time increases, the delay of both signal delay paths increases. Therefore, if the comparison means 3 detects the time when the delay difference between both signal delay paths exceeds a certain value,
For example, the output E of the comparison means 3 can be changed at a certain time Z.

Although the signal A and the signal B are different signals in FIG. 1, they may be the same signal. A simple gate chain or a critical path may be used as the signal delay path. Further, although FIGS. 2 and 3 show the case where the cumulative operation time and the delay of the signal delay path have a linear relationship, they may have a curve relationship.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit example showing this embodiment. FIG.
As shown in FIG. 5, in this embodiment, the N-channel MOS transistor 5, the deterioration load means 10, and the deterioration amount detection load means 11 are used.
And switches 6, 7, 8, and 9. N channel MO
The source terminal L of the S transistor 5 is grounded, the gate terminal J is connected to the signals G and H via the switches 6 and 7,
The drain terminal K is connected via the switch 8 to the load means 1 at the time of deterioration.
In addition to being connected to 0, it is connected to the deterioration amount detection load means 11 via the switch 9. Further, the terminal of the deterioration time load means 10 not connected to the switch 8 is connected to the power supply, and the terminal of the deterioration amount detection time load means 11 not connected to the switch 9 is connected to the power supply.

Next, the operation will be described in detail. There are two modes of operation. One is a mode in which the N-channel MOS transistor is deteriorated, and the other is a mode in which the deterioration amount is detected.

The operation in the deterioration mode will be described. As the signal G, a signal representative of the frequency of use of the LSI whose life is to be predicted, such as a clock signal of the LSI, is used. Turn on switches 6 and 8 and turn off switches 7 and 9,
The deterioration time signal G is input to the gate terminal J of the N-channel MOS transistor 5, and the deterioration time load means 10 is connected to the drain terminal of the N-channel MOS transistor 5. As the time when the signal G is applied elapses, the N-channel MOS transistor 5 shows deterioration of the circuit characteristics due to the HC phenomenon. As a result, the current value of the N-channel MOS transistor 5 changes. This state is shown in FIG. Here, VDS is an N-channel MOS transistor 5
The source-drain voltage applied to the transistor, IDS, represents the drain current when the gate voltage of the N-channel MOS transistor 5 is applied to the gate terminal J. The curves in FIG. 5 represent the characteristics before deterioration due to the HC phenomenon and after deterioration after a certain time has elapsed. As shown in FIG. 5, the current value after deterioration is smaller than that before deterioration.

The operation in the deterioration amount detecting mode will be described. The switches 6 and 8 are turned off, the switches 7 and 9 are turned on, the deterioration amount detection time signal H is input to the gate terminal J of the N channel MOS transistor 5, and the deterioration amount detection time load means 11 is set to the N channel MOS transistor 5. Connect to the drain terminal of. As described with reference to FIG. 5, after the deterioration, the current value of the N-channel MOS transistor 5 is smaller than that before the deterioration. Therefore, this change is converted into a change in the drain voltage through the load means 11 at the time of detecting the deterioration amount and the drain voltage is changed. Output to terminal K.

FIG. 6 shows the states of some signals at the time of deterioration and when the deterioration amount is detected. The signals G and H applied to the gate terminal J of the N-channel MOS transistor 5 are switched by the switches 6 and 7 depending on whether the deterioration or the deterioration amount is detected.

As described above, in the semiconductor device of this embodiment, if the amount of change in drain voltage is set in advance to the amount of change due to deterioration of the LSI which is slightly shorter than the life of the LSI, the individual LSIs can be used almost in actual use. It can be used until the end of its life, and the deterioration status of the LSI can be grasped by the alarm signal before the failure of the LSI occurs.

In this embodiment, the signal G in FIG.
Although the signal and the signal H use different signals, a method using the same signal may be used. A resistance element or a P-channel MOS transistor may be used as the load means. Further, although the source terminal of the N-channel MOS transistor 5 is grounded in this embodiment, the potential of the source terminal at that time may be arbitrarily selected. The load means 10 and 11 are pull-up connected to the power source, but the power source potential at that time may be arbitrarily selected.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 is a circuit example showing this embodiment. Figure 7
As shown in FIG. 5, this embodiment comprises an A / D converter 32 for converting an analog signal into a digital signal and the semiconductor device 31 shown in the second embodiment of the present invention, which are formed on the same semiconductor substrate 30. ing.

The semiconductor device 31 receives the signals G and H and outputs the signal K. The A / D converter 32 inputs the signal K and outputs the signal M. Since the operation of the semiconductor device 31 has been described in the second embodiment, it will be omitted. When the deterioration amount is detected, the deterioration amount is output as a voltage change of the signal K, and the deterioration amount is input to the A / D converter 32 as an analog signal, converted into a digital signal, and a digital signal M having an appropriate number of bits is output.

As described above, in the semiconductor device of this embodiment, the voltage change due to the deterioration of the output K of the semiconductor device 31 is output as the digital signal M. For example, when the signal M is 4 bits, "0000" is made to correspond to the initial state before deterioration, that is, the initial value when the deterioration amount of the signal K is detected, and "1111" is maximally deteriorated, that is, when the deterioration amount of the signal K is detected. Corresponding to the maximum deterioration value of, the binary number "0000" to "1111" when the signal K has a voltage between the initial value and the maximum deterioration value.
It is only necessary to allocate the spaces linearly. If you set the threshold to a digital value corresponding to the amount of change due to deterioration in a time slightly less than the life of the LSI and monitor it, you can use each LSI until the end of its life in the actual operating condition. Moreover, it is possible to grasp the deterioration status of the LSI by the alarm signal before the failure of the LSI occurs.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 is a circuit example showing this embodiment. FIG.
As shown in FIG. 4, this embodiment is a semiconductor device including a common bus 16, signal delay paths 1, 2 and 41, a comparison means 3 and an alarm signal generation means 4 and a semiconductor device 40 similar to that of the first embodiment. The device 13, the processing device 12 built in the semiconductor device 13, the common signal 17, and the operation signals 22, 23, 24
And a semiconductor device 14 and 15.

In the system of this embodiment, the semiconductor device of the first embodiment is built in one LSI of the system consisting of a plurality of LSIs, and each LSI represents the frequency of use of each LSI. Input the signal. As a result, the LSI having the semiconductor device according to the first embodiment grasps the HC deterioration status according to the actual operation of all the LSIs in the system, and the deterioration progresses in the LSIs in the system, and the threshold value of the deterioration amount. When more than one appears, an alarm signal is issued and it is processed.

First, the flow of signals between the components will be described. The common signal 17 of the semiconductor device 14 is connected to the common bus 16, and the operation signal 23 is output to the common bus 16. The common signal 17 of the semiconductor device 15 is connected to the common bus 16, and the operation signal 24 is output to the common bus 16. The common signal 17 of the semiconductor device 13 is connected to the common bus 16, and the operation signals 23 and 24 are input from the common bus 16. Further, the operation signals 23 and 24 input to the semiconductor device 13 are input to the signal delay paths 1 and 2 of the semiconductor device 40, respectively. The common signal 17 connected to the semiconductor device 13 is connected to the processing device 12, and the output of the alarm signal generating means 4 of the semiconductor device 40 is input to the processing device 12. Signal delay path 4
An appropriate operation signal 22 is selected from the semiconductor device 13 and input to the circuit 1.

Next, the operation will be described. Semiconductor device 13, 1
4, 15 are connected to the common bus 16 to configure and operate the system. As the operation signals 23 and 24, for example, a signal of a logical product of a clock signal and a chip select signal of each LSI is used. The signal delay path 1 is deteriorated in circuit characteristics due to the HC phenomenon according to the operation of the semiconductor device 14, and the signal delay path 2 is deteriorated in circuit characteristics due to the HC phenomenon according to the operation of the semiconductor device 15. In the path 41, the circuit characteristic is deteriorated due to the HC phenomenon according to the operation of the semiconductor device 13. The comparison means 3 catches the change in the delay value of each signal delay path, compares them, and outputs the result. The alarm signal generating means 4 receives the output of the comparing means 3 as an input and outputs an alarm signal. The processing device 12 receives and processes the alarm signal.

As described above, in the semiconductor device of this embodiment, one LSI in the system grasps the HC deterioration state based on the actual operation state of all the LSIs, and when the deterioration of the LSIs progresses, an alarm signal is issued. It will be issued and by treating it appropriately, it will be able to deal with the system before it fails.

Although the operation signals 23 and 24 are provided separately from the common signal 17 as shown in FIG. 8 in this embodiment, a part of the common signals may be used as the operation signal. Good. In that case, the number of signals can be reduced. Further, in this embodiment, as shown in FIG. 8, there is only one LSI including the semiconductor device of the first embodiment in the system, but a plurality of LSIs may be provided in the system. In that case, it suffices to add an LSI including the semiconductor device of the first embodiment additionally without designing an LSI including the semiconductor device of the first embodiment according to the complexity of the system.

Further, although the semiconductor device 40 is built in the semiconductor device 13 in this embodiment, the semiconductor device 40 alone may be a single LSI.

[0040]

According to the semiconductor device of the first aspect of the invention, the signal delay path causes HC deterioration in a state where the individual LSIs on which the signal delay path is mounted is actually used, and changes in circuit characteristics are accumulated. When the change exceeds the threshold value, an alarm is issued. By selecting the threshold value properly, it becomes possible to know that a failure will occur before the LSI fails, and a serious situation such as a system down will occur. You can avoid it. In addition, it is possible to take into consideration the difference in the life of individual LSIs depending on the usage state, and it is not necessary to design excessively including a reliability margin at the time of design as in the past, so that high performance of LSIs can be realized at the same time. .

According to the semiconductor device of the second invention, an N-channel MOS transistor is mounted in an individual LSI.
Causes deterioration of the HC in a state where it is actually used and outputs a change in circuit characteristics. By monitoring this output, it becomes possible to know that a failure will occur soon before the LSI fails and a serious situation such as system down can be avoided. In addition, it is possible to take into consideration the difference in the life of individual LSIs depending on the usage state, and it is not necessary to design excessively including a reliability margin at the time of design as in the past, so that high performance of LSIs can be realized at the same time. .

According to the semiconductor device of the third invention, the A / D
Since a digital output is obtained by the converter, it can be easily mounted on a digital signal processing LSI.

According to the semiconductor device of the fourth invention, the H based on the actual operating state of all the LSIs in a particular LSI in the system.
C If the deterioration situation of the LSI is known and a deterioration of the LSI progresses, an alarm signal is issued, and by appropriately processing it, it is possible to deal with it before a system failure occurs. You will be able to avoid a serious situation. In addition, it is possible to take into consideration the difference in the lifespan of the individual LSIs that make up the system, depending on the usage state, and it is possible to avoid designing with excessive reliability margins at the time of design as in the past, thus improving the performance of each LSI. It will be possible at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to a first embodiment of the present invention.

FIG. 2 is a relationship diagram between the cumulative operating time and the delay of the signal delay path in the embodiment.

FIG. 3 is a relationship diagram between the cumulative operating time and the delay of the signal delay path in the embodiment.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of MOS transistor characteristics in the same embodiment.

FIG. 6 is a signal diagram of each part in the embodiment.

FIG. 7 is a block diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a circuit configuration according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1, 2 and 41 Signal delay path 3 Comparing means 4 Alarm signal generating means 5 N-channel MOS transistor 6, 7, 8, 9 Switch 10 Degradation load means 11 Degradation amount detection load means 12 Processing device 13, 14, 15, 31, 40 Semiconductor device 16 Common bus 17 Common signal 22, 23, 24 Operation signal 30 Semiconductor substrate 32 A / D converter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G01R 31/28 H01L 21/66 F 7735-4M

Claims (4)

[Claims] 1. A plurality of signal delay paths having different delay aging rates, a comparison means, and an alarm signal generation means, wherein signals are respectively input to the signal delay paths and outputs of the signal delay paths. Are respectively input to the comparing means, the comparing means outputs a comparison result according to the phase relationship of the output of the signal delay path, the output of the comparing means is input to the alarm signal generating means, and the alarm signal generating means. Outputs a warning signal according to the output of the comparison means. 2. A N-channel MOS transistor, a deterioration load means, and a deterioration amount detection load means, the source terminal of the N-channel MOS transistor is grounded, and the drain terminal of the N-channel MOS transistor is deteriorated. And the deterioration-time load means are connected, the gate terminal of the N-channel MOS transistor is connected to the deterioration-time input signal at the time of deterioration, and the drain terminal of the N-channel MOS transistor and the deterioration-time-detection load means are detected at the time of deterioration amount detection. The N channel M is connected when the deterioration amount is detected.
A semiconductor device, wherein a gate terminal of an OS transistor is connected to an input signal at the time of detecting a deterioration amount, and the deterioration amount is output as a change in a drain terminal voltage of the N-channel MOS transistor. 3. At least an A / D converter, and 2.
A semiconductor device described in the above, and the A / D converter,
The semiconductor device and the semiconductor device are formed on one semiconductor substrate, the output of the semiconductor device is input to an analog input of the A / D converter, and a digital output is obtained from the A / D converter. . 4. A system in which the semiconductor device according to claim 1 and at least one semiconductor integrated circuit are connected to a common bus, and an operation signal of the semiconductor integrated circuit is input to the semiconductor device via the common bus. The operation signal is input to a signal delay path of the semiconductor device.