JP3643044B2 - LSI calculation device for deterioration over time of LSI - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention predicts characteristic deterioration over time of a large-scale semiconductor integrated circuit (hereinafter abbreviated as “LSI”) due to a hot carrier phenomenon (degradation) and the like and should be expected at the time of LSI design or LSI inspection. The present invention relates to a technique for obtaining a aging deterioration margin amount.
[0002]
[Prior art]
In recent years, LSIs have been integrated with tens of millions or more of MOS transistors in order to realize various functions on one chip. In such an LSI, in order to be able to operate properly even if there are fluctuations in the power supply voltage, operating temperature, etc., and fluctuations in characteristics, a margin, that is, a margin amount is given to various characteristics in the design stage. It is necessary to keep. Hereinafter, the margin amount will be described by taking a signal delay as an example.
[0003]
As shown in FIG. 1, an LSI generally has a plurality of basic units, for example, a plurality of signal paths, each including several stages 22 (N stages in FIG. 1) between flip-flops 21 and 21, for example. It can be decomposed into 20. In many cases, each of the circuits 22 includes a logic circuit and a wiring for connecting these logic circuits. The signal delay when the signal propagates through the series of circuits 22 in the signal path 20 is within a predetermined period, that is, the clock signal 23 supplied to the flip-flops 21 and 21 as shown in the following equation (1). Within the cycle time (often the reciprocal of the operating frequency or clock frequency).
[0004]
tcycle ≧ Σti + K (i = 1 to N) (1)
Here, tcycle is a cycle time which is a design target characteristic, Σti is a total signal propagation delay between input / output terminals of each circuit i (22) between flip-flops 21 in the LSI, that is, a signal path delay, and K is a flip-flop 21 This is the sum of the setup time and the skew of the clock signal 23.
[0005]
The maximum value (worst value) of Σti can be obtained by simulation of delay variation in circuit operation. However, design labor can be saved by using derating factors obtained by coefficientizing the effects of various delay variation factors. There are known techniques for achieving this. More specifically, this is a method of designing by simply estimating the worst-case delay from the standard delay as shown in the following equation (2).
[0006]
tworst = ttyp x P x V x T (2)
Here, tworst is the maximum value (worst value) of each signal path delay, ttyp is a standard value of each signal path delay, P is a delay variation coefficient according to manufacturing variation, and V is a delay variation coefficient according to a power supply voltage variation range. , T is a delay variation coefficient corresponding to the temperature variation range, and a difference between the above two and ttyp is a margin amount with respect to the delay variation.
[0007]
The standard value ttyp of the signal path delay can be obtained by a considerably small simulation compared with obtaining the maximum value of the delay variation. That is, if the standard values of the total signal path delay of the LSI are obtained by simulation, the worst value can be obtained efficiently by simply multiplying them by the derating factors P, V, and T. Such a technique is used more often in designing LSIs for specific applications such as ASICs, compared to the types of custom designs that are frequently used, such as microprocessors.
[0008]
By the way, LSIs have a lifetime similar to other products, and cause malfunctions and malfunctions after operating for a certain period after manufacture. Known main causes of failure and malfunction of LSI are characteristic deterioration due to hot carrier phenomenon, wiring disconnection and short circuit due to electromigration. In particular, in recent LSIs, miniaturization of transistors progresses rapidly with the development of manufacturing technology, and the electric field of each part in the LSI tends to increase. For this reason, impact ionization of carriers occurs due to a high electric field generated in the vicinity of the drain, and hot carriers having high energy are likely to be generated. This hot carrier damages the gate oxide film and causes a change in the threshold voltage and drain current of the transistor with time, that is, deterioration of characteristics. As a result, there is a possibility that an operation frequency characteristic of an LSI that is an aggregate of transistors is changed and eventually a malfunction is caused. Therefore, in designing an LSI, it is indispensable to ensure reliability according to a desired product life. Therefore, a design margin that takes into account LSI degradation, that is, a time-dependent degradation margin amount is usually provided.
[0009]
More specifically, the signal path delay shown in the equation (1) is not constant over the LSI operation time as described above, but changes due to a hot carrier phenomenon or the like. The degree of delay change due to this hot carrier phenomenon depends on the circuit type, circuit operating conditions (for example, power supply voltage, temperature, number of operations, input signal slew rate, signal transition direction rising or falling, output signal Load), and variations due to manufacturing variations in circuit characteristics. Considering such deterioration over time, it is necessary not only to satisfy the above formula (1) but also to satisfy the following formula (3) in order to guarantee the operation of the LSI throughout the product life.
[0010]
tcycle ≧ Σ (ti + Δti) + K (i = 1 to N) (3)
Here, ΣΔti is a change in signal path delay due to deterioration. In this way, it is necessary to consider the influence of delay increment due to deterioration in advance, and to design an LSI in consideration of a design margin, that is, a temporal deterioration margin amount so as to satisfy the above formula (3).
[0011]
If the time degradation margin amount provided at the time of designing the LSI is too small, the reliability is insufficient, and there is a risk of malfunctioning in the future without reaching the target product life. On the other hand, if the amount of deterioration over time is too large, the reliability of the LSI becomes excessive. In general, since the reliability and performance of an LSI are in a trade-off relationship, providing excessive reliability results in a reduction in performance (for example, operating frequency) of the LSI. Therefore, if an appropriate aging deterioration margin amount cannot be set, it is difficult to develop an LSI that requires both high performance and reliability, such as a microprocessor.
[0012]
Therefore, as an LSI design verification method considering the above-described deterioration over time, a method as shown in, for example, US Pat. No. 5,634,001 is known. This is based on the LSI design information in the design process using the simulation technique shown in US Pat. No. 5,533,197, and the operation timing characteristics of the LSI after operating for a desired product lifetime, that is, All signal path delays after degradation of the LSI shown in Equation (3) are predicted, and design is performed while confirming by simulation so that the delay after degradation of the slowest signal path (critical path) is within the cycle time. It is. As a result, the aging deterioration margin amount without excess or deficiency is folded.
[0013]
However, the method of predicting all signal path delays after LSI degradation using the simulation technique as described above requires a large amount of calculation, which requires a considerable amount of calculation time, and requires a large-scale apparatus. It has the problem that it is necessary.
[0014]
On the other hand, in the same way as described in the above equation (2) for the margin amount before deterioration, it may be considered that the aging deterioration margin amount considering aging deterioration can be easily obtained using a derating factor. Therefore, it is necessary to set an appropriate derating factor value. However, the size of such a derating factor is more varied than the derating factor for determining the margin amount before deterioration, such as circuit type, history of operating conditions, variation in deterioration degree, etc. It is considered difficult to find easily because of the influence of factors. Further, the conventional design method shown by the above-mentioned US patent is a method for directly obtaining the worst delay before and after degradation in all signal paths by simulation at the time of LSI design. Application to the design method based on Equation (2) is not considered.
[0015]
In addition to the need for consideration at the LSI design stage as described above, the aging deterioration margin amount must also be taken into consideration at the inspection in the manufacturing stage. In other words, in order to guarantee a desired product life (for example, 10 years) of LSI, not only testing that it operates normally at the time before deterioration immediately after the manufacture of LSI (before shipment), It is necessary to check whether the product operates normally over the life of the product, that is, whether the aging deterioration margin is necessary and sufficient. In order to make such a confirmation, for example, as shown in US Pat. No. 5,634,001, a technique for inspecting at a voltage lower than a power supply voltage that guarantees operation is known.
[0016]
More specifically, the cycle time in which the LSI can operate normally varies depending on the power supply voltage, and as shown by the solid line in FIG. 2, when the power supply voltage is high, the operable cycle time is short (the operable frequency is high), When the power supply voltage is low, the operable cycle time is long (operable frequency is low). When the signal path delay deteriorates with time, the relationship between the power supply voltage and the operable cycle time becomes as shown by a broken line in FIG. That is, for example, when the same power supply voltage is applied before and after deterioration, the operable cycle time after deterioration becomes longer than before deterioration.
[0017]
Therefore, first, for the target LSI, the relationship between the power supply voltage before beginning-of-life and the operable cycle time (solid line in FIG. 2) is measured. In addition, by the simulation of deterioration over time, the delay tBOL in the path (critical path) with the largest signal path delay before deterioration over time and after deterioration over time (after continuing the desired product life: end-of-life) The delay tEOL in the critical path is obtained. Next, based on these, power supply voltages VBOL and VEOL operable at cycle times corresponding to the delays tBOL and tEOL for the LSI before deterioration with time are obtained, and a difference ΔV = VBOL−VEOL is calculated. A voltage (VDDmin−ΔV) lower than the guaranteed minimum voltage VDDmin by the difference ΔV is applied to the pre-degraded LSI, and if it operates at a cycle time corresponding to the delay tBOL, it is non-defective. Judge as good. That is, the delay increment before and after deterioration with time Δt = tEOL−tBOL is converted into the power supply voltage difference ΔV to estimate whether or not operation is possible after deterioration with time.
[0018]
However, as described above, the method of inspecting an LSI using the power supply voltage difference ΔV obtained by actual measurement after manufacturing the target LSI has the following problems. That is, as shown in FIG. 3, if a certain signal path A is a critical path, paying attention to the path, the power supply voltage difference ΔV is obtained by simulation and actual measurement as described above, and the power supply is based on this. It is possible to check the apparent delay increment Δt corresponding to the aging of the signal path A by controlling the voltage. (Therefore, in the method described in the above document, the LSI in the initial state is not inspected with the power supply voltage set to VDDmin as shown in FIG. 3 (1), but is changed to (VDDmin−ΔV) as shown in FIG. 3 (2). By increasing the delay and reducing the delay, the delay after the deterioration in FIG. 3 (3) is inspected.) However, the power supply voltage vs. delay and the operating time vs. delay are in a non-linear relationship. These relationships differ depending on the signal path. Therefore, even if the inspection using the power supply voltage difference ΔV set in the signal path A is determined to be non-defective, it does not always operate normally at the time of deterioration, and vice versa. Specifically, for example, as shown in FIG. 3 (4), another signal path B having the same signal path delay as the signal path A when the power supply voltage VDDmin is in the initial state as shown in FIG. 3 (5). Even if it is determined that there is no problem in the inspection with the power supply voltage (VDDmin−ΔV) within the design target delay, the delay after the degradation actually exceeds the design target delay as shown in FIG. there is a possibility.
[0019]
[Problems to be solved by the invention]
As described above, the conventional LSI design method has a problem in that it is not possible to easily obtain a deterioration margin with time in consideration of deterioration with time. In addition, in order to confirm whether the deterioration margin amount with time is necessary and sufficient, the method of adjusting and inspecting the power supply voltage at the time of inspection, that is, the inspection method of setting the power supply voltage to be low and inspecting, actual circuit deterioration There was a problem that the characteristics could not be reflected and there was a risk that proper inspection could not be performed.
[0020]
In view of the above-described problems, the present invention provides a time-dependent deterioration margin amount calculation apparatus and calculation for LSIs that can easily determine a time-dependent deterioration margin amount considering deterioration over time by using, for example, a derating factor. The purpose is to provide a method. It is another object of the present invention to provide an LSI inspection method capable of performing an appropriate inspection in consideration of deterioration over time.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an LSI for calculating a time-dependent degradation margin amount for a design margin so that the LSI can operate even when the above characteristics are deteriorated with respect to a predetermined characteristic in the LSI. An apparatus for calculating a deterioration margin amount over time, a pre-deterioration characteristic generation means for obtaining a characteristic before deterioration of the characteristic in an initial state of the LSI for at least a part of a plurality of signal paths constituting the LSI; For at least some of the plurality of signal paths constituting the LSI, after-deterioration characteristic generation means for obtaining the characteristic after deterioration of the characteristic when a predetermined operation period has passed under a predetermined operation condition, and the plurality of signal paths Among these, the signal path before the deterioration in the signal path having the smallest margin of the characteristic after the deterioration with respect to the characteristic necessary for the LSI to operate. Characteristic deterioration degree generating means for obtaining a characteristic deterioration degree that is a ratio of the characteristic after deterioration to the property, deterioration over time that substantially determines a time deterioration margin amount based on the characteristic before deterioration and the characteristic deterioration degree Margin amount generating means.
[0022]
As a result, the characteristics before deterioration are generally easier to obtain than the characteristics after deterioration. Therefore, once the degree of characteristic deterioration is obtained for a certain LSI, the characteristics of other LSIs are deteriorated each time. The time-dependent deterioration margin amount can be easily obtained without obtaining the above characteristics. Note that the time-dependent deterioration margin amount is not limited to other LSIs as described above. For example, even if the same LSI is used, the signal after the design change is not obtained for the same LSI. It may be a path. Here, the actual value required is not the time-dependent deterioration margin itself, but for example, the sum of the reference characteristic amount and the time-dependent deterioration margin amount or the reciprocal value, etc. The present invention can be applied and the same effect can be obtained as long as it is a value that substantially includes the aging deterioration margin amount as described above.
[0023]
In addition, a predetermined margin may be further included in the amount of time-dependent deterioration margin obtained as described above. In other words, for example, the reliability can be improved even for the influence of factors that are difficult to consider in obtaining the above-described characteristics, or the allowable range of reliability is expanded (a certain degree of decrease in reliability) Or the like, the deterioration margin amount with time may be increased or decreased.
[0024]
In addition, the characteristics after degradation are not necessarily obtained for all signal paths, but are necessary for the LSI to be able to operate in a group in which a plurality of signal paths constituting the LSI are divided into a plurality of groups. The characteristics after degradation may be obtained for a signal path of a group having a small margin of characteristics before degradation with respect to various characteristics. In other words, except for signal paths that have a sufficient margin in the characteristics before degradation, obtain the characteristics after degradation only for signal paths that are likely to be used to determine the degree of characteristic degradation. Thus, the amount of calculation can be reduced and the overall processing efficiency can be increased.
[0025]
The present invention can be applied to signal path delays, for example. In this case, for example, the degree of characteristic deterioration is set as a derating factor corresponding to the deterioration of the characteristic over time, and at least the delay before deterioration together with the derating factor corresponding to manufacturing variation, power supply voltage fluctuation, and temperature fluctuation is shifted. For example, it is possible to easily calculate the maximum delay including the amount of deterioration with time.
[0026]
Further, the power supply voltage condition in the predetermined operating condition when the post-degradation characteristic generation unit obtains the post-degradation characteristic, the pre-deterioration characteristic generation unit, and the post-degradation characteristic generation unit The power supply voltage condition for obtaining the characteristic and the characteristic after the deterioration is different from each other, or the pre-deterioration characteristic generation unit and the post-degradation characteristic generation unit respectively The pre-deterioration delay, and the pre-degradation delay, and the post-degradation delay characteristic of the element (for example, the characteristic of the element having the lowest responsiveness), Further, the reliability of the LSI may be further improved by obtaining the post-deterioration delay.
[0027]
In addition to the device for determining the degree of characteristic deterioration as described above, an LSI device for calculating the time degradation margin amount may be provided, which includes a time degradation margin amount generating means for substantially obtaining the time degradation margin amount. . In this case, since it is not necessary for the apparatus to have a function for obtaining the characteristic after deterioration for obtaining the characteristic deterioration degree, it is possible to obtain the deterioration margin amount with time with a small-scale apparatus.
[0028]
Further, by inspecting the operation of the LSI using the frequency obtained by multiplying the predetermined frequency by the characteristic deterioration degree obtained in the same manner as the case of obtaining the time degradation margin amount, for example, before and after the deterioration. Compared to testing with a lower power supply voltage by converting the delay difference into a power supply voltage difference, errors due to the nonlinear relationship between power supply voltage and delay, etc. cannot occur. Evaluation can be avoided reliably.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described by taking as an example a case where a predetermined characteristic of interest as an object of deterioration with time is a delay and the deterioration degree of the characteristic is a delay deterioration rate.
[0030]
(Embodiment 1)
FIG. 4 is a block diagram showing the overall configuration of a time-dependent deterioration margin amount calculation apparatus used during LSI design and inspection according to Embodiment 1 of the present invention. In the configuration of FIG.
Based on the LSI design information 301, the delay deterioration rate predicting unit 101 calculates a delay (pre-deterioration characteristic) of each signal path constituting the LSI before deterioration (characteristic before deterioration) and outputs pre-deterioration signal path delay information 302. At the same time, the delay degradation rate (characteristic degradation degree) when each signal path operates over the target period of the product life is calculated and the signal path delay degradation rate information 303 is output. The LSI design information 301 corresponds to, for example, the signal path 20 shown in FIG. 1, the type of the built-in logic circuit, the net list representing the connection relationship of the logic circuit, the parasitic element information of the connection wiring of the logic circuit, the mask shape It includes all information necessary for LSI design, such as information, manufacturing information, operating conditions (power supply voltage, temperature, operating frequency, operating frequency, etc.), and product life target. The LSI design information 301 and the following information are held in a storage unit (not shown).
[0031]
The delay-to-delay degradation rate analysis unit 102 reads the pre-degradation signal path delay information 302 and the signal path delay degradation rate information 303, and delay-to-delay degradation rate relationship information that is information relating to the correlation between delay and delay degradation rate. 304 is output.
[0032]
The delay deterioration rate extraction unit 103 (characteristic deterioration degree generation means) extracts a delay deterioration rate of a predetermined signal path to be described later based on the delay-to-delay deterioration rate relationship information 304 and outputs it as a delay deterioration margin 305. It is.
[0033]
A delay deterioration margin amount calculation unit 104 (deterioration deterioration margin amount generation means) using a derating factor calculates a delay deterioration margin amount using the delay deterioration margin 305 as a derating factor G.
[0034]
The inspection operating frequency calculation unit 105 calculates the inspection operating frequency using the delay deterioration margin 305 as the derating factor G, similarly to the delay deterioration margin amount calculation unit 104.
[0035]
More specifically, the delay deterioration rate prediction unit 101 includes, as shown in FIG. 5, for example, a signal path delay calculation unit 111a (pre-deterioration characteristic generation unit) that outputs pre-deterioration signal path delay information 302, a transistor, and the like. A pre-degradation circuit analysis unit 111 including a unit circuit stress calculation unit 111b that calculates stress received by the unit circuit, and unit circuit degradation that analyzes current-voltage characteristics based on information output from the unit circuit stress calculation unit 111b Degree analysis unit 112, post-degradation circuit analysis unit 113 (post-degradation characteristic generation means) for obtaining a post-degradation delay based on the analysis result, and the obtained post-degradation delay and signal path delay calculation unit 111a Based on the signal path delay information 302 before degradation, the delay degradation rate calculator 114 (characteristic degradation) that outputs the signal path delay degradation rate information 303 is output. Degree generating means) and are configured provided.
[0036]
Next, the operation of the time-dependent deterioration margin calculation apparatus configured as described above will be described. The operation of this computing device is roughly divided into an operation for analyzing a certain LSI in advance and obtaining a delay degradation margin 305, and another LSI (or design change) to be designed using the obtained delay degradation margin 305. In this case, there is an operation for obtaining the delay deterioration margin amount and the inspection operating frequency. The former operation is performed by the delay deterioration rate prediction unit 101, the delay versus delay deterioration rate analysis unit 102, and the delay deterioration rate extraction unit 103. Further, the latter operation is performed by a part of the delay deterioration rate prediction unit 101 (signal path delay calculation unit 111a), a delay deterioration margin amount calculation unit 104, and a test operation frequency calculation unit 105 (indicated by a broken line in FIG. 4). Component). Hereinafter, the two operations will be specifically described.
(Operation to obtain delay degradation margin)
The delay deterioration rate prediction unit 101 is disclosed in, for example, a gate level timing deterioration simulation method disclosed in US Pat. No. 5,974,247 and Japanese Patent Laid-Open No. 10-124565, BTABERT User's Manual (BTA Technology Inc., USA), US Pat. No. 5,533,197, and the like. Based on the calculated transistor level reliability simulation method, the delay before deterioration of each signal path included in the LSI is calculated, and each signal path is subjected to a predetermined operating condition (power supply voltage, operating frequency, etc.) over the target period of product life. ) Calculate the delay degradation rate when operating in).
[0037]
More specifically, in the pre-degradation circuit analysis unit 111 of the delay degradation rate prediction unit 101, the signal path delay calculation unit 111a analyzes characteristics before degradation of each signal path to calculate a signal path delay before degradation, and before degradation. Output as signal path delay information 302. Similarly to the signal path delay calculation unit 111a, the unit circuit stress calculation unit 111b analyzes the characteristics of each signal path before deterioration, and then biases the unit circuit included in each signal path, for example, the stress received by each transistor. Calculate from conditions. Next, the unit circuit deterioration degree analysis unit 112 analyzes the degree of deterioration of the voltage-current characteristics of the transistor according to the stress. The post-degradation circuit analysis unit 113 analyzes the post-degradation circuit characteristics using the voltage-current characteristics of the degraded transistor, and obtains the signal path delay after the degradation. The delay degradation rate calculation unit 114 calculates a delay degradation rate based on the signal path delay after the degradation and the pre-degradation signal path delay information 302 output from the signal path delay calculation unit 111a, and the signal path delay degradation Output as rate information 303. This delay deterioration rate is defined by the following equation (4).
[0038]
R = taged / tfresh (4)
Here, tfresh and taged are signal path delays before and after deterioration, respectively. Specific examples of the signal path delay before deterioration, the signal path delay after deterioration, and the signal path delay deterioration rate (for example, for signal paths 1 to M) are shown in a table format in FIG.
[0039]
Next, the delay-to-delay degradation rate analysis unit 102 obtains a correlation between the pre-degradation signal path delay information 302 and the signal path delay degradation rate information 303, and outputs delay-to-delay degradation rate relationship information 304. An example of the delay-to-delay deterioration rate relationship information 304 is shown in a graph form in FIG. Each plot in the figure represents the relationship between the signal path delay before deterioration and the signal path delay deterioration rate for each signal path. When the present inventors actually performed the above calculation for various LSIs, it was found that the signal path delay deterioration rate tends to decrease as the signal path delay before deterioration increases as shown in FIG. It was. The reason why such a correlation is obtained is considered to be as follows. That is, a signal path with a large delay generally means that there are a large number of logic circuit stages. In this case, normally, each logic circuit has a high response such as by increasing a bias voltage, that is, an output signal waveform. The change is configured to be relatively steep. On the other hand, in a signal path with a small number of logic circuit stages, since the delay is originally small, there is not much need to improve the responsiveness in particular, and therefore the output signal waveform is comparative. By the way, it is known that the hot carrier deterioration becomes larger as the input waveform of the logic circuit is rounded. Taking these into account, it can be qualitatively explained that the above correlation results in a distribution as shown in FIG.
[0040]
Here, for the sake of convenience of explanation, in order to simplify FIG. 7, an upper limit envelope of the signal path delay deterioration rate is shown in FIG. 8, and the signal path delay deterioration rate is indicated by the hatched line in FIG. It will be distributed in the area. The signal path delay before degradation in this distribution is the largest, that is, the signal path plotted in the vicinity of the design target delay (for example, cycle time: 5 [ns] in this example) is the critical path.
[0041]
The delay deterioration rate extraction unit 103 extracts the signal path delay deterioration rate α at the point indicated by the symbol P in FIG. 8 based on the delay-to-delay deterioration rate relationship information 304 and outputs it as a delay deterioration margin 305. Here, in FIG. 8, there are signal paths whose signal path delay deterioration rate itself is larger than the point P. However, since these signal paths have a small signal path delay before deterioration, the signal path delay after deterioration (deterioration) (Previous signal path delay × signal path delay deterioration rate) is also small and can be ignored because there is a sufficient margin in operation.
(Operation to obtain delay deterioration margin and inspection operating frequency)
Once the delay deterioration margin 305 is obtained as described above, it is used as the derating factor G, and the delay deterioration margin amount when the other LSI is designed or the same LSI is redesigned, and the inspection is performed. Therefore, the operating frequency can be easily calculated. That is, first, the signal path delay calculation unit 111a of the pre-degradation circuit analysis unit 111 in the delay deterioration rate prediction unit 101 performs the degradation of each signal path included in the LSI, as described in the operation for obtaining the delay degradation margin. The previous characteristic is analyzed to calculate the signal path delay before degradation, and the signal path delay information 302 before degradation is output. Therefore, the delay degradation margin amount calculation unit 104 calculates the worst-case delay after degradation based on the pre-degradation signal path delay information 302 and the delay degradation margin 305 as the derating factor G by the following equation (5). Ask. By designing such that the worst-case delay falls within the design target delay, an LSI capable of guaranteeing the operation throughout the lifetime can be manufactured.
[0042]
tworst = ttyp × P × V × T × G (5)
Here, tworst is the maximum value (worst value) of each signal path delay, ttyp is the standard value of each signal path delay (pre-degradation signal path delay information 302), P is a delay variation coefficient corresponding to manufacturing variation, and V is a power supply The delay variation coefficient according to the voltage variation range, T is the delay variation coefficient according to the temperature variation range, and the difference between the case where G is applied and the case where it is not applied, that is, ttyp × P × V × T × (G -1) is the delay deterioration margin amount.
[0043]
Further, the inspection operating frequency faded is obtained by multiplying the target operating frequency ffresh by the derating factor G as shown in the following equation (6).
[0044]
faged = ffresh × G (6)
An accurate inspection can be performed by supplying the inspection operating frequency obtained as described above to the LSI and inspecting whether or not the LSI operates properly. That is, the delay becomes G times due to deterioration with respect to a certain operating frequency (cycle time) and the margin is reduced, and the operating frequency is G times (cycle time is 1 / G times) the delay before deterioration. This is equivalent to reducing the margin and reducing the delay before and after deterioration into a power supply voltage difference and inspecting with a lower power supply voltage compared to the conventional method. An error due to the relationship cannot occur, and underestimation and overestimation of the aging deterioration margin value can be surely avoided.
[0045]
As described above, according to the time degradation margin amount calculation apparatus of the present embodiment, a design method using a derating factor is applied, and a time degradation margin amount (or a signal path after degradation corresponding directly thereto). (Maximum value of delay, etc.) can be easily obtained, and accurate inspection can be performed using an appropriate inspection operating frequency.
In the above example, the maximum signal path delay deterioration rate in the critical path (the signal path delay deterioration rate α at the point P in FIG. 8) is set as the delay deterioration margin 305. However, in order to further improve reliability. In addition, a value obtained by multiplying a predetermined factor larger than 1 (for example, a signal path delay deterioration rate β at a point indicated by a symbol Q in FIG. 9) may be used. That is, the degree of delay degradation may differ depending on the influence of signal overshoot caused by, for example, the characteristics of the transistors constituting the circuit and the parasitic capacitance of the wiring. In order to increase the safety factor in consideration of such factors that cause the degree of delay deterioration, the above margin rate may be applied based on empirical statistical values. Conversely, a smaller value may be used by expanding the allowable range of reliability. Even when the value of the delay deterioration margin 305 is increased / decreased in this way, since the reference value is obtained appropriately as described above, the reliability of the obtained LSI shall be managed probabilistically. Can do.
[0046]
Further, an example in which the envelope in FIG. 8 based on the simulation result of the signal path delay before deterioration and the signal path delay deterioration rate is monotonously decreased with respect to the signal path delay before deterioration is shown, as shown in FIG. Even when the envelope has irregularities, an appropriate delay deterioration margin amount can be obtained similarly. In this case, for example, the delay degradation rate γ at the point where the signal path delay after degradation becomes the largest may be used as indicated by the symbol R in FIG.
[0047]
In addition, the signal path delay before deterioration and the signal path delay deterioration rate are temporarily set for all signal paths in order to confirm that the envelope in FIG. 8 monotonously decreases with respect to the signal path delay before deterioration. It may be calculated, but when it is already calculated once, and it is known beforehand that it decreases monotonously, the signal path near the design target delay is always the required signal path delay deterioration rate. Therefore, only the signal path near the critical path may be calculated to improve the processing efficiency.
[0048]
Further, when designing a certain LSI, the delay deterioration margin 305 obtained from another plurality of LSIs may be referred to. In this case, as shown in FIG. 11, based on the envelopes A, B, and C obtained from each LSI in the same manner as in FIG. 8, for example, the signal path delay degradation of the signal path having the maximum signal path delay before degradation. The largest signal path delay deterioration rate (α: point P) among the rates may be used as a delay deterioration margin.
[0049]
Further, in the above example, an example is shown in which the characteristic of interest as a target of deterioration with time is set as a delay. However, the present invention may be applied to various characteristics that deteriorate with time, such as frequency characteristics. For example, when applied to frequency characteristics, it is obvious that the horizontal axis in FIG.
[0050]
In the above example, for the sake of convenience of explanation, the example in which the relationship between the pre-degradation signal path delay and the signal path delay degradation rate as shown in FIG. 7 is once shown is shown. It is also possible to extract the maximum signal path delay after degradation obtained in step 113 and set the signal path delay degradation rate for this to the delay degradation margin 305 (characteristic degradation degree generation means). In addition, the signal path delay after degradation is not obtained for all the signal paths, but the signal paths are grouped so that the signal path delay after degradation may be maximized. The signal path delay after degradation may be obtained only for a signal path with a small margin before degradation. That is, in general, the calculation of the post-degradation signal path delay tends to be a large-scale operation due to the repetition according to the circuit operation, compared to the calculation of the pre-degradation signal path delay. Processing efficiency can be improved.
[0051]
Further, in the above equation (5), the derating factor may be calculated by distinguishing between circuit delay and wiring delay. That is, since the delay is generally the sum of the delay due to the wiring itself and the delay due to other elements, the maximum delay may be obtained by using a separate derating factor for each, in which case the wiring itself The delay due to may not be considered degradation.
[0052]
Further, in order to obtain the delay degradation margin amount or the inspection operating frequency based on the delay degradation margin obtained in advance, an apparatus including only the components surrounded by the broken line in FIG. 4 may be configured. . That is, it is possible to configure a device that can easily and quickly obtain the deterioration margin with time by providing the delay deterioration margin with a small configuration.
(Embodiment 2)
The power supply voltage of the LSI can take various values within the specification range during the operation period from the initial state after shipment to the product life, and the degree of hot carrier deterioration depends on the power supply applied during the operation period. It depends on the voltage. Therefore, as the second embodiment, when determining the pre-degradation signal path delay information 302 and the signal path delay degradation rate information 303, the power supply voltage as an operating condition is appropriately set, so that the reliability of the LSI can be increased. An apparatus for calculating a time-dependent deterioration margin amount capable of obtaining a time-dependent deterioration margin amount for the purpose will be described. In the present embodiment, components having the same functions as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0053]
Compared with the first embodiment (FIGS. 4 and 5), the time degradation margin amount calculation apparatus according to the second embodiment has a delay deterioration rate prediction instead of the delay deterioration rate prediction unit 101 as shown in FIG. The difference is that the unit 201 is provided. The pre-degradation circuit analysis unit 211, the unit circuit degradation degree analysis unit 212, and the post-degradation circuit analysis unit 213 that constitute the delay degradation rate prediction unit 201 generally constitute the delay degradation rate prediction unit 101 of the first embodiment. The power supply voltage used when obtaining the pre-degradation signal path delay information 302 and the signal path delay degradation rate information 303 is VDDmin or VDDmax. That is, the signal path delay calculation unit 211a and the post-degradation circuit analysis unit 213 of the pre-degradation circuit analysis unit 211 obtain the pre-degradation signal path delay information 302 using the minimum power supply voltage VDDmin. Further, the unit circuit stress calculation unit 211b and the unit circuit degradation degree analysis unit 212 analyze the degradation state of each signal path using the maximum power supply voltage VDDmax.
[0054]
Setting the power supply voltage as described above means that, as shown in FIG. 13, the maximum power supply voltage VDDmax at which the signal path delay deterioration rate information 303 is the largest and the deterioration as the voltage to be operated until the product lifetime is reached. The delay deterioration margin amount is obtained by using the lowest power supply voltage VDDmin at which the previous signal path delay becomes the largest. More specifically, as shown in FIG. 14, the signal path delay after deterioration becomes larger as the power supply voltage applied at the time of deterioration becomes higher, and the power supply voltage becomes lower regardless of before and after deterioration. Since the signal path delay becomes large (for example, b> a), the signal path delay when the LSI is deteriorated by applying the maximum power supply voltage VDDmax and operating by applying the minimum power supply voltage VDDmin (same figure). C) is the largest signal path delay, and the worst value of the post-degradation delay is obtained. This value is larger than the case where the maximum power supply voltage VDDmax is simply used in all cases, and is a value that can actually occur.
[0055]
Therefore, instead of using the delay deterioration rate prediction unit 101 shown in FIG. 4 as described above, the time degradation margin amount calculation device including the delay deterioration rate prediction unit 201 is used, and by setting the power supply voltage as described above, It is possible to easily determine the delay deterioration margin amount and the inspection operating frequency under the worst conditions, and thus it is possible to obtain an LSI with higher reliability.
(Embodiment 3)
Transistor characteristics generally vary due to various factors in the manufacturing process, and the influence of hot carrier deterioration also varies. Specifically, the drain current and responsiveness typically vary. Therefore, as the third embodiment, by taking into account the variation in transistor characteristics, that is, by appropriately setting the manufacturing variation condition, it is possible to obtain a time-dependent deterioration margin amount for further improving the reliability of the LSI. A deterioration margin amount calculation apparatus will be described.
[0056]
The temporal degradation margin amount calculation apparatus according to the third embodiment has substantially the same configuration as that of the second embodiment (the delay deterioration rate prediction unit in FIG. 12 instead of the delay deterioration rate prediction unit 101 in FIG. 4). 201.). However, the pre-degradation circuit analysis unit 211, the unit circuit degradation degree analysis unit 212, and the post-degradation circuit analysis unit 213 determine the pre-degradation signal path delay information 302 and the signal path delay degradation rate information 303 in the second embodiment. In addition to the setting of the power supply voltage described in the above item, the transistor characteristic is such that the signal path delay is maximized within the range of variation. That is, for example, the drain current magnitude and response of a MOS transistor vary within a predetermined range for both the p-channel and the n-channel, and the combination of characteristics is surrounded by a solid line connecting white circles (corner conditions) in FIG. Range. (Specifically, the corner condition can be expressed by, for example, a SPICE parameter or a BTABERT parameter (BTABERT User's Manual, BTA Technology Inc., USA) used in the simulation.) While the deterioration is generally smaller than that of the n-channel MOS transistor, the characteristic of the n-channel MOS transistor deteriorates as shown by a black circle in the figure, so that the combination of characteristics falls within a range surrounded by a two-dot chain line. Therefore, by setting a variation condition using a corner condition indicated by symbol S in FIG. 15 in a simulation performed by the pre-degradation circuit analysis unit 211, the unit circuit degradation degree analysis unit 212, and the post-degradation circuit analysis unit 213, the transistor The delay deterioration margin amount and the inspection operating frequency under the worst condition that can occur in actual operation can be easily determined in consideration of the variation in the characteristics of the above, and therefore, within the range surrounded by the two-dot chain line in FIG. It is possible to obtain an LSI with higher reliability that operates reliably even if the characteristics of the transistor vary.
[0057]
For example, when the influence of variation in transistor characteristics is greater than the influence of setting the power supply voltage, the power supply voltage setting may be set to a standard value, and only the influence of the variation may be considered.
Each of the above embodiments is merely an example of introduction and description, and is not limited to this. That is, various other embodiments within the substantial scope of the present invention, and modifications from the present embodiment can be made.
[0058]
【The invention's effect】
As described above, according to the present invention, once the degree of characteristic deterioration is obtained for a certain LSI, the time-dependent deterioration margin amount can be easily obtained for other LSIs without obtaining the characteristic after deterioration each time. it can. That is, for example, it is possible to incorporate consideration of delay deterioration with time into a design method using a derating factor, and the delay after deterioration can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a general configuration of a signal path.
FIG. 2 is a graph showing a relationship between a cycle time and an inspection voltage for explaining a conventional inspection method.
FIG. 3 is an explanatory diagram showing an example of a power supply voltage and a delay before and after deterioration.
FIG. 4 is a block diagram showing an overall configuration of a time-dependent deterioration margin amount calculation apparatus according to Embodiment 1 of the present invention.
FIG. 5 is a block diagram showing a detailed configuration of a delay deterioration rate prediction unit 101. FIG.
FIG. 6 is a table showing an example of signal path delay before and after deterioration and a signal path delay deterioration rate.
FIG. 7 is a graph showing an example of a relationship between a signal path delay before deterioration and a signal path delay deterioration rate.
FIG. 8 is a graph showing an example of the relationship between a signal path delay before deterioration and a signal path delay deterioration rate using an envelope.
FIG. 9 is a graph for explaining an example of obtaining a delay deterioration rate.
FIG. 10 is a graph for explaining another example for obtaining the delay deterioration rate.
FIG. 11 is a graph for explaining still another example for obtaining the delay deterioration rate.
FIG. 12 is a block diagram showing a detailed configuration of a delay deterioration rate prediction unit 201 in the temporal deterioration margin amount calculation apparatus according to Embodiments 2 and 3 of the present invention.
FIG. 13 is a graph for explaining an example of a power supply voltage for obtaining a post-deterioration delay according to the second embodiment of the present invention.
FIG. 14 is another graph for explaining an example of the power supply voltage.
FIG. 15 is a graph illustrating an example of variation in characteristics of transistors included in an LSI.
[Explanation of symbols]
20 signal path
21 Flip-flop
22 circuits
23 Clock signal
101 Delay deterioration rate prediction unit
102 Delay versus delay degradation rate analysis unit
103 Delay deterioration rate extraction unit
104 Delay degradation margin amount calculation unit using derating factor
105 Operating frequency calculator for inspection
111 Pre-degradation circuit analyzer
111a Signal path delay calculation unit
111b Unit circuit stress calculator
112 Unit circuit degradation analysis unit
113 Post-degradation circuit analyzer
114 Delay deterioration rate calculation unit
201 Delay degradation rate prediction unit
211 Pre-degradation circuit analysis unit
211a Signal path delay calculation unit
211b Unit circuit stress calculator
212 Unit circuit deterioration analysis unit
213 Post-degradation circuit analysis unit
301 LSI design information
302 Signal path delay information before deterioration
303 Signal path delay deterioration rate information
304 Relationship between delay and delay degradation rate
305 Delay degradation margin

Claims (12)

An LSI aging deterioration amount calculation device for calculating a aging deterioration margin amount for estimating as a design margin so that the LSI can operate even when the characteristic is deteriorated with respect to a characteristic that is a delay in the LSI,
Pre-degradation characteristic generation means for obtaining characteristics before deterioration of the characteristic in the initial state of the LSI for at least some of the plurality of signal paths constituting the LSI;
For at least some of the plurality of signal paths constituting the LSI, after-degradation characteristic generation means for obtaining a characteristic after deterioration of the characteristic when a predetermined operation period has passed under a predetermined operation condition;
A characteristic that is a ratio of the characteristic after deterioration to the characteristic before deterioration in the signal path having the smallest margin of the characteristic after deterioration with respect to the characteristic necessary for the LSI to operate among the plurality of signal paths. A characteristic deterioration degree generation means for obtaining a deterioration degree;
A time-dependent deterioration margin amount generating means for obtaining a time-dependent deterioration margin amount based on the characteristic before deterioration and the characteristic deterioration degree;
A device for calculating an amount of margin for deterioration of LSI over time, comprising: An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
The time degradation margin amount generation means obtains a time degradation margin amount which is a difference between a product of the characteristic before degradation and the characteristic degradation degree and the characteristic before degradation. Quantity calculation device. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
A time degradation margin amount calculation device for an LSI, wherein the time degradation margin amount generation means obtains a time degradation margin amount by obtaining a product of the characteristic before deterioration and the characteristic deterioration degree. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
The aging deterioration margin amount generation means obtains the aging deterioration margin amount based on a predetermined margin rate together with the characteristics before deterioration and the characteristic deterioration degree, and the aging deterioration margin amount of the LSI is characterized in that Computing device. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
The after-degradation characteristic generation means is a group in which a plurality of signal paths constituting the LSI are divided into a plurality of groups, and the margin of the characteristic before deterioration is small with respect to characteristics necessary for the LSI to operate. An apparatus for calculating the deterioration margin amount of LSI over time, characterized in that the characteristic after deterioration of the signal path is obtained. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
A time degradation margin amount calculation apparatus for an LSI, wherein the time degradation margin amount generation means obtains the time degradation margin amount for a signal path different from the signal path for which the characteristic degradation degree is obtained. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
An apparatus for calculating an amount of deterioration with time of an LSI, wherein a characteristic necessary for the operation of the LSI is a design target delay. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
The aging deterioration margin amount generation means uses the degree of characteristic deterioration as a derating factor corresponding to the deterioration of the characteristic over time, and at least the derating factor corresponding to each of manufacturing variation, power supply voltage fluctuation, and temperature fluctuation before the deterioration. A device for calculating an amount of deterioration over time of an LSI, wherein the maximum delay including the amount of deterioration over time is calculated by multiplying the above characteristic. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
A power supply voltage condition in the predetermined operating condition when the post-degradation characteristic generation means obtains the post-degradation characteristic;
The LSI characterized in that the pre-deterioration characteristic generation means and the post-deterioration characteristic generation means determine the pre-degradation characteristic and the power supply voltage condition for obtaining the post-degradation characteristic are different from each other. For calculating the amount of deterioration over time. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
The pre-degradation characteristic generation unit and the post-degradation characteristic generation unit are respectively the element in which the pre-deterioration characteristic and the post-degradation characteristic are the largest in the range of variations in the characteristics of the elements constituting the LSI. An apparatus for calculating a deterioration margin amount with time of an LSI, wherein the characteristic before deterioration and the characteristic after deterioration are obtained using the characteristic of An apparatus for calculating an amount of deterioration over time of an LSI according to claim 10,
A device for calculating an age deterioration margin of an LSI, wherein the characteristic before deterioration and the characteristic of the element having the largest characteristic after deterioration are characteristics with the lowest response of the element. An apparatus for calculating an amount of deterioration over time of an LSI according to claim 1,
A power supply voltage condition in the predetermined operating condition when the post-degradation characteristic generation means obtains the post-degradation characteristic;
The pre-degradation characteristic generation unit and the post-degradation characteristic generation unit are different from each other in power supply voltage conditions for obtaining the pre-degradation characteristic and the post-degradation characteristic.
The pre-degradation characteristic generation unit and the post-degradation characteristic generation unit are respectively the element in which the pre-deterioration characteristic and the post-degradation characteristic are the largest in the range of variations in the characteristics of the elements constituting the LSI. An apparatus for calculating a deterioration margin amount with time of an LSI, wherein the characteristic before deterioration and the characteristic after deterioration are obtained using the characteristic of

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