JPH08125041A - Nonvolatile semiconductor memory and its method for reading/writing - Google Patents

Abstract

PURPOSE: To separate common potential feed wiring from each memory cell without increasing an area occupied by the memory cell to enable electron to be implanted by FN tunneling from a channel. CONSTITUTION: A device comprises memory transistors 24 and 25 acting to accumulate electric charges between a control gate and a channel, a common potential feed wiring 26 supplying a common potential to a plurality of memory cell transistors 24 and 25, and transistors 27 and 28 for separation arranged between the memory transistors 24 and 25 and the common potential feed wiring 26. Gate electrodes 30 and 32 of the transistors 27 and 28 for separation are electrically connected to the common potential feed wiring 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device and a read / write method thereof, and more particularly to a layout structure of a circuit of a memory cell and a transistor.

[0002]

2. Description of the Related Art In recent years, with the spread and development of portable information terminal equipment, the need for a large capacity EEPROM as an external storage device has been increasing. EEPRO as an external storage device
When M is used, it is necessary to lower the rewriting operation voltage and improve the reliability. For that purpose, it has been reported that a method of carrying out electrons in and out of a floating gate and the like in writing and erasing data by FM tunneling using the entire channel of a memory transistor is effective (for example, Nikkei Microdevice 1).
May 992, p. 33).

[0003]

However, when the FM tunneling injection of electrons is performed using the entire surface of the channel, there are the following problems. As shown in FIG. 7, the electron injection into the memory transistor 4 is
The control gate 2 is set to a high potential of, for example, 15 V, and the bit line 1 is set to a low voltage of, for example, 0 V, while the electron transistor is not injected.
The bit line 3 has a high potential of 15 V, for example, to prevent erroneous writing. However, when the common potential supply wiring 6 is connected to the memory transistor 4, the low potential of the bit line 1 is applied to the diffusion layer of the transistor 5 via the common potential supply wiring 6, and electrons are also injected into the transistor 5. Will be done. Further, since the transistor 5 is turned on, the bit lines 1 and 3 set to different potentials are electrically connected.

As a technique for solving such a problem, there is a method of providing isolation transistors 7 and 8 between the memory transistors 4 and 5 and the common potential supply wiring 6, as shown in FIG. The isolation transistors 7 and 8 are controlled by the control gate 9.

However, in this case, as shown in the layout diagram of FIG. 9, there is a problem that the occupied area of the memory cell, particularly the long side L, is significantly increased. In FIG. 9, reference numeral 1
Reference numeral 1 denotes a contact for the bit line 1 shown in FIG. 8, and reference numeral 13 denotes a contact for the bit line 3 shown in FIG.

The present invention was devised in view of such conventional problems, and the common potential supply wiring is separated from each memory cell without increasing the occupied area of the memory cell, and the channel is formed. It is an object of the present invention to provide a non-volatile semiconductor memory device capable of injecting electrons by FN tunneling from a semiconductor device and a read / write method thereof.

[0007]

SUMMARY OF THE INVENTION According to the present invention, memory cells adjacent to each other are connected to each other so that a common potential supply line and a gate of a separation transistor are electrically connected to each other and the gate of the separation transistor is connected to the same common potential supply line. The solution is to let them share it.

Specifically, the nonvolatile semiconductor memory device according to the present invention includes a memory cell transistor having a function of accumulating charges between a control gate and a channel,
A common potential supply wiring for supplying a common potential to a plurality of memory cell transistors; and a separation transistor arranged between the memory cell transistor and the common potential supply wiring, wherein a gate electrode of the separation transistor is It is electrically connected to the common potential supply wiring.

The control gate of the memory cell transistor can be used as a selected word line, and one memory cell can be composed of two transistors. A selection transistor may be provided between the memory cell transistor and the bit line to configure one memory cell with three transistors.

The gate electrode of the isolation transistor is
It can be arranged in parallel with the selected word line and can be used as a wiring for supplying a common potential to each memory cell. The gate electrode of the isolation transistor can be formed of polycide, for example.

A part of both sides of the gate electrode of the isolation transistor may be laminated so as to overlap a part of the control gate of the memory cell transistor with an interlayer insulating film interposed therebetween. The gate electrode of the isolation transistor is
It is arranged above or below the control gate of the memory cell transistor.

According to the read / write method of the non-volatile semiconductor memory device of the present invention, the isolation transistor is
And a gate electrode of the common potential supply wiring and the isolation transistor is set to a high level at the time of reading and is set to a low level at the time of writing.

The separating transistor is a P-type MO.
It is also possible to use an S-transistor and set the common potential supply wiring and the gate electrode of the separation transistor to a low level during reading and to a high level during writing.

[0014]

According to the present invention, the common potential supply wiring and the gate wiring of the separation transistor are electrically connected to each other so that the gate of the separation transistor is shared between the memory cells adjacent to each other connected to the same common power supply wiring. This allows a layout to be performed, and thus a significant reduction in memory cell area as compared with the conventional method.

Furthermore, since the gate of the isolation transistor can be used as a common power supply wiring, the wiring resistance can be reduced and the data reading speed can be increased. Furthermore, a part of both sides of the gate electrode of the isolation transistor is
By stacking the interlayer insulating film so as to overlap a part of the control gate of the memory cell transistor, the area of the memory cell can be further reduced and high integration can be achieved.

[0016]

1 is a circuit diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, the non-volatile semiconductor memory device according to the present embodiment is a NOR type memory device, and each memory cell M ₁ and M ₂ includes a memory cell transistor 24 and 25 and a separation transistor 2.
7 and 28. Although only two memory cells M ₁ and M ₂ are shown in FIG. 1, many memory cells are arranged in a matrix in an actual memory device.

The memory cell transistors 24 and 25 are not particularly limited in structure as long as they have a function of accumulating charges between the control gate 22 and the channel, but in the present embodiment, a transistor having a floating gate. Will be described as an example.

The gates of the memory cell transistors 24 and 25 are connected to the control gate 22. The drains of the memory cell transistors 24 and 25 are connected to the bit lines 21 and 23, respectively. The sources of the memory cell transistors 24 and 25 are connected to one source / drain of the separating transistors 27 and 28, respectively, and the other source / drain of the separating transistors 27 and 28 are connected to the common potential supply wiring 26. It is connected.

In this embodiment, the isolation transistor 27,
The gate electrodes 30 and 32 of 28 are common potential supply wiring 26
It is conducting. In addition, in this embodiment, the transistor 2
Reference numerals 4, 25, 27 and 28 are N-type MOS transistors. When injecting electrons into the floating gate of one of the memory transistors 24 for data writing, the potential of the common potential supply wiring 26 is set to a low level equal to or lower than the potential of the bit line 21 to simultaneously lower the gate electrode 30. Then, the isolation transistor is turned off and the memory cell transistor 24 is isolated from the common potential supply wiring 26. For example, the common potential supply wiring 26
By setting the bit line 21 to 0 V and the control gate 22 to 15 V, electrons can be injected from the bit line 21 to the floating gate of the memory transistor 24 through the channel. On the other hand, the bit line 23 of the memory transistor 25 that does not inject electrons is, for example, 15V.
The high potential prevents the erroneous writing. Due to the action of the isolation transistors 27 and 28, the write voltage of the adjacent memory cell transistor 24 does not adversely affect the memory cell transistor 25 which is not written.

At the time of reading data, the common potential supply wiring 26 is set to the power supply voltage to separate the transistor 2 for separation.
7, 28 are turned on, and each memory cell M ₁ , M ₂ has
A potential obtained by subtracting the thresholds of the isolation transistors 27 and 28 from the power supply voltage is supplied. The control gate 22 which is a word line is set to a high potential, and for example, the bit line 2
The data stored in the memory transistors 24 and 25 can be read by setting the potentials of 1 and 23 to the ground potential and detecting the current flowing therein.

When the PMOS is used as the memory transistors 24 and 25 and the isolation transistors 27 and 28, the above-mentioned operation of turning over is necessary. That is, the common potential supply wiring 26 is set to a high level when writing data, and the common potential supply wiring 26 is set to a low level when reading data.

FIG. 2 shows a memory cell M having the circuit structure shown in FIG.
A specific layout diagram of ₁ and M ₂ is shown. As shown in FIG. 2, element isolation regions (LOCOS) 40 are formed in a predetermined pattern on the surface of the semiconductor substrate. LOCOS40
On the surface of the semiconductor substrate surrounded by, active regions to be the source / drain region impurity diffusion layers 42 and 44 are formed, and a gate insulating film is formed thereon. On the gate insulating film and the LOCOS 40, the control gate 22 and the shared wiring 26a are formed substantially parallel to each other in a predetermined pattern substantially orthogonal to the impurity diffusion layers 42 and 44.
Below the control gate 22, floating gates 46 and 48 are arranged.

In this embodiment, the gate electrodes 30 and 32 of the isolation transistors 27 and 28 shown in FIG. 1 and the common potential supply wiring 26 are combined into a single shared wiring 26a shown in FIG. The shared wiring 26a and the source / drain region diffusion layers of the isolation transistors 27 and 28 are connected to each other through a contact hole 34.

In the non-volatile semiconductor memory device according to this embodiment, the long side length L of the memory cell is shortened, which makes it possible to greatly reduce the cell area. Further, in this structure, the common potential supply wiring is thicker than in the conventional structure of FIG. Furthermore, since polycide or the like can be used for the shared wiring 26a, it is possible to reduce the parasitic resistance when the potential is supplied to the memory cell at the time of reading data, and to increase the reading speed.

The two-transistor type cell in which the control gate of the memory cell transistor is used as a word selection line has been described above, but the present invention is also applicable to a three-transistor type storage element having a selection transistor in addition to the memory cell transistor. Can be applied.

FIG. 3 shows a circuit of a memory cell according to the second embodiment using three transistors. In addition to the memory cell transistors 24 and 25, isolation transistors 27 and 28 and word selection transistors 50 and 52 are provided on both sides thereof. The gate electrodes of the word selection transistors 50 and 52 are connected to the word line 54, and are driven and controlled by the word line 54.

In such a three-transistor structure, even if the memory cell transistor 24 is depleted by, for example, over-erasing, no extra current flows through the bit line 21 when it is not selected. That is, there is an advantage that leakage noise at the time of reading through the non-selected cell can be prevented. Further, since the non-selected cell and the bit line can be easily separated, it is difficult to receive the gate disturb at the time of writing the data.

Further, the present invention is not limited to the floating gate type memory element in which charges are stored in the floating gate under the control gate of the memory cell transistor, and the MONO in which charges are stored in the interface between SiN and SiO _2.
The same applies to the S type or the MNOS type. Further, it can be applied to a memory cell transistor using a ferroelectric ceramic film as an insulating film.

Further, by forming the gate electrodes of the isolation transistor and the memory cell transistor into a laminated structure, the memory cell area can be further reduced. 4 and 5 are sectional views showing an example of a laminated structure of a two-transistor type memory cell using a floating gate type transistor. In the embodiment shown in FIG. 4, a gate insulating film, floating gates 46b and 48b, an intermediate insulating film, a control gate 22b, an interlayer insulating film 58, a shared wiring 26b, an interlayer insulating film 58 and a bit line 23b are formed on a semiconductor substrate 56. But,
The layers are laminated in the sectional structure shown in FIG.

As the semiconductor substrate 56, for example, a single crystal silicon substrate is used. A silicon oxide film is used as the gate insulating film. Floating gate 46
b and 48b are formed of, for example, a polysilicon film.
The interlayer insulating film 58 is, for example, a silicon oxide film or PSG.
It is composed of a film, a BPSG film and the like. The shared wiring 26b is
For example, it is composed of a polycide film which is a laminated film of a polysilicon film and a silicide film. Bit line 23b is formed of a metal wiring layer such as an aluminum alloy.

On the surface layer of the semiconductor substrate 56, source / drain region impurity diffusion layers 44b are formed in self-alignment with the control gate 22b. The floating gate 48b and the control gate 22b form a memory cell transistor 25b. The floating gate 46b and the control gate 22b form another adjacent memory cell transistor 24b. The shared wiring 26b also serves as a common potential supply wiring and a gate electrode of the separation transistor 60. The bit line 23b passes through the contact hole 38b formed in the inter-layer insulating film 58, and the one diffusion layer 4 of the memory cell transistor 25b.
4b is connected.

In this embodiment, a part of the shared wiring 26b is
By adopting a structure in which the memory cell transistors 24b and 25b are stacked on the control gate 22b via the interlayer insulating film 58, the degree of integration is improved. In the embodiment shown in FIG. 5, on the semiconductor substrate 56, the gate insulating film, the shared wiring 26c, the floating gate 46c,
48c, the intermediate insulating film, the control gate 22c, the interlayer insulating film 58c, and the bit line 23c are laminated in the sectional structure shown in FIG. Semiconductor substrate 56, gate insulating film, shared wiring 26c, floating gates 46c, 4
Materials of 8c, the intermediate insulating film, the control gate 22c, the interlayer insulating film 58c, and the bit line 23c are the same as those in the example shown in FIG.

On the surface layer of the semiconductor substrate 56, source / drain region impurity diffusion layers 44c are formed in self-alignment with the control gates 22c. The floating gate 48c and the control gate 22c form a memory cell transistor 25c. The floating gate 46c and the control gate 22c constitute another adjacent memory cell transistor 24c. The shared wiring 26c also serves as the common potential supply wiring and the gate electrode of the separation transistor 60c. The bit line 23c is
Contact hole 38c formed in the interlayer insulating film 58c
Through, it is connected to one diffusion layer 44c of the memory cell transistor 25c.

In this embodiment, the memory cell transistor 2
4c and 25c floating gates 46c and 48c and a part of the control gate 22c are connected to the shared wiring 26.
The degree of integration is improved by adopting a structure in which it is laminated on c through the interlayer insulating film 58c.

FIG. 6 shows an example of a laminated structure of a three-transistor type memory cell using the MONOS type. As shown in FIG. 6, a gate insulating film is formed on the semiconductor substrate 56,
A word line 54d of the word selection transistor 52d and a shared wiring 26d are formed thereon. The shared wiring 26d serves both as the gate electrode of the separation transistor 60d and the common potential supply wiring. Selection transistor 52d
The ONO film 62 is used as a gate insulating film between the word line 54d and the gate electrode of the separation transistor 60d.
A memory cell transistor 25d having a control gate 22d laminated thereon is arranged thereon.

The shared wiring 26d which also serves as the gate electrode of the isolation transistor 60d is formed using the same polycide layer as the word line 54d. Memory transistor 25
The control gate 22d of d is laminated thereon, and its gate length is the same as that of the word line 54d and the shared wiring 60.
It is determined in a self-aligned manner with d. ONO film 6
Reference numeral ₂ is a thin film in which SiO ₂ , SiN, and SiO ₂ are sequentially stacked, and charges can be stored in the thin film.

On the control gate 22d, a bit line 23d made of a metal wiring layer such as an aluminum alloy is laminated via an interlayer insulating film 58d. The bit line 23d is connected to one of the source / drain region impurity diffusion layers 44d of the selection transistor 52d through a contact hole 38d formed in the interlayer insulating film 58d.

In this embodiment, the control gate 22d
Since both sides of the above are partially overlapped with the word line 54d and the shared wiring 26d with the interlayer insulating film 58d interposed therebetween, the degree of integration can be improved. In addition,
The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention.

[0039]

As described above, according to the present invention, the common potential supply wiring and the gate wiring of the separation transistor are electrically connected to each other so that the gates of the separation transistors are connected to the same common power supply wiring. Enables a layout to be shared between adjacent memory cells connected to
Therefore, it is possible to significantly reduce the memory cell area as compared with the conventional method.

Furthermore, since the gate of the separation transistor can be used as a common power supply wiring, the wiring resistance can be reduced and the data reading speed can be increased. Furthermore, a part of both sides of the gate electrode of the isolation transistor is
By stacking the interlayer insulating film so as to overlap a part of the control gate of the memory cell transistor, the area of the memory cell can be further reduced and high integration can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit example of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a plan view showing an example of the layout configuration of the nonvolatile semiconductor memory device according to the embodiment shown in FIG.

FIG. 3 is a diagram showing a circuit example of a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a nonvolatile semiconductor memory device according to still another embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a nonvolatile semiconductor memory device according to still another embodiment of the present invention.

FIG. 7 is a circuit diagram of a nonvolatile semiconductor memory device according to a conventional example.

FIG. 8 is a circuit diagram of a non-volatile semiconductor memory device according to another conventional example.

9 is a plan view of relevant parts showing a layout configuration of the nonvolatile semiconductor memory device shown in FIG. 8;

[Explanation of symbols]

 21, 23 ... Bit line 22 ... Control gate 24, 25 ... Memory cell transistor 26 ... Common potential supply wiring 27, 28 ... Separation transistor 30, 32 ... Gate electrode 34, 36, 38 ... Contact hole 40 ... LOCOS 42, 44 Source / drain region impurity diffusion layers 46, 48 ... Floating gates 50, 52 ... Word selection transistor 54 ... Word line 56 ... Semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 16/02 H01L 21/76 21/8246 27/112 H01L 21/76 M 27/10 433

Claims (8)

[Claims] 1. A memory cell transistor having a function of accumulating charges between a control gate and a channel, a common potential supply line for supplying a common potential to a plurality of memory cell transistors, the memory cell transistor and the common potential. A non-volatile semiconductor memory device, comprising: a separation transistor disposed between a supply wiring and a gate electrode of the separation transistor electrically connected to the common potential supply wiring. 2. The data read / write method for a nonvolatile semiconductor memory device according to claim 1, wherein the separation transistor is an N-type MOS transistor, and the common potential supply line and the separation transistor are used at the time of reading. The data read / write method of the non-volatile semiconductor memory device is characterized in that the gate electrode is set to a high level and set to a low level during writing. 3. The data read / write method for a non-volatile semiconductor memory device according to claim 1, wherein the separation transistor is a P-type MOS transistor, and the common potential supply wiring and the gate of the separation transistor are arranged at the time of reading. A data read / write method for a non-volatile semiconductor memory device, wherein the electrodes are set to a low level and the electrodes are set to a high level during writing. 4. The non-volatile semiconductor memory device according to claim 1, wherein the control gate of the memory cell transistor is used as a selected word line, and one memory cell is composed of two transistors. 5. The non-volatile semiconductor memory device according to claim 1, wherein a selection transistor is provided between the memory cell transistor and a bit line, and one memory cell is composed of three transistors. . 6. The non-volatile semiconductor memory device according to claim 1, wherein a gate electrode of the isolation transistor is arranged in parallel with a selected word line, and a common potential is applied to each memory cell. A non-volatile semiconductor memory device used as a supply wiring. 7. The non-volatile semiconductor memory device according to claim 6, wherein the gate electrode of the isolation transistor is formed of polycide. 8. The non-volatile semiconductor memory device according to claim 1, wherein a part of both sides of the gate electrode of the isolation transistor is
A non-volatile semiconductor memory device, which is laminated so as to overlap a part of a control gate of a memory cell transistor via an interlayer insulating film.