JPH08124940A - Field effect transistor - Google Patents

Abstract

PURPOSE: To enhance breakdown strength of an FET having heterojunction structure fabricated on a compound semiconductor substrate. CONSTITUTION: A channel layer 6 is formed on a semiinsulating substrate 1 and an insulation layer, composed of a compound semiconductor different from the channel layer 6, is formed thereon to produce an FET 3 having heterojunction structure. The insulation layer 7 comprises an insulation layer 7a of AlGaAs, an insulation layer 7b of GaAs, and an insulation layer 7c of AlGaAs deposited sequentially from below.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect transistor technology, and more particularly to a field effect transistor (Field Effe) having a heterojunction structure in which a compound semiconductor different from the compound semiconductor substrate is laminated on the compound semiconductor substrate.
ct Transistor; hereinafter referred to as MES • FET), and is a technology effective.

[0002]

2. Description of the Related Art As the information-oriented society advances, it is required to develop a circuit capable of processing high-density information at high speed. An FET using a compound semiconductor substrate typified by gallium arsenide (GaAs) or the like is drawing attention as an element that meets the requirements.

This is an FET using a GaAs substrate or the like.
However, as compared with the case where a semiconductor substrate of a single element such as silicon (Si) is used, it has excellent advantages such as large carrier mobility and high speed, large substrate resistance and small stray capacitance. Because they are doing it.

By the way, as an improved form of such MES-FET, a structure in which an insulating layer made of a different kind of compound semiconductor is sandwiched between a Schottky gate electrode and a channel layer having a high impurity concentration in a compound semiconductor substrate is adopted. There is an FET with a heterojunction structure.

According to the technique examined by the present inventor for the FET of this structure, the Schottky gate electrode and the GaA
From the viewpoint of improving the breakdown voltage, for example, an aluminum (Al) GaAs layer and GaA
There is a FET having a heterojunction structure in which an insulating layer formed by stacking an s layer in order from the lower layer is interposed.

In this structure, the band gap of the AlGaAs layer is wider than the band gap of the GaAs layer, so that electrons passing through the Schottky barrier formed in the contact portion between the GaAs layer and the Schottky gate electrode are crossed. It is possible to prevent the movement, which improves the breakdown voltage.

Regarding the FET of this type, for example, "Ohm Co., Ltd.," issued on November 30, 1984, "L
SI Handbook "P725-P728,
FETs having various heterojunction structures formed on a compound semiconductor substrate have been described.

[0008]

However, in the above FET technology in which a double heterojunction layer of, for example, an AlGaAs layer and a GaAs layer is interposed between the gate electrode and the GaAs channel layer, in the forbidden band of the AlGaAs layer, Since there are many deep energy levels, electrons are AlG
The present inventor has found that as a result of moving to the channel side via a deep energy level in the aAs layer, a leak current flows, which hinders improvement of the breakdown voltage of the FET.

An object of the present invention is to provide a technique capable of improving the breakdown voltage of an FET having a heterojunction structure formed on a compound semiconductor substrate.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the FET of the present invention has a heterojunction structure in which an insulating layer made of a compound semiconductor different from the channel layer is laminated on a channel layer made of a compound semiconductor formed on a compound semiconductor substrate. A field effect transistor, wherein the insulating layer includes a first insulating layer,
A second insulating layer sandwiched thereby, the first insulating layer is made of a compound semiconductor having a band gap wider than that of the second insulating layer, and the second insulating layer has a deep energy level number. It is composed of less compound semiconductor than the first insulating layer.

Another FET of the present invention is a heterojunction in which an insulating layer made of a compound semiconductor different from the channel layer is laminated on a channel layer made of a compound semiconductor layer formed on a compound semiconductor substrate. A field effect transistor having a structure, wherein the insulating layer is provided with an insulating layer made of an indirect transition type compound semiconductor.

Further, in another FET of the present invention, the insulating layer made of the indirect transition type compound semiconductor is AlAs.

[0015]

According to the above-mentioned FET of the present invention, the movement of electrons across the Schottky barrier is blocked by the first insulating layer having a wide forbidden band, while the movement of electrons through the deep energy level is deep. It can be suppressed by the second insulating layer having a small number of units.

According to the other FET of the present invention described above, by providing an insulating layer made of an indirect transition type compound semiconductor in the insulating layer on the channel layer, the energy of hot electrons can be gradually released. As a result, avalanche breakdown can be prevented.

Further, according to the above-mentioned other FET of the present invention, the insulating layer made of the indirect transition type compound semiconductor is Al.
By using As, the width of the forbidden band can be made wider than in the case of AlGaAs, so that the Schottky barrier can be made higher and the energy of hot electrons can be released little by little, so that avalanche breakdown can be prevented. can do.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a field effect transistor which is an embodiment of the present invention, FIG. 2 is an energy band diagram of a main part of the field effect transistor of FIG. 1, and FIG. Band diagram of the main part of a field effect transistor formed of a layer / AlGaAs layer, FIGS.
Reference numeral 0 is a cross-sectional view during a manufacturing process of the field effect transistor of FIG.

As shown in FIG. 1, a semi-insulating substrate (compound semiconductor substrate) 1 is made of, for example, GaAs, and an FET 3 having a heterojunction structure is formed in an element region surrounded by an element isolation groove 2. ing. Although not shown, a plurality of FETs 3 and other elements are formed on the semi-insulating substrate 1 to thereby form an analog IC for communication equipment.
A predetermined semiconductor integrated circuit device such as (Integrated Circuit) is configured.

The FET 3 has a source region 5s, a drain region 5d and a channel layer 6 formed on the buffer layer 4.
An insulating layer 7 formed on the channel layer 6, and an insulating layer 7
It has a gate electrode 9 formed thereon with a cap layer 8 interposed therebetween.

The buffer layer 4 is made of, for example, p-type GaAs, and the source region 5s, the drain region 5d and the channel layer 6 are made of, for example, n-type GaAs. The thickness of the channel layer 6 is, for example, about 15 nm.

The insulating layer 7 is formed by depositing insulating layers 7a to 7c in order from the lower layer. Bottom insulating layer (first
The insulating layer) 7a is made of, for example, AlGaAs and has a thickness of, for example, about 4 nm. The upper insulating layer (second insulating layer) 7b is made of, for example, GaAs and has a thickness of, for example, about 3 nm. The upper insulating layer (first
The insulating layer) 7c is made of, for example, AlGaAs and has a thickness of, for example, about 4 nm.

That is, in the first embodiment, the insulating layer 7 is formed of, for example, AlGaAs layer / GaAs layer / AlGaA.
An s-layer heterojunction layer is formed. This can prevent electrons that have exceeded the Schottky barrier level from moving to the channel layer 6 side.
It is possible to prevent the electrons from moving to the channel layer 6 side via the deep energy level. This will be described with reference to FIGS. 2 and 3.

FIG. 2 shows an energy band diagram of the insulating layer 7 and its vicinity in the case of the first embodiment. Further, FIG. 3 shows an energy band diagram of the insulating layer and its vicinity when the insulating layer is a GaAs layer / AlGaAs layer.

In the case of FIG. 2, between the insulating layers 7a and 7c having a wide bandgap, the insulating layer 7 having a narrower bandgap and a smaller deep energy level DL number.
By interposing b, the Schottky barrier level VR
It is possible to prevent the phenomenon that the electrons e that have passed over the distance move to the channel layer side by the insulating layer 7c having a wide bandgap, and the electrons e move to the channel layer side through the deep energy level DL. This phenomenon can be suppressed by the insulating layer 7b.

On the other hand, in the case of FIG. 3, movement of the electrons e exceeding the Schottky barrier potential VR is caused by AlG in the insulating layer.
AlGaA, which can be blocked by the aAs layer
It can be seen that electrons move to the channel layer side via the deep energy levels DL existing in large numbers in the s layer.

In FIG. 1, the cap layer 8 is, for example, G
It consists of aAs. The gate electrode 9 is made of, for example, tungsten silicide, and an insulating film 10 made of, for example, silicon nitride is formed on the upper surface thereof.

The side surface of the gate electrode 9 and the surface of the insulating film 10 are covered with an insulating film 11 made of, for example, a nitride film. In addition, the gate electrode 9 and the insulating film 1
On the side surface of 0, the side wall 12 is formed through the insulating film 11.
Are formed.

An insulating film 11 made of, for example, a nitride film is deposited on the element isolation groove 2. An interlayer insulating film 14 is deposited on the insulating film 11 via an insulating film 13 made of, for example, silicon oxide.

A connection hole 15 is formed in the interlayer insulating film 14 so that the source region 5s and the drain region 5d are exposed. In the connection hole 15, the source electrode 16s is formed.
And a drain electrode 16d are formed respectively. The source electrode 16s and the drain electrode 16d are made of, for example, a laminated metal of gold (Au) / tungsten (W) / nickel (Ni) / gold germanium (AuGe) alloy.

A gate lead electrode 17 is formed on the gate electrode 9 via an insulating film 11. The gate lead electrode 17 is made of Au, for example, and is electrically connected to the gate electrode 9 although not shown.

Next, a method of manufacturing the FET 3 according to the first embodiment will be described with reference to FIGS. 1 and 4 to 10.

First, as shown in FIG. 4, on a semi-insulating substrate 1 made of GaAs, a buffer layer 4 made of p-type GaAs or the like, a channel layer 6 made of n-type GaAs or the like, undoped AlGaAs or the like is formed. Insulating layer 7a, GaA
An insulating layer 7b made of s or the like, an insulating layer 7c made of undoped AlGaAs or the like and a cap layer 8 made of GaAs or the like are sequentially grown by a molecular beam epitaxy (MBE) method, and then, for example, tungsten silicide is formed on the cap layer 8. A conductor film 18 made of, for example, is deposited by the sputtering method.

Subsequently, as shown in FIG. 5, the conductor film 18 made of tungsten silicide or the like is patterned by a normal photolithography technique.
After forming the conductor film pattern 18a, the conductor film pattern 18a is used as an etching mask to etch the cap layer 8, the insulating layers 7a to 7c, the channel layer 6, the buffer layer 4 and the upper portion of the semi-insulating substrate 1, thereby separating elements. The groove 2 is formed.

After the conductor film pattern 18a is removed by etching, as shown in FIG. 6, a conductor film 19 made of tungsten silicide or the like is deposited on the entire surface of the semi-insulating substrate 1 by a sputtering method or the like, and the upper surface thereof is further deposited. Then, an insulating film 10 made of silicon nitride or the like is sequentially deposited by a plasma CVD method or the like.

Then, as shown in FIG. 7, the gate electrode 9 is formed by sequentially etching the insulating film 10 made of silicon nitride and the conductor film 19 made of tungsten silicide by using the photoresist 20a as a mask, and then, The resist 20a is removed by etching.

Subsequently, as shown in FIG. 8, an insulating film 11 made of nitride or the like is deposited on the entire surface of the semi-insulating substrate 1 by plasma CVD or the like.

After that, as shown in FIG. 9, an insulating film made of nitride or the like is deposited on the entire surface of the semi-insulating substrate 1 by the plasma CVD method, and then the insulating film is etched back, whereby the gate electrode 9 is formed. Side wall 12
To form.

Next, as shown in FIG. 9, an insulating film 13 made of silicon oxide is formed on the entire surface of the semi-insulating substrate 1 by CVD.
After being deposited by the method or the like, the insulating film 13 and the insulating film 11 therebelow are sequentially etched using the photoresist 20b as an etching mask to expose a part of the upper surface of the cap layer 8.

Then, after removing the photoresist 20b by etching, as shown in FIG. 10, the source region 5s, is formed on a part of the cap layer 8 and the insulating layer 7 using the insulating film 13 made of silicon oxide or the like as a mask. Drain region 5
d is selectively epitaxially grown.

After that, as shown in FIG. 1, an interlayer insulating film 14 is deposited on the entire surface of the semi-insulating substrate 1 by the CVD method or the like, and a part of the interlayer insulating film 14 is removed by etching to remove the gate. After exposing a part of the upper surface of the electrode 9, a gate extraction electrode 17 made of, for example, Au is formed on the gate electrode 9.

Finally, after forming the connection hole 15 in the interlayer insulating film 14 on the source region 5s and the drain region 5d,
The FET 3 having the heterojunction is manufactured by forming the source electrode 16s and the drain electrode 16d made of Au / W / Ni / AuGe or the like, for example.

As described above, according to the first embodiment, the following effects can be obtained.

(1). For the insulating layer 7 below the gate electrode 9 of the FET 3, for example, AlGaAs layer / GaAs layer / A
By providing the hetero junction layer of the 1GaAs layer, the movement of electrons across the Schottky barrier is blocked by the insulating layers 7c and 7a having a wide forbidden band, while the movement of electrons through the deep energy level is deep energy level. This can be suppressed by the insulating layer 7b having a small amount. Therefore,
FE having heterojunction formed on semi-insulating substrate 1
Since the Schottky breakdown voltage of T3 can be improved, the yield and reliability of the FET3 can be improved.

(Embodiment 2) FIG. 11 is a sectional view of a field effect transistor which is another embodiment of the present invention, and FIG. 12 is FIG.
FIG. 3 is an energy band diagram of a main part of the field effect transistor of FIG.

In the second embodiment, FIG. 11 and FIG.
As shown in FIG. 2, an insulating layer 7d is formed in the lower insulating layer of the gate electrode 9 of the FET 3 (FIG. 11) instead of the insulating layers 7a to 7c of the first embodiment. The insulating layer 7d is made of, for example, an indirect transition type compound semiconductor such as AlAs, and is formed by, for example, the MBE method.

As a result, in the second embodiment, Al
AlAs with a wider forbidden band instead of GaAs
Since the insulating layer 7d is made of, the Schottky barrier can be increased.

Since the insulating layer is changed from the direct transition type to the indirect transition type, the energy of hot electrons can be released little by little, so that avalanche breakdown can be prevented.

Therefore, the Schottky withstand voltage of the FET 3 having the heterojunction formed on the semi-insulating substrate 1 can be improved, and the yield and reliability of the FET 3 can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments 1 and 2, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first and second embodiments, the case where the insulating layer is formed by the MBE method has been described, but the present invention is not limited to this. For example, the insulating layer is formed by the metal organic chemical vapor deposition (MOCVD) method or the like. May be.

In the above description, the case where the invention made by the present inventor is mainly applied to the FET used in the analog IC for the communication equipment which is the field of use in the background has been described, but the invention is not limited to this. It is applicable and can be applied to other FETs such as FETs forming a semiconductor integrated circuit device for logic circuits and memory circuits.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) According to the FET of the present invention, the movement of electrons across the Schottky barrier is blocked by the first insulating layer having a wide forbidden band, while the movement of electrons through a deep energy level is deep. This can be suppressed by the second insulating layer having a low energy level. Therefore, it is possible to improve the Schottky withstand voltage of the FET having the heterojunction formed on the compound semiconductor substrate.
It is possible to improve the yield and reliability.

(2). According to another FET of the present invention, by providing an insulating layer made of an indirect transition type compound semiconductor in the insulating layer on the channel layer, it is possible to gradually release hot electron energy. As a result, avalanche breakdown can be prevented. Therefore, the Schottky breakdown voltage of the FET having the heterojunction formed on the compound semiconductor substrate can be improved, and the yield and reliability of the FET can be improved.

(3). According to another FET of the present invention, since the insulating layer made of the indirect transition type compound semiconductor is made of AlAs, the band gap can be made wider than that of AlGaAs. It is possible to raise the Schottky barrier, release the energy of hot electrons little by little, and prevent avalanche breakdown. Therefore, the Schottky breakdown voltage of the FET having the heterojunction formed on the compound semiconductor substrate can be improved, and the yield and reliability of the FET can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a field effect transistor that is an embodiment of the present invention.

FIG. 2 is an energy band diagram of a main part of the field effect transistor of FIG.

FIG. 3 is an energy band diagram of a main part of a field effect transistor in which an insulating film is formed of a GaAs layer / AlGaAs layer.

FIG. 4 is a cross-sectional view during a manufacturing process of the field effect transistor of FIG.

5 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 4;

6 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 5;

7 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 6;

8 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 7;

9 is a sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 8;

10 is a cross-sectional view of the field-effect transistor of FIG. 1 during a manufacturing step following that of FIG. 9;

FIG. 11 is a cross-sectional view of a field effect transistor which is another embodiment of the present invention.

12 is an energy band diagram of a main part of the field effect transistor of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate (compound semiconductor substrate) 2 Element isolation groove 3 Field effect transistor 4 Buffer layer 5s Source region 5d Drain region 6 Channel layer 7 Insulating layers 7a, 7c Insulating layer (1st insulating layer) 7b Insulating layer (2nd) Insulating layer) 7d Insulating layer 8 Cap layer 9 Gate electrode 10 Insulating film 11 Insulating film 12 Sidewall 13 Insulating film 14 Interlayer insulating film 15 Connection hole 16s Source electrode 16d Drain electrode 17 Gate extraction electrode 18 Conductive film 18a Conductive film pattern 19 Conductor Films 20a, 20b Photoresist DL Deep energy level e Electron VR Schottky barrier level

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Munetoshi Fukui 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center

Claims (5)

[Claims] 1. A field effect transistor having a heterojunction structure in which an insulating layer made of a compound semiconductor different from the channel layer is laminated on a channel layer made of a compound semiconductor formed on a compound semiconductor substrate. A first insulating layer and a second insulating layer sandwiched between the first insulating layer and the second insulating layer having a forbidden band width of the second insulating layer;
A field effect transistor comprising a compound semiconductor wider than an insulating layer, and the second insulating layer made of a compound semiconductor having a deep energy level number smaller than that of the first insulating layer. 2. The field effect transistor according to claim 1, wherein the first insulating layer is made of aluminum gallium arsenide, and the second insulating layer is made of gallium arsenide. 3. A field effect transistor having a heterojunction structure in which an insulating layer made of a compound semiconductor different from the channel layer is laminated on a channel layer made of a compound semiconductor layer formed on a compound semiconductor substrate. hand,
A field effect transistor, wherein an insulating layer made of an indirect transition type compound semiconductor is provided on the insulating layer. 4. The field effect transistor according to claim 3, wherein the insulating layer made of the indirect transition type compound semiconductor is aluminum arsenic. 5. The field effect transistor according to claim 2 or 4, wherein the channel layer is made of n-type gallium arsenide, and the compound semiconductor substrate is made of gallium arsenide.