JPH08123787A - Arithmetic circuit and signal processor using the same - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To provide an arithmetic circuit that requires a short time for moving average arithmetic processing and a video signal processor that can efficiently perform video signal processing by using this arithmetic circuit. To do. [Structure] Each clock cycle, a working buffer or an input / output buffer is accessed, and pixel data x _k
From input terminal X to adder circuit 304 and register 400
Read in. The register 400 selects the pixel data x _k−1 input in the previous clock cycle from the selector circuit 3
It outputs to the selector circuit 402 via 08. The cumulative addition circuit 304 adds the pixel data x _k and x _k−1 and outputs the result from the output terminal A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for performing numerical calculation, and in particular, an arithmetic circuit used in a computer system for image processing and graphics processing, and
The present invention relates to a signal processor using this arithmetic circuit and suitable for encoding / decoding a video signal.

[0002]

2. Description of the Related Art In recent years, CCITT H. 261 Recommendation and M
There have been proposed many signal processors for video signal processing devices that perform compression encoding processing or decompression decoding processing of video signals in accordance with standards such as PEG. The signal processor is a discrete cosine transform (DCT) process, a discrete cosine inverse transform (IDCT) process, a quantization process, an inverse quantization process, a motion vector detection process, for pixel data included in a digital format video signal. The configuration is suitable for sequentially executing the element processing necessary for the video signal processing such as the motion compensation processing, the image data addition processing and the subtraction processing.

[0003]

In the video signal processing device, in addition to the element processing such as the discrete cosine transform processing described above, the average value (moving average value) of the adjacent pixel data is calculated for the motion compensation processing. Pixels located in the middle of these pixel data (virtual pixels) that are sequentially calculated and the calculated average value
It is necessary to treat the pixel data as the pixel data (virtual pixel data) and perform the process of interpolating the image data.

The moving average value calculation process (moving average calculation process) needs to be repeated for the number of pixel data (virtual pixel data) of virtual pixels to be calculated. Therefore, if the time required for one moving average calculation process becomes long even for one clock cycle (operation period), a large amount of time will be spent in the entire process.

For example, in the case where the processing time is increased by one clock cycle for one moving average calculation process,
If moving average calculation processing is performed to generate virtual pixel data for one macroblock (16 × 16; 256),
Since it is necessary to repeat the process of calculating 16 virtual pixel data from 17 pixel data 16 times, the processing time becomes 256 clock cycles longer. Moreover, the control sequence of the control unit for controlling the moving average calculation process is increased by 256 steps, which complicates the configuration of the control unit. As described above, if the processing time of the moving average calculation process becomes long, not only the performance of the motion compensation process deteriorates, but also the configuration of the video processing device or the signal processor used for this becomes complicated. .

The present invention has been made in view of the above-mentioned problems of the prior art. The time required for the moving average calculation processing is short, and the cumulative addition processing required for the video signal processing is performed by using the same circuit. It is an object to provide an arithmetic circuit that can be performed. Another object of the present invention is to provide a signal processor that uses the above arithmetic circuit and can efficiently perform video signal processing.

[0007]

In order to achieve the above object, a first arithmetic circuit of the present invention has a first input terminal and a second input terminal to which input data is applied. A cumulative addition circuit that adds and holds the data input from the input terminal, a cumulative addition result register that holds the output data of the cumulative addition circuit, and an input that holds the input data input in response to the operation clock. And a first selector circuit that selects either the output data of the cumulative addition result register or the output data of the input register and applies the selected data to the first input terminal of the cumulative addition circuit. When executing the operation, the first selector circuit outputs the output data of the input register to the first addition circuit of the cumulative addition circuit.
When applying the cumulative addition operation to the input terminal of
The first selector circuit applies the output data of the cumulative addition result register to the first input terminal of the cumulative addition circuit.

A second arithmetic circuit according to the present invention is characterized in that a negative number generation circuit for generating a negative number of the input data, and one of the output data of the negative number generation circuit and the input data are selected to select the first addition circuit of the cumulative addition circuit. A second selector circuit for applying the input data to the second input terminal, the second selector circuit, when performing a moving addition operation and a cumulative addition operation, the second selector circuit outputs the input data to the second addition circuit of the cumulative addition circuit. When performing the cumulative subtraction operation by applying the negative number to the second input terminal of the cumulative addition circuit, the second selector circuit applies the negative number to the second input terminal of the cumulative addition circuit.

Preferably, when the moving addition operation and the cumulative addition operation are executed by the second arithmetic circuit and the second selector circuit, the input data is input to the second input terminal of the cumulative addition circuit. And a control circuit for applying the negative number to the second input terminal of the cumulative addition circuit when executing the cumulative subtraction operation.

Preferably, a plurality of the above arithmetic circuits and the plurality of arithmetic circuits are controlled to cause these arithmetic circuits to execute either the moving addition value calculation or the cumulative addition calculation in parallel. And a control circuit. Preferably,
A control circuit that controls the plurality of second arithmetic circuits and the plurality of arithmetic circuits and causes these arithmetic circuits to execute any one of the moving addition value arithmetic operation, the cumulative addition arithmetic operation, and the cumulative subtraction arithmetic operation in parallel. And.

[0011]

In the arithmetic circuit according to the present invention, the input register sequentially stores the pixel data of the input video signal every clock cycle of the signal processor, and inputs the pixel data immediately before the stored clock cycle. The selected pixel data is sequentially supplied to the selector circuit. The cumulative addition circuit adds, for each clock cycle, the selection output data supplied from the selector circuit and the pixel data input in the clock cycle to calculate addition result data, and outputs the addition result data. Supply to the result register.

The addition result register sequentially stores the addition result data supplied from the cumulative addition circuit for each clock cycle, and sequentially selects the addition result data supplied in the immediately preceding stored clock cycle. Second of the circuit
Supply as input data for. The selector circuit supplies the first input data to the cumulative addition circuit when calculating the moving addition value, or the second input data when calculating the cumulative addition value.
The input data of is supplied to the cumulative addition circuit.

The pixel data of the immediately preceding clock cycle is stored in the input register, and the cumulative addition circuit adds the pixel data to the pixel data input in the clock cycle. Access to the memory circuit outside the arithmetic circuit other than the addition result data output is unnecessary, and one moving addition arithmetic process can be executed in one clock cycle. Also,
Pixel data input to the previous clock cycle stored in the input register by the selector circuit, or
By selecting the addition result data calculated in the previous clock cycle stored in the addition result register and adding any one of these with the pixel data input in that clock cycle by the cumulative addition circuit, The moving addition arithmetic processing and the cumulative addition arithmetic processing can be executed by the same circuit.

[0014]

First Embodiment Hereinafter, the first embodiment of the present invention will be described with reference to FIGS.
An example will be described. First, the configurations of the signal processor 1 and the arithmetic circuit 30 used therein will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, the signal processor 1 includes a control unit (CU) 10, an input / output buffer (IOB) 12, and a working buffer (WB).
14 and the arithmetic processing unit 20 include an internal bus (IBUF) 16
Are connected to each other through the arithmetic processing unit 20.
Is an arithmetic operation unit (ALU) 22, a multiplication circuit 24,
It is composed of a shifter 26 and an arithmetic circuit 30.

The control unit 10 controls each component of the signal processor 1 via a control signal shown by a dotted line in FIG. The input / output buffer 12 is the control unit 10
Under the control of, the data IOD input / output between the signal processor 1 and the external circuit is buffered.
The working buffer 14 buffers data input from each component of the signal processor 1 under the control of the control unit 10. The internal bus 16 transmits data transmitted / received between each component of the signal processor 1.

The arithmetic unit 22 is the control unit 1
Under the control of 0, arithmetic and logical operations are performed on the data stored in the input / output buffer 12 and the working buffer 14, and the data is output to the input / output buffer 12 and the working buffer 14 via the internal bus 16. Under the control of the control unit 10, the multiplication circuit 24 receives the input / output buffer 12 and the working buffer 14.
The data stored in 1 is multiplied and output to the input / output buffer 12 and the working buffer 14 via the internal bus 16. Under the control of the control unit 10, the shifter 26 shifts the data stored in the input / output buffer 12 and the working buffer 14, and the input / output buffer 12 and the working buffer 14 via the internal bus 16.
Output to

The signal processor 1 is a processor used in a video signal processing device and the like, and the data I included in a video signal in a digital format is formed by the above-mentioned components.
For OD, discrete cosine transform processing, discrete cosine inverse transform processing, quantization processing, inverse quantization processing, motion vector detection processing, motion compensation processing, image data addition processing, subtraction processing, cumulative addition processing and moving average calculation processing. The above-described element processing necessary for video signal processing such as video signal compression encoding processing and decompression decoding processing is adaptively executed.

As shown in FIG. 2, the arithmetic circuit 30 includes a complement generating circuit 300 and a first selector circuit (SEL) 30.
2, a cumulative addition circuit (ACC) 304, an addition result register (REG) 306, and a second selector circuit 308. With these components, the arithmetic circuit 30 sequentially outputs pixel data input from the input / output buffer 12 and the working buffer 14 via the internal bus 16 and the input terminal X to the control signal ACC_CNTL.

[0], AC
Under the control of the control unit 10 via C_CNTL [1], cumulative addition processing and average calculation processing are performed, and output to the input / output buffer 12 and the working buffer 14 via the output terminal A and the internal bus 16.

The operation when the signal processor 1 and the arithmetic circuit 30 perform the motion compensation process will be described below. Prior to the description of the operations of the signal processor 1 and the arithmetic circuit 30, the content of the motion compensation processing in the video signal processing device will be described with reference to FIGS. 3 and 4. The motion compensation processing in the video signal processing device is classified by the value of the motion vector calculated from the video signal and the method (block mode) of dividing the pixel data included in the video signal into blocks. When performing the most complicated motion compensation process, two calculation processes of virtual pixel generation and predicted pixel generation are performed.

First, the virtual pixel generation process will be described with reference to FIG. The virtual pixel generation process is a process of generating a virtual pixel by interpolating between pixels in accordance with a half-pixel precision motion vector. The values of the virtual pixel data a to e of the virtual pixels a to e shown in FIG. 3 are expressed by the following equations 1 to 5.
However, in Expressions 1 to 5, a to e are virtual pixels a,
It is the value of the virtual pixel data a, b, c, d, e of b, c, d, e, and x, y, z, w is the pixel data x, y, z of the pixel x, y, z, w. , W.

[0021]

## EQU00001 ## a = (x + y + z + w) / 4 (1)

[0022]

## EQU00002 ## b = (x + z) / 2 (2)

[0023]

## EQU3 ## c = (z + w) / 2 (3)

[0024]

D = (y + w) / 2 (4)

[0025]

## EQU00005 ## e = (x + y) (5)

By the way, as can be seen from FIG. 3 and equations 1 to 5, the most complicated virtual pixel generation process is the center of four adjacent pixel data x, y, z, w. This is a process of generating virtual pixel data a.

The prediction pixel generation process will be described below. The prediction pixel generation process differs depending on whether it is a unidirectional (forward or backward) motion compensation prediction process or a bidirectional motion compensation prediction process, that is, a processing mode. That is, in the case of performing the unidirectional motion compensation prediction, the frame memory storing the video signal is simply accessed according to the motion vector, the pixel data of the image block is obtained, and the process is performed. On the other hand, the bidirectional motion compensation prediction process obtains image data of image blocks from two frame memories that store video signals of preceding and following frames according to two types of forward and backward motion vectors, respectively, and obtains these pixels. Calculate the average value of the data to obtain the predicted value.

Hereinafter, further referring to FIG. 4, the arithmetic circuit 3
FIG. 3 shows the operation when the virtual pixel generation process is performed with 0.
The generated virtual pixel data b or virtual pixel data c.
The case will be described as an example. The arithmetic circuit 30 has the image shown in FIG.
Raw data x_k(K = ..., i-3, i-2, ..., i + 3,
(..., the same below), the calculation shown in Equation 6 is performed to
Virtual pixel data is sequentially generated from the pixel data to be processed.
Such calculation processing is called moving average calculation processing.
However, in FIG. 4 and Equation 6, x_kIs the pixel data
Show, y _kIndicates virtual pixel data.

[0029]

Y _k = (x _k + x _k-1 ) / 2 (6)

In the signal processor 1, the arithmetic circuit 30 performs the processing of calculating the numerical value x _k + x _{k- 1} among the arithmetic processing shown in the equation 6, and the moving addition value x _k + x _{k-1 is set} to the numerical value 2
The shifter 26 performs the process of dividing by to calculate the moving average value (x _k + x _k-1 ) / 2. Note that, hereinafter, the arithmetic processing for adding adjacent pixel data, that is, the arithmetic operation before the shift processing by the shifter 26 is referred to as a moving addition operation, and the result thereof is referred to as a moving addition value.

The operation of the arithmetic circuit 30 for calculating the horizontal moving addition value will be described below with reference to Table 1. The process of generating the virtual pixel data a shown in FIG. 3 and Expression 1 can be realized by, for example, performing the above-described virtual pixel generation process in the horizontal direction and then in the vertical direction. The arithmetic circuit 30 performs the arithmetic operation shown in Table 1 to perform the moving average arithmetic processing.

[0032]

[Table 1] Clock cycle: Input data X: Output data A: (Pixel data): (Addition result data) 0: x _i-3 : 0 + x _i-3 1: x _i-2 : x _i-3 + x _{i -2} 2: x _i-2 : 0 + x _i-2 3: x _i-1 : x _i-2 + x _i-1 4: x _i-1 : 0 + x _i-1 5: x _i : x _i-1 + X _i 6: x _i : 0 + x _i 7: x _{i + 1} : x _i + x _{i + 1} 8: x _{i + 1} : 0 + x _{i + 1} 9: x _{i + 2} : x _{i + 1} + x _{i + 2} 10: x _{i + 2} : 0 + x _{i + 2} 11: x _{i + 3} : x _{i + 2} + x _{i + 3} · ： ・ ： ・ ・ ： ・ ： ・ ・ ： ・ ・ ： ・

As shown in Table 1, in the clock cycle 0, the control unit 10 controls the control unit 10 in the initialized state, that is, the arithmetic circuit 30 in which the content of the addition result register 306 is set to 0. According to the working buffer 14 or the input / output buffer 12
To read the pixel data x _i-3 from the input terminal X into the cumulative addition circuit 304. On the other hand, the selector circuit 308
Selects the numerical value 0 and outputs it as the selected output data to the cumulative addition circuit 304 (moving average calculation mode). The cumulative addition circuit 304 adds and holds the numerical value 0 and the pixel data x _i-3 , and adds the addition result data x _i-3 to the addition result register 3
It is stored in 06.

In clock cycle 1, arithmetic circuit 3
0 is the pixel data x under the control of the control unit 10.
_i-2Working buffer 14 or input / output buffer 1
Read from 2. At this time, the selector circuit 308
Clock cycle 0 output from the result register 306
Result data x calculated in_i-3Select
Output as selected output data to the adder circuit 304
(Cumulative addition operation mode). The cumulative addition circuit 304 outputs the selected output.
Data x_i-3And input in clock cycle 1
Pixel data x_i-2And are added and added from output terminal A
Calculation result data x _i-3+ X_i-2Is output.

Similarly after clock cycle 2, the arithmetic circuit 30 controls the addition result data x _i-2 + x _i-2 , x every two clock cycles under the control of the control unit 10.
_i-1 + x _i , ... Are sequentially calculated and output from the output terminal A. That is, the arithmetic circuit 30 outputs the input / output buffer 12 or the working buffer 1 once every clock cycle.
4 is accessed to calculate one moving addition value every two clock cycles. Under the control of the control unit 10, the shifter 26 sequentially divides the moving addition value calculated in the arithmetic circuit 30 by the numerical value 2, calculates the moving average value, and calculates the moving average value via the internal bus 16 and the input / output buffer 12. Three
Output to the outside of 0.

[0036]

[Second Embodiment] A second embodiment of the present invention will be described below with reference to FIG. The configuration of the arithmetic circuit 40 will be described below with reference to FIG. As shown in FIG. 5, in the arithmetic circuit 40, in addition to the constituent elements of the arithmetic circuit 30, a selector circuit 402 is connected between the selector circuit 308 and the cumulative addition circuit 304, and further between the selector circuit 402 and the input terminal X. The register 400 is connected to. The components of the arithmetic circuit 40 not described below are the same as the components of the arithmetic circuit 30 denoted by the same reference numerals.

The register 400 sequentially stores the pixel data input from the input / output buffer 12 or the working buffer 14 via the input terminal X every clock cycle, and the selector circuit 402 in the next clock cycle.
Are sequentially output to. The selector circuit 402 controls the control unit 10 via the control signal ACC_CNTL [2].
In the moving average operation mode, the pixel data input to the previous clock cycle, which is held in the register 400, is output to the cumulative addition circuit 304 as selected output data under the control of 1.

The selector circuit 402 also controls the control signal A.
Under the control of the control unit 10 via CC_CNTL [2], in the cumulative addition operation mode, the numerical value 0 selected by the selector circuit 308 or the addition result data of the cumulative addition circuit 304 in the previous clock cycle is added to the cumulative addition circuit 304. Output to.

The arithmetic circuit 40 is an arithmetic circuit suitable for the above-described virtual pixel generation processing, and is used in place of the arithmetic circuit 30 in the signal processor 1 shown in FIG.
The control signal ACC_CNTL is made by each of the above components.

[0], ACC_CNTL [1], ACC_CNTL
According to the control of the control unit 10 via [2], initialization is performed, or the moving addition value and cumulative addition value (cumulative subtraction value) of pixel data are calculated.

As will be described later, the arithmetic circuit 30 shown in the first embodiment calculates one moving addition value every two clock cycles, whereas the arithmetic circuit explained in the second embodiment. 40 can calculate one moving addition value for each clock cycle. In addition, the arithmetic circuit 40
Of the constituent elements of the above, the selector circuit 402 corresponds to the first selector circuit according to the present invention, the register 400 corresponds to the input register according to the present invention, and the cumulative addition circuit 304 corresponds to the cumulative addition circuit according to the present invention. Corresponding to the addition result register 306
Corresponds to the cumulative addition result register according to the present invention.

The operation of the arithmetic circuit 40 for calculating the horizontal moving addition value will be described below with reference to Table 2.

[0042]

[Table 2] Clock cycle: input data X: output data A: (pixel data): (addition result data) 0: x _i-3 : x _i-3 1: x _i-2 : x _i-3 + x _{i- 2} 2: x _i-1 : x _i-2 + x _i-1 3: x _i : x _i-1 + x _i 4: x _{i + 1} : x _i + x _{i + 1} 5: x _{i + 2} : x _{i + 1} + x _{i + 2} 6: x _{i + 3} : x _{i + 2} + x _{i + 3} · ： ・ ： ・ ・ ：： ・ ： ・ ・ ： ・ ・ ： ・ ・

As shown in Table 2, in the clock cycle 0, the control circuit 10 controls the initialization state, that is, the arithmetic circuit 40 in which the contents of the addition result register 306 and the register 400 are set to the numerical value 0 is the control unit. Under the control of 10, the working buffer 14 or the input / output buffer 12 is accessed to read the pixel data x _i-3 from the input terminal X. In addition, the selector circuit 302
Is a control signal ACC_CNTL

Under control of the control unit 10 via [0], non-inverted pixel data is selected and output to the cumulative addition circuit 304, and the register 400
Stores the pixel data x _i-3 input at clock cycle 0.

On the other hand, the selector circuit 308 controls the control signal A
Under the control of the control unit 10 via CC_CNTL [1], the addition result data (numerical value 0 in clock cycle 0) held in the addition result register 306 is selected and output to the selector circuit 402. Also,
The selector circuit 402 controls the control signal ACC_CNTL.
Under the control of the control unit 10 via [2], the data output from the selector circuit 302 is selected and output as the selected output data to the cumulative addition circuit 304 (cumulative addition calculation mode). The cumulative addition circuit 304 adds the numerical value 0 and the pixel data x _i-3 , stores the addition result data x _i-3 in the addition result register 306, and outputs it from the output terminal A.

In clock cycle 1, arithmetic circuit 4
0 is the pixel data x under the control of the control unit 10.
_i-2Working buffer 14 or input / output buffer 1
Read from 2. At this time, the selector circuit 402
In clock cycle 0 stored in the star 400
Input pixel data x_i-3And the cumulative addition circuit 30
Output data x selected for 4_i-3Output as (move
Average calculation mode). The cumulative addition circuit 304 uses the selected output data.
Tax_i-3And in clock cycle 1
Pixel data x_i-2Add and, and add from output terminal A
Result data x _i-3+ X_i-2Is output.

Similarly after clock cycle 2, the arithmetic circuit 40, under the control of the control unit 10, adds result data x _i-2 + x _i-1 , x every clock cycle.
_i-1 + x _i , ... Are sequentially calculated and output from the output terminal A. That is, the arithmetic circuit 40 outputs the input / output buffer 12 or the working buffer 1 once every clock cycle.
4 is accessed to calculate one moving addition value in one clock cycle. Under the control of the control unit 10, the shifter 26 sequentially divides the moving addition value calculated by the arithmetic circuit 40 by the numerical value 2, calculates the moving average value, and calculates the moving average value via the internal bus 16 and the input / output buffer 12. Four
Output to the outside of 0. The arithmetic processing in the shifter 26 can be performed in parallel with the arithmetic processing in the arithmetic circuit 40. The procedure by which the arithmetic circuit 40 calculates the moving addition value is not limited to the above, and may be changed as long as the same result can be obtained.

In the calculation circuit 40, the cumulative addition value of the pixel data x _k is calculated by the selector circuit 308 according to the control unit 10 to always select the addition result data input from the addition result register 306 to the selector circuit 402. This is possible by outputting the data to the cumulative addition circuit 304 by selecting the data input from the selector circuit 308 by the selector circuit 402 at all times. In addition, the selector circuit 302 selects the complement corresponding to the negative number of the pixel data x _k generated by the complement generation circuit 300 according to the control of the control unit 10 and outputs the complement to the cumulative addition circuit 304. 40 can calculate the cumulative subtraction value of the pixel data x _k . (The calculation for calculating the cumulative subtraction value is called cumulative subtraction calculation).

Even if the register 400 and the selector circuit 402 are added to the arithmetic circuit 40 to realize the moving average arithmetic function, the performance of the functions (cumulative addition, cumulative subtraction, etc.) realized in the arithmetic circuit 30 is also improved. It does not decrease. That is, the arithmetic circuit 40 has a so-called upper compatible relationship with the arithmetic circuit 30, and the versatility is not impaired at all as compared with the arithmetic circuit 30. As described above, according to the present invention, in the video processing device, the moving average value (moving addition value) used for the virtual pixel generation in the motion compensation process.
When calculating, by storing the pixel data read in the previous clock cycle in the register 400,
Unlike the arithmetic circuit 30, it is not necessary to access the same pixel data twice over two clock cycles. Therefore, the number of clock cycles in the motion compensation processing can be reduced, and the performance of the signal processor 1 can be improved by replacing the arithmetic circuit 30 with the arithmetic circuit 40.

That is, for example, when performing virtual pixel generation processing for generating 256 virtual pixel data (16 × 16 macroblocks) in the horizontal direction, the arithmetic circuit 40 causes the 17 pixel data in the horizontal direction to be generated. 16 virtual pixel data is generated over 17 clock cycles, and this is repeated 16 times. Therefore, 256 virtual pixel data can be generated in 272 clock cycles. Further, the control sequence by the control unit 10 for performing this virtual pixel generation process may have 272 steps. Therefore, by replacing the arithmetic circuit 30 with the arithmetic circuit 40, the control unit 1 of the signal processor 1
0 can also be simplified.

[0050]

Third Embodiment A third embodiment of the present invention will be described below with reference to FIG. FIG. 6 is a diagram showing the configuration of the signal processor 2 according to the present invention in the third embodiment. The signal processor 2 includes the arithmetic processing unit 20 shown in FIG.
Arithmetic processing section 50 having a plurality of arithmetic circuits 40 ₁ to 40 _n
It has been replaced with. The arithmetic circuit 40 _1-
40 _n and the arithmetic circuit 40 shown in FIG. 5 are the same.
As shown in FIG. 6, each arithmetic circuit 40 ₁ of the arithmetic processing unit 50
The control unit 10 controls each of .about.40 _n in parallel in the same manner as the arithmetic circuit 40, whereby moving average calculation and the like can be performed in parallel, and the speed of video signal processing can be improved.

The configurations of the signal processors 1 and 2 and the configurations of the arithmetic circuits 30 and 40 are not limited to those shown in FIGS. 1 and 6, but necessary components are added or unnecessary components are deleted. You may. In addition to the embodiments described above, for example, in the signal processor 2, a plurality of arithmetic operation units 22, multiplication circuits 24, and shifters 26 are provided, and the arithmetic circuit of the present invention and the signal processor using the same are various. Can be configured.

[0052]

As described above, according to the arithmetic circuit of the present invention, the time required for the moving average arithmetic processing can be shortened, and the cumulative addition processing required for the video signal processing can be performed by the same circuit. Can also be done. Therefore, by using the arithmetic circuit of the present invention, it is possible to improve the efficiency of video signal processing and provide a signal processor or a video signal processing device with a short processing time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a signal processor according to the present invention.

FIG. 2 is a diagram showing a configuration of an arithmetic circuit according to the present invention in a first embodiment.

FIG. 3 is a diagram showing a rule of virtual pixel generation processing for generating virtual pixel data.

FIG. 4 is a diagram showing an operation when the arithmetic circuit shown in FIG. 2 generates horizontal component virtual pixel data.

FIG. 5 illustrates a configuration of an arithmetic circuit according to the present invention in a second embodiment.

FIG. 6 is a diagram showing a configuration of a signal processor according to the present invention in a third exemplary embodiment.

[Explanation of Codes] 1, 2 ... Signal Processor, 10 ... Control Unit, 1
2 ... I / O buffer, 14 ... Working buffer, 16
... internal bus, 20, 50 ... arithmetic processing unit, 22 ... arithmetic operation unit, 24 ... multiplication circuit, 26 ... shifter, 30, 40
... arithmetic circuit, 300 ... complement generation circuit, 302 ... selector circuit, 304 ... cumulative addition circuit, 306 ... addition result register, 308 ... selector circuit, 400 ... register, 402
... Selector circuit

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H04N 7/137 Z

Claims (5)

[Claims] 1. A cumulative addition circuit which has a first input terminal and a second input terminal to which input data is applied, and which adds and holds data input from these input terminals, and the cumulative addition A cumulative addition result register that holds the output data of the circuit; an input register that holds the input data that is input in response to the operation clock; and either the output data of the cumulative addition result register or the output data of the input register. A first selector circuit for selecting and applying to a first input terminal of the cumulative addition circuit, and when performing a moving addition operation, the first selector circuit outputs the output data of the input register. When applied to the first input terminal of the cumulative addition circuit to execute the cumulative addition operation, the first selector circuit outputs the output data of the cumulative addition result register to the first addition circuit of the cumulative addition circuit. Arithmetic circuit for applying to the input terminal. 2. A negative number generation circuit for generating a negative number of the input data, and a circuit for selecting one of the output data of the negative number generation circuit and the input data and applying the selected data to a second input terminal of the cumulative addition circuit. And a second selector circuit, wherein the second selector circuit applies the input data to the second input terminal of the cumulative addition circuit when performing the moving addition operation and the cumulative addition operation. The arithmetic circuit according to claim 1, wherein the second selector circuit applies the negative number to the second input terminal of the cumulative addition circuit when performing a subtraction operation. 3. The arithmetic circuit according to claim 2, wherein the moving data addition operation and the cumulative addition operation are executed by the second selector circuit, the input data is input to the second input terminal of the cumulative addition circuit. And a control circuit for applying the negative number to the second input terminal of the cumulative addition circuit when the cumulative subtraction operation is performed. 4. A plurality of arithmetic circuits according to claim 1 or 2, and a plurality of arithmetic circuits that are controlled to perform one of the moving addition value arithmetic and the cumulative addition arithmetic in parallel with these arithmetic circuits. A signal processor having a control circuit for executing the signal processing. 5. A plurality of arithmetic circuits according to claim 2, and a plurality of arithmetic circuits that control the arithmetic circuits to perform the moving addition value arithmetic operation, the cumulative addition arithmetic operation, and the cumulative subtraction arithmetic operation in parallel with the arithmetic operation circuits. A signal processor having a control circuit for executing any of the above.