JPH08115974A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE: To provide a semiconductor device the size of which can be modified during the slicing process by a structure wherein an impurity region being divided by first and second insulating walls but continuous between both insulating walls constitutes a semiconductor element between both insulating walls. CONSTITUTION: The semiconductor device comprises first and second insulating walls 22a, 22b extending in same direction, and at least one impurity region 3 of semiconductor extending longer than the interval between the first and second insulating walls 22a, 22b from the first insulating wall 22a toward the second insulating walls 22b. Any impurity region 3 is divided by the first and second insulating walls 22a, 22b and at least one impurity region 3 is continuous between the first and second insulating walls 22a, 22b and constitutes a semiconductor element between them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for determining the size of a semiconductor device having semiconductor elements such as bipolar transistors, MOS transistors, BiCMOS transistors, capacitors, resistors and diodes.

[0002]

158 to 160 are views showing a conventional technique, FIG. 158 is a plan view, FIG. 159 is a cross-sectional view as seen from the X1X1 direction in FIG. 158, and FIG. 160 is a Y1Y1 direction in FIG. It is sectional drawing seen from.
Also, FIG. 158 shows the structure of FIG.
It is the top view seen from the D1D1 direction of 60.

In FIG. 158, three transistors Q are provided.
1, Q2, Q3 are shown, but for simplicity, only the transistor Q1 is shown in FIGS. 159 and 160.

An N-conductivity type epitaxial layer 3 is formed on a substrate 1 made of a P-conductivity type single crystal semiconductor.
Further, in the vicinity of the interface between the substrate 1 and the epitaxial layer 3, N ⁺
A conductive type buried layer 2 is formed. And an N ⁺ conductive type collector extraction layer (collector wall) 5,
The epitaxial layer 3 and the buried layer 2 are the transistor Q.
It constitutes one collector. Here, the buried layer 2 has a function of reducing the collector resistance of the transistor Q1.

An intrinsic base 11 and a base electrode lead layer (external base) 9 for reducing the base resistance are provided on the upper surface of the epitaxial layer 3, and both form the base of the transistor Q1.

Further, an N conductive type emitter 15 is formed on the upper surface of the intrinsic base 11. The transistor Q1 is isolated from the others by the oxide film 21 buried in the trench 24 and the field oxide film 4 selectively formed on the upper surface of the epitaxial layer 3.

Further, these transistors Q1, Q2,
Q3 is covered with an interlayer film 12 such as an oxide film, and contact holes 14 are selectively formed in these. The contact hole 14 is filled with an aluminum electrode 16 so as to be electrically connected to each of the emitter, the collector, and the base.

The emitter lengths of the transistors Q1, Q2, Q3 are L1, L2, L3, respectively.

Such transistors Q1, Q2, Q3
Can be manufactured as follows. 161 to 178 are cross-sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps, including FIGS. 161, 163, 165, and 16.
7, FIG. 169, FIG. 171, FIG. 173, FIG. 175, FIG.
7 corresponds to FIG. 159, and FIGS. 162, 164, 166, 168, 170, 172, 174, 176 and 178 all correspond to FIG. 160.

First, an N conductivity type impurity is selectively implanted into the substrate 1 by an ion implantation method, and heat treatment is performed to form a buried layer 2. Further, Si epitaxial growth containing N conductivity type impurities is performed to form the epitaxial layer 3.
After that, the oxide film 20 is formed by the CVD method, and photoengraving is performed to selectively remove the oxide film 20. Thereafter, using the oxide film 20 as a mask, the epitaxial layer 3 and the substrate 1 are anisotropically etched with a fluorine-based gas so as to reach the substrate 1. As a result, the trench 24 is formed (FIGS. 161 and 162).

Next, the oxide film 2 is formed on the entire surface of the wafer by the CVD method.
1 is deposited to completely fill the trench 24 (FIG. 16).
3, FIG. 164).

Then, the entire surface of the wafer is etched by a fluorine-based gas until the epitaxial layer 3 is exposed, and the oxide film 21 is left only in the trench 24 (FIG. 16).
5, FIG. 166).

Then, the epitaxial layer 3 and the trench 2
The upper surface of 4 is selectively oxidized to form a field oxide film 4. Thereafter, the N conductivity type impurities are further selectively diffused in the solid phase to form the collector wall 5 (FIGS. 167 and 16).
8).

Next, the resist film 7 is patterned by photolithography, and ions are implanted using this as a mask to introduce impurities of P conductivity type into the epitaxial layer 3. This forms the external base 9 (FIGS. 169 and 17).
0).

Next, the resist film 7 is removed, and the resist film 10 is patterned by photolithography. Using this as a mask, ions are implanted to introduce P-conductivity type impurities into the external base 9 and the epitaxial layer 3 to form an intrinsic base. 11 is formed (FIG. 171, FIG. 172).

After that, the resist film 10 is removed, and the resist film 19 is patterned by photolithography. Using this as a mask, ions are implanted to introduce impurities of N conductivity type into the intrinsic base 11 to form the emitter 15 (FIG. 17
3, FIG. 174).

After that, the resist film 19 is removed, and the interlayer film 1 is removed.
2 is formed by the CVD method (FIGS. 175 and 17).
6). The processes up to this correspond to the master process of the gate array.

Next, the resist film 13 is patterned by photolithography, and the interlayer film 12 is anisotropically etched using this as a mask to form contact holes 14 (FIGS. 177 and 178).

After that, an aluminum alloy film is formed by a sputtering method, and this is selectively etched to form the aluminum electrode 16 (FIGS. 159 and 160).

[0020]

Now, the semi-custom I
A gate array, which is a type of C, can be roughly classified into a master process for manufacturing semiconductor elements and a slicing step for wiring between semiconductor elements.

Before the customer orders the LSI, the manufacturer prepares a wafer (master) manufactured up to the master process in anticipation of the customer's order, and the LSI ordered by the customer thereafter has only wiring to this master. It is produced by forming. By thus dividing the LSI manufacturing process into two steps, the time required from the customer ordering the LSI to the actual manufacturing of the LSI can be shortened considerably.

Taking the above-described method for manufacturing a semiconductor device as an example, the steps up to the steps shown in FIGS. 175 and 176 correspond to the gate array master step, and the subsequent steps correspond to the slicing step.

However, if the master process is prepared in advance, the size of the semiconductor element is fixed. In other words, in the slicing process, it is possible to freely design the semiconductor devices in terms of simply wiring the semiconductor devices to each other, but since the semiconductor device is already manufactured in the master process, the size of the semiconductor device is reduced. Has the problem that it cannot always respond freely.

In order to solve such a problem, a master including a plurality of types of semiconductor elements having different sizes is produced.
Although it is conceivable to prepare a plurality of types of masters having different semiconductor element sizes, the manufacturing cost will be increased, which is not desirable.

The present invention has been made in order to solve the above-mentioned problems. As in the conventional case, the size of the semiconductor element is reduced even in the slicing step while ensuring the free design of the wiring in the slicing step. An object is to obtain a semiconductor device that can be changed. Another object is to provide a manufacturing method suitable for such a semiconductor device.

[0026]

[Means for Solving the Problems] Claim 1 of the present invention
(A) A first insulating wall and a second insulating wall extending in the same direction, and (b) a direction from the first insulating wall to the second insulating wall. And a semiconductor device including at least one impurity region made of a semiconductor, which is provided longer than a distance between the first insulating wall and the second insulating wall. Each of the impurity regions is divided by the first insulating wall and the second insulating wall, and at least one impurity region is provided between the first insulating wall and the second insulating wall. The impurity regions are continuous and form a semiconductor element between the first insulating wall and the second insulating wall.

A second aspect of the present invention is the semiconductor device according to the first aspect, wherein the impurity region is
A first conductivity type collector region, a second conductivity type base region,
And the first conductivity type emitter region, and the semiconductor element is a bipolar transistor.

A third aspect of the present invention is the semiconductor device according to the second aspect, wherein the collector region comprises:
All of the base region and the emitter region are continuous between the first insulating wall and the second insulating wall.

According to a fourth aspect of the present invention, in the semiconductor device according to the second aspect, (c) the first insulating wall and the second insulating wall are provided in the same direction. A third insulating wall that extends to divide the base region and the emitter region is further provided.

According to a fifth aspect of the present invention, in the semiconductor device according to the second aspect, (c) between the first insulating wall and the second insulating wall in the same direction. It further comprises a third insulating wall extending to divide the emitter region.

A sixth aspect of the present invention is the semiconductor device according to the first aspect, wherein the impurity region is
A first conductivity type anode region and a second conductivity type cathode region, and the semiconductor element is a diode.

A seventh aspect of the present invention is the semiconductor device according to the first aspect, wherein the impurity region is a resistor and the semiconductor element is a resistor.

The invention according to claim 8 is the semiconductor device according to claim 7, wherein the impurity region is
The first conductive type resistor and the second conductive type support layer are electrically separated from each other by applying a reverse bias to the resistor and the support layer.

According to a ninth aspect of the present invention, there is provided the semiconductor device according to the seventh aspect, wherein (c) the semiconductor device is arranged along the direction from the first insulating wall toward the second insulating wall. A first insulating wall and a second insulating wall, the insulating layer is provided longer than a distance between the first insulating wall and the second insulating wall, and the resistor is divided into the first insulating wall and the second insulating wall;
Are separated by the insulating wall and the second insulating wall and the insulating layer.

According to a tenth aspect of the present invention, (a) a first insulating wall and a second insulating wall extending in the same direction, and (b) (b-1) the first insulating wall Along the direction from the insulation wall of the first insulation wall to the second insulation wall.
At least one conductive region that is longer than the distance between the insulating wall and the second insulating wall and is made of a semiconductor into which an impurity that determines the conductivity type is introduced; and (b-2) the first insulating wall. A configuration region that is provided longer than a distance between the first insulating wall and the second insulating wall and has an insulating insulating region, along a direction from the first insulating wall to the second insulating wall. It is a device. Each of the constituent regions is divided by the first insulating wall and the second insulating wall, and at least one of the constituent regions is the first insulating wall.
Between the first insulating wall and the second insulating wall, and the constituent region constitutes a semiconductor element between the first insulating wall and the second insulating wall.

According to an eleventh aspect of the present invention, in the semiconductor device according to the tenth aspect, the conductive region is formed on a first conductive type base having an upper surface and the upper surface of the base. A pair of second conductivity type source / drain regions and a gate region, the insulating region is formed on a region sandwiched by the pair of source / drain regions on the upper surface of the base, and the gate region is Formed above the insulating region, the semiconductor element is a MOS transistor.

According to a twelfth aspect of the present invention, in the semiconductor device according to the eleventh aspect, all of the pair of source / drain regions, the gate region, and the insulating region are the first insulating wall. And the second insulating wall are continuous.

A thirteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, including: (c) the first device.
A third insulating wall that extends in the same direction and divides one of the gate region, the insulating region, and one of the source / drain regions is further provided between the insulating wall and the second insulating wall.

A fourteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, including: (c) the first device.
A third insulating wall that extends in the same direction and divides the gate region and the insulating region is further provided between the insulating wall and the second insulating wall.

According to a fifteenth aspect of the present invention, the semiconductor device according to the eleventh aspect is provided, in which (c) the first
Between the second insulating wall and the second insulating wall, the third insulating wall extending in the same direction and dividing only one of the source / drain regions is further provided.

According to a sixteenth aspect of the present invention, there is provided the semiconductor device according to the fifteenth aspect, including:
Between the insulating wall and the second insulating wall, a fourth insulating wall extending in the same direction and dividing only the other of the source / drain regions is further provided.

A seventeenth aspect of the present invention is the semiconductor device according to the tenth aspect, wherein the conductive region is a first conductor and a second conductor, and the insulating region is the first conductor. Formed by being sandwiched between the conductor and the second conductor,
The semiconductor element is a capacitor.

According to a eighteenth aspect of the present invention, (a) a step of forming at least one impurity region extending in the first direction, made of a semiconductor, and having a length of a predetermined value or more, b) After the step (a), a first insulating wall and a second insulating wall which are orthogonal to the first direction and divide any of the impurity regions and are separated by a distance shorter than the predetermined value are formed. And (c) after the step (b), wiring the semiconductor element formed of the impurity region between the first insulating wall and the second insulating wall. It is a method of manufacturing a semiconductor device. Then, at least one impurity region is continuous between the first insulating wall and the second insulating wall.

A nineteenth aspect of the present invention is the method for manufacturing a semiconductor device according to the eighteenth aspect, wherein the impurity region is a first conductivity type collector region, a second conductivity type base region, and The first conductivity type emitter region and the semiconductor element are bipolar transistors.

A twentieth aspect of the present invention is the method for manufacturing a semiconductor device according to the nineteenth aspect, wherein all of the collector region, the base region, and the emitter region are the first insulating wall. It is continuous between the second insulating walls.

A twenty-first aspect of the present invention is the method for manufacturing a semiconductor device according to the nineteenth aspect, which comprises (d) the first step after the step (a) and before the step (c).
Between the first insulating wall and the second insulating wall
And a step of forming a third insulating wall that is orthogonal to the direction of and divides the base region and the emitter region.

A twenty-second aspect of the present invention is the method for manufacturing a semiconductor device according to the nineteenth aspect, which comprises (d) the first step after the step (a) and before the step (c).
Between the first insulating wall and the second insulating wall
And a step of forming a third insulating wall that is orthogonal to the direction of and divides the emitter region.

A twenty-third aspect of the present invention is the method for manufacturing a semiconductor device according to the eighteenth aspect, wherein the impurity regions are a first conductivity type anode region and a second conductivity type cathode region. And the semiconductor element is a diode.

A twenty-fourth aspect of the present invention is the method for manufacturing a semiconductor device according to the eighteenth aspect, wherein the impurity region is a resistor and the semiconductor element is a resistor.

A twenty-fifth aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-fourth aspect, wherein the impurity regions are a first conductivity type resistor and a second conductivity type support layer. Yes, the resistor and the support layer are electrically separated by applying a reverse bias.

According to a twenty-sixth aspect of the present invention, there is provided at least one of (a) a semiconductor which extends in the first direction and is doped with an impurity for determining a conductivity type, and has a length of a predetermined value or more. Two conductive regions, extending in a first direction,
Forming a constituent region having an insulating insulating region having a length not less than the predetermined value, and (b) the step (a)
After that, a first portion that is orthogonal to the first direction and divides any of the constituent regions and that is separated by a distance shorter than the predetermined value.
Forming an insulating wall and a second insulating wall, and (c) after the step (b), a semiconductor including the constituent region between the first insulating wall and the second insulating wall. A method of manufacturing a semiconductor device, comprising: wiring an element. And at least one of the constituent regions is the first
Is continuous between the insulating wall and the second insulating wall.

A twenty-seventh aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-sixth aspect, wherein the conductive region is formed on a first conductivity type base having an upper surface and on the upper surface of the base. A pair of second conductivity type sources formed
A drain region and a gate region, and the insulating region is
The upper surface of the substrate is formed on a region sandwiched by the pair of source / drain regions, the gate region is formed above the insulating region, and the semiconductor element is a MOS.
It is a transistor.

A twenty-eighth aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-seventh aspect, wherein the pair of source / drain regions, the gate region, and the insulating region are all the first regions. Is continuous between the insulating wall and the second insulating wall.

A twenty-ninth aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-seventh aspect,
(C) A third insulating wall that extends in the same direction between the first insulating wall and the second insulating wall and divides one of the gate region, the insulating region, and one of the source / drain regions. Is further provided.

A thirtieth aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-seventh aspect,
(C) A third insulating wall, which extends in the same direction and divides the gate region and the insulating region, is further provided between the first insulating wall and the second insulating wall.

A thirty-first aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-seventh aspect,
(C) A third insulating wall which extends in the same direction and divides only one of the source / drain regions is further provided between the first insulating wall and the second insulating wall.

According to a thirty-second aspect of the present invention, there is provided a semiconductor device manufacturing method according to the thirty-first aspect,
(D) A fourth insulating wall that extends in the same direction and divides only the other of the source / drain regions is further provided between the first insulating wall and the second insulating wall.

A thirty-third aspect of the present invention is the method for manufacturing a semiconductor device according to the twenty-sixth aspect, wherein the conductive region is formed on the first conductivity type base having an upper surface and the upper surface of the base. A pair of second conductivity type sources formed
A drain region and a gate region, and the insulating region is
A gate oxide film provided between the gate region and a region sandwiched by the pair of source / drain regions on the upper surface of the base; and a nitride film covering the source / drain region and the gate region. The step (a) includes (a-1) a step of forming the gate oxide film on the upper surface of the substrate, and (a-2) a step of selectively forming the gate region on the gate oxide film. , (A-3) a step of forming a pair of the source / drain regions on the upper surface of the base, and (a-4) forming the nitride film on the structure obtained by the step (a-3). Process, and (a-
5) forming an oxide film on the structure obtained in the step (a-4); and (a-6) selectively removing the oxide film until the nitride film is exposed. -7)
Patterning by selectively removing the nitride film at the location where the oxide film is removed, and using the mask as a mask to selectively remove the gate region.
Then, the place where the oxide film, the nitride film, and the gate region are removed corresponds to the place where the first insulating wall and the second insulating wall are provided.

According to a thirty-fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-sixth aspect, the conductive region is a first conductor and a second conductor, and the insulating region is the The semiconductor element is formed by being sandwiched between a first conductor and the second conductor, and the semiconductor element is a capacitor.

[0060]

In the semiconductor device according to claim 1 of the present invention, the length of the impurity region forming the semiconductor element is determined by the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 2 of the present invention, the length of the impurity region forming the bipolar transistor is determined by the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 3 of the present invention, all of the lengths of the collector region, the base region and the emitter region forming the bipolar transistor are the first insulating wall and the second insulating wall. Is determined by the interval.

In the semiconductor device according to claim 4 of the present invention, the first and second bipolar transistors are determined. The first bipolar transistor has an emitter region and a base region sandwiched by the first insulating wall and the third insulating wall, and the second bipolar transistor is sandwiched by the third insulating wall and the second insulating wall. The first bipolar transistor and the second bipolar transistor share the collector region sandwiched by the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 5 of the present invention, the bipolar transistor has a multi-emitter structure. That is, a collector region and a base region sandwiched by the first insulating wall and the second insulating wall, a first emitter region sandwiched by the first insulating wall and the third insulating wall, a third insulating wall, and It has a second emitter region sandwiched by a second insulating wall.

In the semiconductor device according to claim 6 of the present invention, the length of the impurity region forming the diode is determined by the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 7 of the present invention, the length of the impurity region forming the resistor is the first.
Is determined by the distance between the insulating wall and the second insulating wall.

In the semiconductor device according to claim 8 of the present invention, the resistor and the support layer can be formed by using the step of forming the base and collector of the bipolar transistor, or the base and emitter.

In the semiconductor device according to claim 9 of the present invention, the resistor is separated by an insulating element.

In the semiconductor device according to claim 10 of the present invention, the length of the constituent region forming the semiconductor element is determined by the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 11 of the present invention, the length of the impurity region forming the MOS transistor is determined by the distance between the first insulating wall and the second insulating wall.

According to a twelfth aspect of the present invention, in the semiconductor device according to the twelfth aspect, the lengths of the source region, the drain region, the gate region, and the insulating region which form the MOS transistor are the first insulating wall and the second insulating wall. It is determined by the distance from the insulating wall.

In the semiconductor device according to claim 13 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a gate region and an insulating region sandwiched by the first insulating wall and the third insulating wall, and one source / drain region, and the second MOS transistor has the third insulating wall and the third insulating wall. The first MOS transistor and the second MOS transistor have a gate region and an insulating region sandwiched between two insulating walls, and one source / drain region,
Share the other source / drain region sandwiched by the insulating walls.

In the semiconductor device according to claim 14 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a gate region and an insulating region sandwiched between the first insulating wall and the third insulating wall, and the second MOS transistor sandwiches between the third insulating wall and the second insulating wall. A first MOS transistor and a second MOS having a gate region and an insulating region
The transistor shares a pair of source / drain regions sandwiched by the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 15 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has one of a source / drain region sandwiched between the first insulating wall and the third insulating wall, and the second MOS transistor sandwiches between the third insulating wall and the second insulating wall. A first MOS transistor and a second MOS transistor
The MOS transistor of 1 shares the other of the gate region and the insulating region and the source / drain region sandwiched by the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 16 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a pair of source / drain regions sandwiched by the first insulating wall and the third insulating wall, and the second MOS transistor is sandwiched by the third insulating wall and the second insulating wall. A pair of sauces
A drain region, a first MOS transistor and a second
The MOS transistor of 1 shares the gate region and the insulating region sandwiched by the first insulating wall and the second insulating wall.

According to a seventeenth aspect of the present invention, in the semiconductor device according to the seventeenth aspect, the length of the conductive region forming the capacitor is the first.
Is determined by the distance between the insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 18 of the present invention, in the step (b), the first insulating wall and the second insulating wall are added to the structure obtained in the step (a).
The distance of the insulating wall can be arbitrarily set as long as it is shorter than a predetermined value.

In the semiconductor device manufacturing method according to claim 19 of the present invention, the length of the impurity region forming the bipolar transistor is determined by the distance between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 20 of the present invention, the collector region, the base region, and the emitter region constituting the bipolar transistor have the first insulating wall and the second insulating wall, respectively. It is determined by the distance from the insulating wall.

In the semiconductor device manufacturing method according to the twenty-first aspect of the present invention, the first and second bipolar transistors are determined. The first bipolar transistor has an emitter region and a base region sandwiched by the first insulating wall and the third insulating wall, and the second bipolar transistor is sandwiched by the third insulating wall and the second insulating wall. The first bipolar transistor and the second bipolar transistor share the collector region sandwiched by the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, a bipolar transistor having a multi-emitter structure is formed. That is, the bipolar transistor has a collector region and a base region sandwiched by a first insulating wall and a second insulating wall, and a first insulating wall and a first insulating wall.
A first emitter region sandwiched by the insulating wall and the third insulating wall, and a second emitter region sandwiched by the third insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 23 of the present invention, the length of the impurity region forming the diode is determined by the distance between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to a twenty-fourth aspect of the present invention, the length of the impurity region forming the resistor is determined by the distance between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to the twenty-fifth aspect of the present invention, the resistor and the support layer can be formed by utilizing the step of forming the base and collector of the bipolar transistor, or the base and emitter.

According to a twenty-sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the length of the constituent region forming the semiconductor element is determined by the distance between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 27 of the present invention, the length of the impurity region forming the MOS transistor is determined by the distance between the first insulating wall and the second insulating wall.

According to a twenty-eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-eighth aspect, all of the lengths of the source region, the drain region and the gate region, and the insulating region which form the MOS transistor are the first insulating wall. It is determined by the distance from the second insulating wall.

In the semiconductor device manufacturing method according to claim 29 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a gate region and an insulating region sandwiched by the first insulating wall and the third insulating wall, and one source / drain region, and the second MOS transistor has the third insulating wall and the third insulating wall. Two
Having a gate region and an insulating region sandwiched between the insulating walls and one of the source / drain regions, the first MOS transistor and the second MOS transistor are sandwiched between the first insulating wall and the second insulating wall. The other source / drain region is shared.

In the method of manufacturing a semiconductor device according to claim 30 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a gate region and an insulating region sandwiched between the first insulating wall and the third insulating wall, and the second MOS transistor sandwiches between the third insulating wall and the second insulating wall. The first MOS transistor and the second MOS transistor share a pair of source / drain regions sandwiched by the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 31 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a source-source sandwiched by the first insulating wall and the third insulating wall.
The second MOS transistor has one of the drain regions, the second MOS transistor has one of the source / drain regions sandwiched by the third insulating wall and the second insulating wall, and includes the first MOS transistor and the second MOS transistor. Share the other of the gate region and the insulating region and the source / drain region sandwiched by the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 32 of the present invention, the first and second MOS transistors are determined. The first MOS transistor has a pair of source / drain regions sandwiched by the first insulating wall and the third insulating wall, and the second MOS transistor is sandwiched by the third insulating wall and the second insulating wall. The first MOS transistor and the second MOS transistor share a gate region and an insulating region sandwiched by the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to the thirty-third aspect of the present invention, the etching of the oxide film is stopped by the exposure of the nitride film.

In the method of manufacturing a semiconductor device according to a thirty-fourth aspect of the present invention, the length of the conductive region forming the capacitance is determined by the distance between the first insulating wall and the second insulating wall.

[0094]

【Example】

A. Embodiment relating to bipolar transistor: (a-1) First embodiment: FIGS. 1 to 3 show a first embodiment of the present invention.
1 is a plan view, FIG. 2 is a cross-sectional view seen from the X2X2 direction in FIG. 1, and FIG. 3 is a cross-sectional view seen from the Y2Y2 direction in FIG. Also, FIG.
FIG. 4 is a plan view seen from the A2A2 direction in FIG. 2 and the D2D2 direction in FIG. 3.

The semiconductor device shown in the first embodiment uses the oxide film 22 instead of the conventional oxide film 21,
The bipolar transistors B1, B2 and B3 are made of oxide film 22.
The elements are separated by.

The oxide film 22 is a portion 2 extending in the X2X2 direction.
2a, 22b and portions 22c, 2 extending in the Y2Y2 direction
It has 2d, 22e, 22f, 22g and 22h.
The bipolar transistors B1, B2, B3 are separated from other elements by the portions 22a, 22b, 22c, 22d of the oxide film 22. The bipolar transistors B1 and B2 are separated from each other by a portion 22f of the oxide film 22, and the bipolar transistors B2 and B3 are separated from each other by a portion 22g of the oxide film 22.

Similar to the conventional technique, the epitaxial layer 3 is formed on the substrate 1, and the buried layer 2 is formed near the interface between the substrate 1 and the epitaxial layer 3. The collector wall 5a, the epitaxial layer 3 and the buried layer 2 constitute the collector of the bipolar transistor B1. Similarly, collector walls 5b and 5c
Together with the epitaxial layer 3 and the buried layer 2, respectively constitute the collectors of the bipolar transistors B2 and B3.

An intrinsic base 11a and an extrinsic base 9a are provided on the upper surface of the epitaxial layer 3, and both form the base of the bipolar transistor B1. Similarly, the intrinsic base 11b and the extrinsic base 9b, and the intrinsic base 11c and the extrinsic base 9c, which are provided on the upper surface of the epitaxial layer 3, are bipolar transistors B2 and B, respectively.
3 forming the base.

Furthermore, the intrinsic bases 11a, 11b, 11c
Emitters 15a, 15b, 15c are formed on the upper surfaces of the respective.

The field oxide film 4 separates the collector wall and the external base on the upper surface of the epitaxial layer 3 from other regions in each of the bipolar transistors B1, B2 and B3.

In addition, these bipolar transistors B
1, B2, B3 are covered with an interlayer film 12, and contact holes 14 are selectively formed in these. Then, the contact hole 14 is filled with aluminum electrodes 16a to 16i. Here, the aluminum electrodes 16a, 16d and 16g are the collectors of the bipolar transistors B1, B2 and B3 respectively, and the aluminum electrodes 16b, 16e and 16h are the emitters of the bipolar transistors B1, B2 and B3 respectively and the aluminum electrodes 16c, 16f and 16i. Are respectively electrically connected to the bases of the bipolar transistors B1, B2 and B3.

Needless to say, the bipolar transistors B1, B2 and B3 thus separated are also operated similarly to the transistors Q1, Q2 and Q3 manufactured by the conventional technique. Such a transistor B
1, B2 and B3 can be manufactured as follows.

FIGS. 4 to 19 are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIGS. 1 to 3 in the order of steps, and FIGS. 4, 6, 8, 10, 12, and 14. 16 and 18 both correspond to FIG. 2, and FIG. 5, FIG. 7, FIG. 9, and FIG.
1, FIG. 13, FIG. 15, FIG. 17, and FIG. 19 all correspond to FIG.

First, an N-conductivity type impurity is selectively introduced into the substrate 1 by an ion implantation method, and heat treatment is performed to form a buried layer 2. Next, Si epitaxial growth containing impurities of N conductivity type is performed to form an epitaxial layer 3. Then, the epitaxial layer 3 is selectively oxidized to form a field oxide film 4. After that, the N conductivity type impurities are selectively diffused in the solid phase to form the collector wall 5 (FIGS. 4 and 5).

Next, the resist film 7 is patterned by photolithography, and ions are implanted using this as a mask to introduce impurities of P conductivity type into the epitaxial layer 3. This forms the external base 9 (FIG. 6,
(Fig. 7).

Next, the resist film 7 is removed, the resist film 10 is patterned by photolithography, and ion implantation is performed using this as a mask to introduce impurities of P conductivity type into the external base 9 and the epitaxial layer 3. This forms the intrinsic base 11 (FIGS. 8 and 9).

After that, the resist film 10 is removed, the resist film 19 is patterned by photolithography, and ion implantation is performed by using this as a mask, whereby the intrinsic base 11 is formed.
Then, impurities of N conductivity type are introduced. This forms the emitter 15 (FIGS. 10 and 11).

Next, the resist film 19 is removed, and the interlayer film 12 is formed by the CVD method (FIGS. 12 and 13).

In this embodiment, the processes up to this point are master processes. That is, as shown in FIG.
The master in which the transistor having the emitter length of L4 is formed. Prior to the customer's order, a master having such a structure is prepared.

Next, the resist film 23 is patterned by photolithography, and the interlayer film 12 and the field oxide film 4 are anisotropically etched using this as a mask using a fluorine-based gas. The etching is performed until the emitter 15, the collector wall 5, the external base 9, the intrinsic base 11, and the epitaxial layer 3 are exposed. That is, silicon appears on the entire etching region and etching stops. Thereby, the trenches 8a to 8h are punched (see FIGS. 14 and 1).
5).

Then, the resist film 23 is removed, and the epitaxial layer 3, collector wall 5, emitter 15, intrinsic base 11, external base 9, buried layer 2, and substrate 1 are used as the buried layer 2 with the interlayer film 12 as a mask. Etch deeper than the bottom surface. This etching can be realized by anisotropic etching of silicon using a fluorine-based gas. As a result, the trenches 8a to 8h extend downward.

Further, an oxide film (not shown) is formed on the entire surface of the wafer.
Is formed, and the entire surface of the wafer is etched back to form the trench 8a.
.About.8h are filled with (parts of) oxide films 22a to 22h (FIGS. 16 and 17).

By this step, the collector wall 5 is formed into collector walls 5a, 5b and 5c, the emitter 15 is formed into emitters 15a, 15b and 15c, the intrinsic base 11 is formed into intrinsic bases 11a, 11b and 11c, and the external base 9 is formed into an external base. 9a, 9b, 9c, respectively. By this division, the respective emitter lengths are L1 and L
2, L3 bipolar transistors B1, B2, B
3 is formed.

That is, in the master of this embodiment, the emitter length is not specifically set, and only the maximum value of the emitter length of the obtained bipolar transistor is limited. To set. Therefore, the size of the semiconductor device can be determined after the customer has placed an order, and the above-mentioned conventional problems can be solved.

Furthermore, the resist film 13 is patterned by photolithography, and the interlayer film 12 is anisotropically etched using the collector as a mask to form the contact holes 14a to 14i.
(14a, 14c, 14d, 14f, 14g, 14i are not shown) are punched (FIGS. 18 and 19).

Thereafter, an aluminum alloy film is formed by a sputtering method and the collector is selectively etched to form the contact holes 14a to 14i in the aluminum electrode 16.
Fill with a-16i. As a result, the semiconductor device shown in FIGS. 1 to 3 is manufactured.

As described above, according to the first embodiment of the present invention, a transistor having a relatively long emitter length is formed in the master process, and the transistor having a plurality of relatively short emitter lengths is formed in the slicing process. The division into the transistors has an effect that the size of the semiconductor element can be freely designed according to the customer's request in the slicing process.

(A-2) Second Embodiment: According to the present invention, a plurality of transistors can be connected in a slicing process without using wiring. This can be realized by sharing the diffusion regions of a plurality of transistors.

For example, FIG. 20 is a circuit diagram showing a structure in which the collectors of the bipolar transistors B1 and B2 are commonly connected. Such a circuit is an emitter follower circuit,
It is often used when you want to obtain a large current.

Such a structure can be realized by performing the slicing process so as to share the diffusion region serving as the collector of the bipolar transistors B1 and B2, that is, the collector wall.

21 to 24 are views showing a second embodiment of the present invention, FIG. 21 is a plan view, FIG. 22 is a sectional view taken along the line X3X3 in FIG. 1, and FIG. 23 is FIG.
FIG. 24 is a sectional view taken along line Y3Y3 in FIG. 24 and FIG. 24 is a sectional view taken along line Z3Z3 in FIG. In addition, FIG. 21 shows D3 of FIG. 23 from the A3A3 direction of FIG.
FIG. 25 is a plan view seen from the 3D3 direction and from the E3E3 direction in FIG. 24.

The semiconductor device shown in the second embodiment is the first
The only difference is that collector walls 5a and 5b of bipolar transistors B1 and B2 in the semiconductor device shown in the embodiment are shared by a single collector wall 5d. In order to realize this, the length of the oxide film portion 22f extending in the X3X3 direction is shorter than that of the first embodiment, and the emitter 15 of the bipolar transistors B1 and B2 is formed.
Although a, 15b, the intrinsic bases 11a, 11b, and the external bases 9a, 9b are divided, the collector wall 5 is not divided.

In such a semiconductor device, in the manufacturing method shown in the first embodiment, the resist film 23 is formed so that the trench 8f (see FIG. 15) does not separate the collector wall 5.
May be patterned.

Further, since it is not necessary to form the aluminum electrode 16b and only the aluminum electrode 16a needs to be formed, it is not necessary to form the contact hole 14b, and the contact hole 14a exists on the extension of the oxide film 22f. Is also good.

(A-3) Third Embodiment FIG. 25 is a circuit diagram showing a bipolar transistor having multiple emitters. Such bipolar transistors are often used in output circuits. Such a configuration can also be realized by manufacturing the bipolar transistors B1 and B2 in a slice process.

26 to 29 are views showing a second embodiment of the present invention, FIG. 26 is a plan view, FIG. 27 is a cross-sectional view as seen from the X4X4 direction in FIG. 26, and FIG. 28 is FIG.
29 is a sectional view taken along the line Y4Y4 in FIG.
FIG. 27 is a cross-sectional view seen from the Z4Z4 direction in FIG. 26.
26 is a plan view seen from the A4A4 direction in FIG. 27, the D4D4 direction in FIG. 28, and the E4E4 direction in FIG. 29.

The semiconductor device shown in the third embodiment is the second one.
The only difference is that the external bases 9a and 9b of the bipolar transistors B1 and B2 in the semiconductor device shown in the embodiment are shared by a single external base 9d. In order to realize this, the oxide film 22f has a shorter length extending in the X3X3 direction as compared with the second embodiment and is divided into the emitters 15a and 15b of the bipolar transistors B1 and B2 and the intrinsic bases 11a and 11b. The collector wall 5 and the external base 9 are not divided.

In such a semiconductor device, the resist film 23 may be patterned in the manufacturing method shown in the first embodiment so that the trench 8f (see FIG. 15) does not separate the collector wall 5 and the external base 9.

Further, since it is not necessary to form the aluminum electrode 16f and only the aluminum electrode 16c needs to be formed, it is not necessary to form the contact hole 14f, and the contact hole 14c exists on the extension of the oxide film 22f. Is also good.

B. Examples for MOS transistors:
The present invention is not limited to bipolar transistors,
It can also be applied to MOS transistors.

(B-1) Fourth embodiment: FIGS. 30 to 32.
FIG. 30 is a diagram showing a fourth embodiment of the present invention, FIG. 30 is a plan view, FIG. 31 is a sectional view seen from the X5X5 direction in FIG. 30, and FIG. 32 is a sectional view seen from the Y5Y5 direction in FIG. is there. Further, FIG. 30 is a plan view seen from the A5A5 direction in FIG. 31 and the D5D5 direction in FIG.

On the P-conductivity type substrate 1, an N-conductivity type diffusion layer (well) 40 is formed. A field oxide film 4 defining an active region is provided on the well 40 so as to extend in the Y5Y5 direction, and source regions 42a, 42b, 42c and drain regions 44a, 44b, 44c are sandwiched by the field oxide film 4. Has been formed. The source region and the drain region can be replaced with each other.

The gate oxide film 43a is sandwiched between the source region 42a and the drain region 44a, the gate oxide film 43b is sandwiched between the source region 42b and the drain region 44b, and the gate oxide film 43b is sandwiched between the source region 42c and the drain region 44c. The films 43c are formed respectively. Gates 41a, 41b and 41c are provided on the gate oxide films 43a, 43b and 43c, respectively.

Source region 42a, drain region 44a,
And a gate 41a, a PMOS transistor M1, a source region 42b, a drain region 44b, and a gate 41b.
Form a PMOS transistor M2, and the source region 42c, the drain region 44c, and the gate 41c form a PMOS transistor M3. The gate width of each of the PMOS transistors M1, M2, M3 is W1,
W2 and W3, and the gate lengths are both L.

Aluminum electrodes 36b, 36f and 36j are respectively provided in the source regions 42a, 42b and 42c, and aluminum electrodes 3 are respectively provided in the drain regions 44a, 44b and 44c.
6d, 36h, 36l, and gates 41a, 41
Aluminum electrodes 36c, 36g and 3 are provided on b and 41c, respectively.
6k is electrically connected.

On the other hand, aluminum electrodes 36a, 36e and 36i are electrically connected to the well 40 in each of the PMOS transistors M1, M2 and M3.

The oxide films 32a and 32b are provided so as to extend in the Y5Y5 direction, and the oxide films 32c and 32d are X.
It is provided so as to extend in the 5X5 direction and separates the PMOS transistors M1, M2 and M3 from other elements. Further, the oxide film 32e connects the PMOS transistors M1 and M2 to
The oxide film 32f isolates the PMOS transistors M2 and M3 from each other.

Such transistors M1, M2, M3
Can be manufactured as follows.

33 to 49 are cross-sectional views showing the method of manufacturing the semiconductor device shown in FIGS. 30 to 32 in the order of steps, and FIGS. 33, 35, 37, 39, 41 and 4.
4, FIG. 46, and FIG. 48 all correspond to FIG. 31, and FIG.
36, 38, 40, 42, 45, 47, and 49 all correspond to FIG.

First, a well 40, which is a diffusion layer containing impurities of N conductivity type, is formed on the substrate 1 by epitaxial growth, and then this is selectively oxidized to form a field oxide film 4 extending in the Y5Y5 direction (see FIG. 33, FIG.
4).

Then, the entire surface of the wafer is oxidized to form a gate oxide film 43. Next, a polysilicon film 45 containing impurities of N conductivity type is formed on the entire surface of the wafer by the CVD method (FIGS. 35 and 36).

After that, photolithography is performed to form the polysilicon film 4
5 is selectively etched to form a gate 41. At this time, the gate oxide film 43 is not etched. Further, photoengraving is performed to selectively ion-implant P-conductivity type impurities to form a source region 42 and a drain region 44 (FIGS. 37 and 38).

After that, the interlayer film 12 is formed (FIGS. 39 and 40). In this embodiment, the steps up to here are master steps. That is, a master is one in which a PMOS transistor having a gate width longer than the total gate width W1, W2, W3 of the PMOS transistors M1, M2, M3 is formed. Prior to the customer's order, a master having such a structure is prepared.

Next, the resist film 51 is patterned by photolithography, and the interlayer film 12 and the field oxide film 4 are anisotropically etched using this as a mask to form the trenches 38a to 38f. The etching is performed until the gate 41 made of polysilicon is exposed. At this time, the anisotropic etching of the field oxide film 4 may be stopped halfway (FIGS. 41 and 42).

FIG. 43 is a cross-sectional view of a portion where the drain region 44 is present, viewed from the same direction as FIG. 42. Gate 41
Exposure of the oxide film ends the etching of the oxide film,
In the trenches 38c, 38e, 38f, 38d,
As shown by the broken line in FIG. 41 and as shown in FIG. 43, the interlayer film 12 is slightly left on the drain region 44. Similarly, the interlayer film 12 is left on the well 40 and the source region 42.

After that, the resist film 51 is removed, and anisotropic etching of polysilicon is performed using the interlayer film 12 as a mask. As a result, the gate 41 becomes the gates 41a, 41
b, 41c. After that, anisotropic etching of the oxide film is performed to divide the gate oxide film 43 into gate oxide films 43a, 43b and 43c. At this time, the field oxide film 4 is also etched and the trenches 38a to 38f are etched.
Extends in the depth direction (FIGS. 44 and 45). FIG.
Well 40 and source region 4 indicated by broken lines in FIG.
2. The interlayer film 12 left on the drain region 44 is removed.

Next, using the interlayer film 12 as a mask, the well 4 is formed.
0, the source region 42, and the drain region 44 are etched by using anisotropic etching of silicon to form the trench 38a.
Extend until ~ 38f reaches substrate 1. by this,
The source region 42 is the source regions 42a, 42b, 42c.
The drain region 44 is divided into 44a, 44b, and 44c. The well 40 is also divided. This allows PMOs with gate widths of W1, W2 and W3, respectively.
S transistors M1, M2 and M3 are formed (FIG. 4).
6, FIG. 47).

Thereafter, an oxide film is formed on the entire surface of the wafer by the CVD method, and the entire surface of the wafer is etched back to form oxide films 32a to 32f in the trenches 38a to 38f, respectively.
f is filled (FIGS. 48 and 49).

Thereafter, the contact holes are selectively punched,
Aluminum alloy film is formed on the entire surface by sputtering method,
By selectively etching, the aluminum electrodes 36a ...
36l is formed (FIGS. 31 and 32).

As described above, also in the fourth embodiment, the first
A transistor having a relatively long gate width is formed in the master process in the same manner as in the embodiment, and is divided into a plurality of transistors having a relatively short gate width in the slicing process, so that the semiconductor element of the semiconductor device is sliced in the slicing process. There is an effect that the size can be freely designed according to the customer's request.

(B-2) Fifth Embodiment: In the embodiment relating to the MOS transistor as well, similar to the second and third embodiments, the connection of a plurality of transistors can be performed in the slicing process without using wiring. it can.

For example, FIG. 50 shows a MOS transistor M.
It is a circuit diagram which shows the structure which the drains of 1 and M2 were connected in common. Alternatively, it is a circuit diagram showing a configuration in which sources are commonly connected. Further, FIG. 51 is a circuit diagram showing a configuration in which the drain of the MOS transistor M1 and the source of M2 are commonly connected. Such a circuit is a sense amplifier,
Used as a part of NAND circuit.

Such a structure has the MOS transistor M
This can be realized by performing a slicing process so that the diffusion regions that can serve as the drains and the sources of M1 and M2, that is, the source region and the drain region are shared.

52 to 55 are views showing a fifth embodiment of the present invention, and show a semiconductor device which realizes the structure shown in FIG.

52 is a plan view, FIG. 53 is a sectional view taken along the X6X6 direction in FIG. 52, FIG. 54 is a sectional view taken along the Y6Y6 direction in FIG. 52, and FIG. 55 is taken along the Z6Z6 direction in FIG. FIG. Further, FIG. 52 is taken from the direction A6A6 of FIG.
FIG. 56 is a plan view seen from the E6E6 direction in FIG. 55 from the 6D6 direction.

The semiconductor device shown in the fifth embodiment is similar to the fourth embodiment.
The only difference is that the drain regions 44a and 44b of the MOS transistors M1 and M2 in the semiconductor device shown in the embodiment are shared by a single drain region 44d. To achieve this, the oxide film 32e has a shorter length extending in the X6X6 direction as compared with the fourth embodiment, and the gates 41a and 41b of the MOS transistors M1 and M2, the gate oxide films 43a and 43b, and the source region 42a are formed. , 42
Although b is divided, the drain region 44 is not divided.

In such a semiconductor device, in the manufacturing method shown in the fourth embodiment, the resist film 51 is formed so that the trench 38e (see FIG. 47) does not separate the drain region 44.
May be patterned.

Further, it is not necessary to form the aluminum electrode 36h, only the aluminum electrode 36d may be formed, and the aluminum electrode 36d may be present on the extension of the oxide film 32e.

Further, as shown in FIG. 52, the oxide film 3
2e is a well 4 for the MOS transistors M1 and M2
It is possible not to separate 0s. Such a semiconductor device can be easily realized by changing the patterning of the resist film 51. In this case, it is not necessary to form the aluminum electrode 36e, and the aluminum electrode 3e
It is only necessary to form 6a, and the aluminum electrode 36a may be present on the extension of the oxide film 32e.

Similarly, MOS transistors M1 and M2
, The source of the MOS transistor M1 and the source of the MOS transistor M2 are shared by using the source region 42 as the drain and the drain region 44 as the source. You can

(B-3) Sixth Embodiment: FIG. 56 shows M.
It is a circuit diagram showing a configuration in which the drains of the OS transistors M1 and M2 are connected in common and the sources are also connected in common. Alternatively, it is a circuit diagram showing a configuration in which sources are commonly connected. Such a circuit is used as a part of a current mirror circuit or a NAND circuit.

Such a structure has a MOS transistor M
This can be realized by performing a slicing process so that the diffusion regions that can serve as the drains and the sources of M1 and M2, that is, the source region and the drain region are shared.

57 to 60 are views showing a sixth embodiment of the present invention, and show a semiconductor device which realizes the structure shown in FIG.

57 is a plan view, FIG. 58 is a cross-sectional view seen from the direction X7X7 in FIG. 57, FIG. 59 is a cross-sectional view seen from the direction Y7Y7 in FIG. 57, and FIG. 60 is seen from the direction Z7Z7 in FIG. FIG. Further, FIG. 57 is taken from the direction A7A7 of FIG.
It is the top view seen from the 7D7 direction and the E7E7 direction of FIG.

The semiconductor device shown in the sixth embodiment is the fifth embodiment.
The only difference is that the source regions 42a and 42b of the MOS transistors M1 and M2 in the semiconductor device shown in the embodiment are shared by a single source region 42d.
In order to realize this, the oxide film 32e has a shorter length extending in the X6X6 direction as compared with the fifth embodiment, and divides the gates 41a and 41b and the gate oxide films 43a and 43b of the MOS transistors M1 and M2. However, the drain region 44 and the source region 42 are not divided.

In such a semiconductor device, in the manufacturing method shown in the fourth embodiment, the resist film 51 may be patterned so that the trench 38e (see FIG. 47) does not separate the source region 42 and the drain region 44.

Further, it is not necessary to form the aluminum electrode 36f, only the aluminum electrode 36b may be formed, and the aluminum electrode 36b may be present on the extension of the oxide film 32e.

(B-4) Seventh Embodiment: FIG. 61 shows M.
FIG. 6 is a circuit diagram showing a configuration in which gates of OS transistors M1 and M2 are commonly connected. Such a circuit is used as a part of the current mirror circuit.

Such a structure has a MOS transistor M
It can be realized by performing the slicing process so that the gates of 1 and M2 are shared.

62 to 65 are views showing a seventh embodiment of the present invention, and show a semiconductor device which realizes the structure shown in FIG.

62 is a plan view, FIG. 63 is a cross-sectional view seen from the X8X8 direction in FIG. 62, FIG. 64 is a cross-sectional view seen from the Y8Y8 direction in FIG. 62, and FIG. 65 is a Z8Z8 direction from the FIG. FIG. Further, FIG. 62 is taken from the direction A8A8 of FIG.
FIG. 66 is a plan view seen from the 8D8 direction and seen from the E8E8 direction in FIG. 65.

The semiconductor device shown in the seventh embodiment is the same as the fourth embodiment.
The only difference is that the gates 41a and 41b and the gate oxide films 43a and 43b of the MOS transistors M1 and M2 in the semiconductor device shown in the embodiment are shared by a single gate 41d and a gate oxide film 43d, respectively. In order to realize this, the oxide film 32e of the fourth embodiment is used.
Are replaced with oxide films 32g and 32h. And
The oxide film 32g divides the source regions 42a and 42b and the drain regions 44a and 44b of the MOS transistors M1 and M2, but the gate 41 and the gate oxide film 43.
Is not divided.

In such a semiconductor device, in the manufacturing method shown in the fourth embodiment, the resist film 51 may be patterned so that the trench 38e (see FIG. 47) does not separate the gate 41 and the gate oxide film 43.

Further, it is not necessary to form the aluminum electrode 36g, only the aluminum electrode 36c may be formed, and the aluminum electrode 36c may be present between the oxide films 32g and 32h.

Further, as shown in FIG. 62, the oxide film 3
2g is well 4 for MOS transistors M1 and M2
It is possible to avoid separating 0s. Such a semiconductor device can be easily realized by changing the patterning of the resist film 51. In this case, it is not necessary to form the aluminum electrode 36e, and the aluminum electrode 3e
It is only necessary to form 6a, and the aluminum electrode 36a may be present on the extension of the oxide films 32g and 32h.

(B-5) Eighth Embodiment: FIG.
FIG. 9 is a circuit diagram showing a configuration in which the gates of OS transistors M1 and M2 are commonly connected and the sources thereof are commonly connected. Alternatively, it is a circuit diagram showing a configuration in which gates are commonly connected and drains are commonly connected. Such a circuit is used as a part of the current mirror circuit.

The MOS transistor M having such a configuration
It can be realized by performing a slicing process so that the gate and source regions of 1 and M2 are shared.

67 to 70 are views showing an eighth embodiment of the present invention, and show a semiconductor device which realizes the structure shown in FIG.

67 is a plan view, FIG. 68 is a sectional view seen from the X9X9 direction in FIG. 67, FIG. 69 is a sectional view seen from the Y9Y9 direction in FIG. 67, and FIG. 70 is a view from the Z9Z9 direction in FIG. FIG. Further, FIG. 67 is taken from the direction A9A9 in FIG.
FIG. 70 is a plan view seen from the direction 9D9 and the direction E9E9 in FIG. 69.

The semiconductor device shown in the eighth embodiment is the seventh embodiment.
The only difference is that the source regions 42a and 42b of the MOS transistors M1 and M2 in the semiconductor device shown in the embodiment are shared by a single source region 42d. In order to realize this, the oxide film 32g of the seventh embodiment is not provided. The oxide film 32h divides the drain regions 44a and 44b of the MOS transistors M1 and M2, but does not divide the gate 41, the gate oxide film 43, and the source region 42.

In such a semiconductor device, in the manufacturing method shown in the fourth embodiment, the resist film 51 is patterned so that the trench 38e (see FIG. 47) does not separate the gate 41, the gate oxide film 43 and the source region 42. Good.

Further, it is not necessary to form the aluminum electrodes 36f and 36g, only the aluminum electrodes 36b and 36c may be formed, and the aluminum electrodes 36b and 36c may be present on the extension of the oxide film 32h.

(B-6) Ninth Example: In the fourth example, the field oxide film 4, the source region 42, the drain region 44 and the gate 41 were in direct contact with the interlayer film 12. However, by providing the nitride film 60 as a base of the interlayer film 12, the depth of the trench filled with the oxide films 32a, 32b, ... Can be formed with good controllability.

71 to 73 are views showing a ninth embodiment of the present invention, FIG. 71 is a plan view, FIG. 72 is a sectional view taken along the line X10X10 in FIG. 71, and FIG. It is sectional drawing seen from the Y10 Y10 direction. In addition, FIG. 71 is from the A10A10 direction of FIG.
It is the top view seen from the D10D10 direction of FIG.

71 to 73 respectively correspond to FIGS. 30 to 32 shown in the fourth embodiment, but only one MOS transistor M4 and its vicinity are shown for simplification. It goes without saying that the same configuration can be adopted for other MOS transistors.

The MOS transistor M4 shown in the ninth embodiment differs from the MOS transistor M1 shown in the fourth embodiment only in that a nitride film 60 is present as a base of the interlayer film 12.

74 to 89 are cross-sectional views showing the method of manufacturing the semiconductor device shown in FIGS. 71 to 73 in the order of steps, and FIGS. 74, 76, 78, 80, 82, and 8.
4, FIG. 86, and FIG. 88 all correspond to FIG. 72, and FIG.
77, 79, 81, 83, 85, 87, and 89 all correspond to FIG. 73.

First, a well 40, which is a diffusion layer containing impurities of N conductivity type, is formed on the substrate 1 by epitaxial growth, and then this is selectively oxidized to form a field oxide film 4 extending in the Y10Y10 direction (FIG. 74, FIG. 75).

Then, the entire surface of the wafer is oxidized to form a gate oxide film 43. Next, a polysilicon film 45 containing impurities of N conductivity type is formed on the entire surface of the wafer by the CVD method (FIGS. 76 and 77).

After that, photolithography is performed to form the polysilicon film 4
5 is selectively etched to form a gate 41. Further, photoengraving is performed to selectively implant P-conductivity type ions to form a source region 42 and a drain region 44 (FIGS. 78 and 79).

Thereafter, the nitride film 60 is formed by the CVD method, and further the interlayer film 12 is formed by the CVD method (FIG. 8).
0, FIG. 81). In this embodiment, the steps up to here are master steps. That is, the master in which the PMOS transistor having the gate width longer than the gate width W4 of the PMOS transistor M4 is formed is the master. Prior to the customer's order, a master having such a structure is prepared.

Next, the resist film 51 is patterned by photolithography, and a gas having a high etching selection ratio of the oxide film to the nitride film, for example, a fluorine-based gas containing a large amount of carbon is used until the nitride film 60 is exposed using the resist film 51 as a mask. Etching is performed by using the trenches 38a, 38b, 38
C and 38e are perforated (FIGS. 82 and 83).

Then, the nitride film 60 is anisotropically etched using a gas having a high etching selection ratio of the nitride film to the oxide film, for example, a fluorine-based gas, until the gate 41, the field oxide film 4 and the gate oxide film 43 are exposed. Trench 3
8a, 38b, 38c, 38e are dug down. afterwards,
Further, using the nitride film 60 as a mask, the gate 41 which is polysilicon is anisotropically etched using a gas having a high etching selection ratio of polysilicon to the oxide film, for example, a chlorine-based gas (FIGS. 84 and 85).

The features of this embodiment will now be described in comparison with the fourth embodiment. The interlayer film 12 sandwiched between the trench 38c and the drain region 44 shown in FIG. 43 of the fourth embodiment.
Consider the case where all are etched. In this case, when the gate 41 is selectively removed by the subsequent etching of polysilicon, the source region 42 and the drain region 4 are removed.
4 is etched to further extend the trench 38c and the like.
On the other hand, since the bottoms of the trenches 38a and 38b are in contact with the field oxide film 4, they are not extended by the etching of polysilicon. Therefore, in the fourth embodiment, the trench 38c
If the interlayer film 12 sandwiched between the drain region 44 and the like is completely etched, the depth of all the trenches cannot be made uniform and the breakdown voltage of the transistor may become unstable.

However, in this embodiment, since the nitride film 60 exists, even if the interlayer film 12 sandwiched between the trench 38c and the drain region 44 is completely etched, the nitride film serves as a mask and the gate made of polysilicon is used. Even if 41 is anisotropically etched, the source region 42 and the drain region 44 are not etched.

Thereafter, the field oxide film 4 and the gate oxide film 43 are anisotropically etched by using a gas having a high etching selection ratio of the oxide film with respect to silicon, for example, a fluorine-based gas, and the trenches 38a, 38b, 38c and 38e are dug down. Further, the well 40, the source region 42, the drain region 44, and the substrate 1 are anisotropically etched by using a gas having a high etching selection ratio of silicon to the oxide film to dig down the trenches 38a, 38b, 38c, 38e (FIG. 8).
6, FIG. 87).

After that, an oxide film is formed on the entire surface of the wafer, and the entire surface is etched back to form trenches 38a and 3a.
8b, 38c, and 38e have oxide films 32a and 32, respectively.
b, 32c and 32e are filled (FIGS. 88 and 89).

Thereafter, the contact holes are selectively punched,
Aluminum alloy film is formed on the entire surface by sputtering method,
By selectively etching, the aluminum electrodes 36a ...
36d is formed (FIGS. 72 and 73).

As described above, in this embodiment, it is easier to make the depth of the trench uniform as compared with the fourth embodiment.
It is possible to prevent the breakdown voltage of the transistor from becoming unstable.

C. Embodiments for PN diodes: The invention can be applied not only for transistors but also for diodes.

(C-1) Tenth Embodiment: FIGS. 90 to 9
FIG. 2 is a diagram showing a tenth embodiment of the present invention, FIG. 90 is a plan view, FIG. 91 is a sectional view seen from the X11X11 direction in FIG. 90, and FIG. 92 is Y11Y1 in FIG.
It is sectional drawing seen from 1 direction. Also, FIG. 90 corresponds to FIG.
92 is a plan view seen from the direction A11A11 of FIG.

The oxide films 52a, 52b, 52c and 52d separate the PN diodes J1, J2 and J3 from other elements, the oxide film 52e the PN diodes J1 and J2, and the oxide film 52f the PN diodes J2 and J3. They are separated from each other.

An N-conductivity type epitaxial layer 3 is provided on a P-conductivity type substrate 1, and P-conductivity type impurity diffusion layers 56a, 56b and 56c and N-conductivity type impurity diffusion layers 57a and 57b are provided on the epitaxial layer 3. , 57c are formed. Aluminum electrodes 59b, 59d, and 59f are provided on the impurity diffusion layers 56a, 56b, and 56c, respectively.
Aluminum electrodes 59a, 59c, 5 are provided on a, 57b, 57c.
9e are electrically connected to each other. The impurity diffusion layers 56a, 56b, 56c function as anode regions, and the impurity diffusion layers 57a, 57b, 57c function as cathode regions, respectively.

PN diode J having such a structure
1, J2 and J3 are impurity diffusion layers 56a and 57, respectively.
A has a PN junction between a, between the impurity diffusion layers 56b and 57b, and between the impurity diffusion layers 56c and 57c. The formation of such a PN diode will be described below by taking the PN diode J1 as an example. The other PN diodes J2 and J3 can be similarly manufactured.

93 to 100 are sectional views showing a method of manufacturing the semiconductor device shown in FIGS. 90 to 92 in the order of steps, and FIGS. 93, 95, 97 and 99 are all shown in FIG.
94, 96, 98, and 100 all correspond to FIG. 92.

First, the epitaxial layer 3 containing N-conductivity type impurities is formed on the substrate 1 by Si epitaxial growth (FIGS. 93 and 94).

After that, a P-conductivity type impurity is introduced into the epitaxial layer 3 by an ion implantation method to form a P-conductivity type impurity diffusion layer 56 (FIGS. 95 and 96). Then, the resist film 702 is patterned by photolithography, and N-conductivity type impurities are introduced into the epitaxial layer 3 by using the ion-implantation method using the resist film 702 as a mask to form the N-conductivity type impurity diffusion layer 57 (FIG. 97, FIG. 97). (Fig. 98). After that, the resist film 702 is removed and the interlayer film 12 is formed to obtain a master (FIGS. 99 and 100).

In the subsequent slicing process, the first embodiment was used.
Similarly, the trenches 58a to 58f are drilled until reaching the substrate 1, an oxide film is formed on the entire surface and etched back to form oxide films 52a to 52f for filling the trenches, and then the interlayer film 12 is selected. To form contact holes, which are then filled with aluminum to form aluminum electrodes 59a to 59f (FIGS. 90 to 92).

[0209] Here, in the slicing step, the trench 5 is formed.
The size of the PN diode J1 can be changed by appropriately selecting the intervals of 8e and 58c.

Therefore, as in the case of the transistor, the size of the semiconductor element can be freely designed in accordance with the customer's request in the slicing process.

D. Embodiments relating to resistors: The invention can be applied not only for transistors but also for resistors.

(D-1) Eleventh Embodiment: FIGS. 101 to 103 are views showing an eleventh embodiment of the present invention.
01 is a plan view, and FIG. 102 is X12X1 in FIG.
103 is a cross-sectional view seen from two directions, and FIG. 103 is a cross-sectional view seen from the Y12Y12 direction in FIG. In addition, FIG. 101 is taken from the direction of A12A12 of FIG.
12 is a plan view seen from the direction D12D12 of FIG.

The oxide films 72a, 72b, 72c and 72d separate the resistors R1, R2 and R3 from other elements, and the oxide film 7
2e is resistors R1 and R2, and oxide film 72f is resistors R2 and R2.
3 are separated from each other.

An N-conductivity type epitaxial layer 3 is provided on a P-conductivity type substrate 1, and P-conductivity type impurity diffusion layers 50a, 50b and 50c are selectively provided on the epitaxial layer 3.

An aluminum electrode 76 is formed on the impurity diffusion layer 50a.
a and 76b are aluminum electrodes 76 in the impurity diffusion layer 50b.
d and 76e are aluminum electrodes 76 in the impurity diffusion layer 50c.
g and 76h are electrically connected to each other, and each of the impurity diffusion layers 50a, 50b and 50c functions as a resistor.

Aluminum electrodes 76c, 76f and 76i are electrically connected to the epitaxial layer 3. A potential difference is given between these electrodes and the aluminum electrodes 76a, 76d, and 76g, respectively, and the N conductive type epitaxial layer 3 is formed.
And a P-conductivity-type impurity diffusion layer 50a, 50b, 50c are used to apply a reverse bias. Due to this reverse bias, the impurity diffusion layers 50a, 50b, 50c are used while being insulated from the epitaxial layer 3.

The resistors R1, R2 and R3 can be formed on the same substrate 1 simultaneously with the formation of the bipolar transistor shown in the first embodiment.

FIGS. 104 to 119 are the same as FIGS.
FIG. 104 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG.
0, FIG. 112, FIG. 114, FIG. 116, and FIG. 118 all correspond to FIG. 102, and FIG. 105, FIG. 107, FIG. 109, FIG. 111, FIG. 113, FIG. 115, FIG. 117, and FIG. It corresponds to. And FIG. 104 thru | or FIG.
19 corresponds to FIGS. 4 to 19 of the first embodiment, respectively.

In the first embodiment, proceeding to the steps shown in FIGS. 4 and 5, the epitaxial layer 3 is formed on the substrate 1 in the portion where the resistor is formed (FIGS. 104 and 105).

Then, when the resist film 7 is patterned as shown in FIGS. 6 and 7, the resist film 7 is also patterned in the portion where the resistor is formed (FIG. 1).
06, FIG. 107). The portion where the resist film 7 is left is a portion secured so that the aluminum electrodes 76c, 76f and 76i are electrically connected to the epitaxial layer 3 later.

Next, as shown in FIGS. 6 and 7, when the external base 9 is formed, the impurity diffusion layer 50 is simultaneously formed. That is, the impurity diffusion layer 50 is also formed by ion implantation of P conductivity type impurities for forming the external base 9.

After that, when the resist film 10 is patterned as shown in FIGS. 8 and 9, the resist film 10 is formed on the entire surface in the portion where the resistance is formed (FIG. 1).
08, 102). Therefore, even if the ion implantation for forming the intrinsic base 11 is performed in the portion where the bipolar transistor is formed, the ion implantation is not performed in the portion where the resistance is formed.

Further, when the resist film 19 is patterned as shown in FIGS. 10 and 11, the resist film 19 is formed on the entire surface where the resistor is formed (FIGS. 110 and 104). Therefore, even if the ion implantation for forming the emitter 15 is performed in the portion where the bipolar transistor is formed, the ion implantation is not performed in the portion where the resistance is formed.

Thereafter, the entire surface of the epitaxial layer 3 and the impurity diffusion layer 50 is covered by forming the interlayer film 12 shown in FIGS. 12 and 13 (FIGS. 112 and 113).

After that, the patterning of the resist film 23 exhibits the patterns shown in FIGS. 14 and 15, and FIGS. 114 and 115. By using this as a mask, the trenches 8a to 8h and the trenches 78a to 78h are simultaneously formed.
f is perforated.

16 and 17, the oxide film 2 is formed.
2a to 22h are filled with the oxide films 72a to 72a.
72f is filled.

The patterning of the resist film 13 exhibits the patterns shown in FIGS. 18 and 19, and 118 and 119. By using this as a mask, the contact holes 74a to 74h are formed at the same time as the contact holes 14a to 14h.

After that, the contact holes 74a to 74h are filled with an aluminum alloy to form aluminum electrodes 76a to 76h.

Therefore, also in this embodiment, similarly to the case of the transistor, there is an effect that the resistor size can be freely designed in accordance with the customer's request in the slicing process.

Further, since the impurity diffusion layer 50 is also formed by ion implantation of the P conductivity type impurity for forming the external base 9, it is easy to form the impurity diffusion layer 50 in the master having the bipolar transistor.

(D-2) Twelfth Embodiment: FIGS. 120 to 122 are views showing a twelfth embodiment of the present invention.
20 is a plan view, and FIG. 121 is X13X1 in FIG.
FIG. 122 is a cross-sectional view seen from three directions, and FIG. 122 is a cross-sectional view seen from the Y13Y13 direction in FIG. 120. Further, FIG. 120 is taken from the direction of A13A13 of FIG.
13 is a plan view seen from the direction D13D13 of FIG.

Oxide films 82a, 82b, 82c and 82d separate resistors R4, R5 and R6 from other elements, and oxide film 8a.
2e is resistors R4 and R5, and oxide film 82f is resistors R5 and R5.
6 are separated from each other.

An N-conductivity type well 40 is provided on a P-conductivity type substrate 1, a field oxide film 4 is formed on the N-conductivity well 40, and polysilicon films 45a, 45b, 45c into which predetermined impurities have been introduced. Is provided.

An aluminum electrode 86 is formed on the polysilicon film 45a.
a and 86b are aluminum electrodes 8 on the polysilicon film 45b.
6c and 86d are electrically connected to the polysilicon film 45c, and aluminum electrodes 86e and 86f are electrically connected to the polysilicon film 45c.
Each of the polysilicon films 45a, 45b, 45c functions as a resistor. The field oxide film 4 serves to insulate the polysilicon films 45a, 45b, 45c from the well 40.

The resistors R4, R5 and R6 are formed on the same substrate 1 simultaneously with the formation of the MOS transistor shown in the fourth embodiment.
Can be formed on.

123 to 138 are the same as FIGS. 120 to 1.
FIG. 12C is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG.
9, FIG. 131, FIG. 133, FIG. 135 and FIG. 137 all correspond to FIG. 121, and FIG. 124, FIG. 126, FIG. 128, FIG. 130, FIG. 132, FIG. 134, FIG. 136 and FIG. It corresponds to. 123 to 1
32 corresponds to FIGS. 33 to 42 of the fourth embodiment, and FIGS. 133 to 138 refer to FIGS. 44 to 49, respectively.
It corresponds to.

In the fourth embodiment, when the process shown in FIGS. 33 and 34 is performed, the well 40 is formed on the substrate 1 and the field oxide film 4 is selectively formed thereon. At this time, the field oxide film 4 is formed on the entire surface in the region where the resistance is to be formed (FIGS. 123 and 124).

Next, corresponding to FIGS. 35 and 36, a polysilicon film 45 containing impurities of N conductivity type is formed on the entire surface of the wafer (FIGS. 125 and 126).

Then, in the region where the MOS transistor is to be formed, photoengraving is performed to selectively etch the polysilicon film 45 to form the gate 41 (FIG. 37,
38), the region where the resistance is formed is not etched but left as it is (FIGS. 127 and 128).

After that, the interlayer film 12 is formed on the entire surface (FIGS. 129 and 130), the resist film 51 is patterned thereon, and the interlayer film 12 is selectively etched to form the trench 38a (FIG. 41, FIG. 41, etc.). At the same time, trenches 88a to 88f are drilled (FIGS. 131 and 13).
2).

Simultaneously with the step of transitioning from the state shown in FIGS. 41 to 43 to the state shown in FIGS. 44 and 45, the polysilicon film 45 and the field oxide film 4 are etched to form the trenches 88a to 88f. Grows (FIGS. 133 and 134).

Further, the well 40 and the substrate 1 are etched to extend the trenches 88a to 88f (FIGS. 135 and 13).
6), and these are filled with oxide films 82a to 82f, respectively (FIGS. 137 and 138). After that, a contact hole is bored in the interlayer film 12 and an aluminum alloy is filled to fill the aluminum electrode 86.
a to 86f are formed.

Therefore, also in this embodiment, similarly to the case of the transistor, there is an effect that the resistor size can be freely designed in accordance with the customer's request in the slicing process.

Further, the polysilicon film 45 for forming the gate 41 serves as a resistor, and the polysilicon film 45 serves as a resistor.
Since a, 45b, and 45c are also formed, they can be easily formed in the master having the MOS transistor.

E. Embodiments Regarding Capacitance: (e-1) Thirteenth Embodiment: The present invention can be applied not only to transistors but also to capacitors.

139 to 141 show a thirteenth embodiment of the present invention.
FIG. 139 is a view showing an example, FIG. 139 is a plan view, FIG. 140 is a cross-sectional view seen from the X14X14 direction in FIG. 139, and FIG. 141 is a cross-sectional view seen from the Y14Y14 direction in FIG. Also, FIG. 139 shows A1 of FIG.
FIG. 141 is a plan view seen from the direction D14D14 of FIG. 141 from the direction 4A14.

The oxide films 92a, 92b, 92c and 92d separate the capacitors C1, C2 and C3 from other elements, and the oxide film 9
2e represents the capacitances C1 and C2, and the oxide film 92f represents the capacitances C2 and C.
3 are separated from each other.

An N-conductivity type well 40 is provided on the P-conductivity type substrate 1, and an N-conductivity type high-concentration impurity diffusion layer 91a, 91b, 91c, 95a, 95 is further provided on the well 40.
b and 95c are selectively formed. An oxide film 93 is formed on the impurity diffusion layers 95a, 95b, 95c, respectively.
Polysilicon films 94a, 94b, 94c containing impurities of N conductivity type are provided via a, 93b, 93c.

The impurity diffusion layers 91a, 91b, 91c function as electrode lead layers for the impurity diffusion layers 95a, 95b, 95c, respectively, and the aluminum electrodes 96a, 9b are provided respectively.
6c and 96e are electrically connected. On the other hand, aluminum electrodes 96b, 96d, 96f are electrically connected to the polysilicon films 94a, 94b, 94c, respectively.

A capacitor C1 is placed between the aluminum electrodes 96a and 96b, and a capacitor C2 is placed between the aluminum electrodes 96c and 96d.
, And a capacitance C3 between the aluminum electrodes 96e and 96f.
Are formed respectively.

The capacitors C1, C2 and C3 can be formed on the same substrate 1 in substantially the same manner as the MOS transistor shown in the fourth embodiment.

142 to 157 are shown in FIGS. 139 to 1.
FIG. 42 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 41 in the order of steps, and FIGS. 142, 144, 146, and 14;
8, FIG. 150, FIG. 152, FIG. 154, and FIG. 156 all correspond to FIG. 140, and FIG. 143, FIG. 145, FIG. 147, FIG. 149, FIG. 151, FIG. 153, FIG. 155, and FIG. It corresponds to.

First, the well 40 is formed on the substrate 1, and the N-conductivity type impurity is introduced into the well 40 at a high concentration by the ion implantation method. As a result, the impurity diffusion layer 95 is formed (FIGS. 142 and 143).

Then, the structure obtained in the above process is oxidized to obtain an oxide film 93, and a polysilicon film 94 containing impurities of N conductivity type is formed (FIGS. 144 and 145).

The polysilicon film 94 and the oxide film 93 are selectively etched to expose the impurity diffusion layer 95, and N-conductivity type impurities are introduced thereinto at a high concentration by an ion implantation method. As a result, the impurity diffusion layer 91 is formed (FIGS. 146 and 147).

An interlayer film 12 is formed on the entire surface of the structure thus obtained (FIGS. 148 and 149), and a resist film 99 is formed.
Is patterned, and the interlayer film 12 is selectively etched using this as a mask. Thereby, the trench 98a-
98f is perforated (FIGS. 150 and 151).

Further, the polysilicon film 94 and the oxide film 93 are etched to extend the trenches 98a to 98f, and the polysilicon films 94a to 94c and the oxide films 93a to 93f, respectively.
93c is formed. Further, the impurity diffusion layer 91 is exposed (FIGS. 152 and 153).

Further, the impurity diffusion layer 91, the well 40 and the substrate 1 are etched to extend the trenches 98a to 98f to form the impurity diffusion layers 91a to 91c (FIGS. 154 and 155).

Then, each of trenches 98a to 98f is filled with oxide films 92a to 92f (FIGS. 156 and 15).
7). Then, the interlayer film 12 is selectively etched to form contact holes, and an aluminum alloy is filled in the contact holes to form aluminum electrodes 96a to 96f.

Therefore, also in this embodiment, similarly to the case of the transistor, there is an effect that the capacity size can be freely designed in accordance with the customer's request in the slicing process.

[0261]

In the semiconductor device according to claim 1 of the present invention, the size of the semiconductor element can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 2 of the present invention, the size of the bipolar transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 3 of the present invention, the emitter length of the bipolar transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 4 of the present invention, the first bipolar transistor and the second bipolar transistor having the collectors connected to each other are formed without connecting the collectors to each other by wiring. You can

In the semiconductor device according to claim 5 of the present invention, a bipolar transistor having a multi-emitter structure can be formed by dividing the emitter region by the third insulating wall.

In the semiconductor device according to claim 6 of the present invention, the size of the diode can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 7 of the present invention, the resistance size can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 8 of the present invention, the resistance can be formed at the same time when the bipolar transistor is formed.

In the semiconductor device according to claim 9 of the present invention, the resistance can be simultaneously formed when forming the MOS transistor.

In the semiconductor device according to claim 10 of the present invention, the size of the semiconductor element can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 11 of the present invention, the size of the MOS transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device according to claim 12 of the present invention, the gate width of the MOS transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In a semiconductor device according to a thirteenth aspect of the present invention, as a first case, the first MOS transistor and the second MOS transistor having drains connected to each other are connected to each other with wirings between the drains. Can be formed without performing.

In the second case, the first MOS transistor and the second M-transistor having sources connected to each other are provided.
The OS transistor can be formed without connecting the sources with wiring.

Further, as a third case, a structure in which the source of the first MOS transistor and the drain of the second MOS transistor are connected can be realized without connecting them by wiring.

In the semiconductor device according to claim 14 of the present invention, the first MOS transistor and the second MOS transistor each having a drain connected to each other and a source connected to each other are provided at the drain and the source. It can be formed without connecting each other with wiring.

According to a fifteenth aspect of the present invention, in the semiconductor device according to the fifteenth aspect, the first M has gates connected to each other and sources (or drains) connected to each other.
The OS transistor and the second MOS transistor can be formed without connecting the gates and the sources (or the drains) with each other by wiring.

In the semiconductor device according to claim 16 of the present invention, the first MOS transistor and the second MOS transistor having the gates connected to each other are formed without connecting the gates with each other by wiring. You can

In the semiconductor device according to claim 17 of the present invention, the capacitance value can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to claim 18 of the present invention, the structure obtained in the step (a) is used as a master, and the steps (b) and (c) are the slicing steps. In, the size of the semiconductor device can be determined. Therefore, it is possible to easily obtain a semiconductor device having a size according to a user's request without designing many types of masters having different sizes or designing the master to have many types of sizes.

According to the semiconductor device manufacturing method of the nineteenth aspect of the present invention, in the slicing step, the first
The size of the bipolar transistor can be freely set by setting the distance between the insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 20 of the present invention, the emitter length of the bipolar transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 21 of the present invention, the first bipolar transistor and the second bipolar transistor having collectors connected to each other can be provided without connecting the collectors to each other by wiring. Can be formed.

In the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, the bipolar transistor having the multi-emitter structure can be formed by dividing the emitter region by the third insulating wall.

In the semiconductor device manufacturing method according to the twenty-third aspect of the present invention, the size of the diode can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to the twenty-fourth aspect of the present invention, the resistance size can be determined only by setting the interval between the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to the twenty-fifth aspect of the present invention, the resistor can be formed at the same time when the bipolar transistor is formed.

In the method of manufacturing a semiconductor device according to claim 26 of the present invention, the size of the semiconductor element can be determined only by setting the interval between the first insulating wall and the second insulating wall.

In the method of manufacturing a semiconductor device according to claim 27 of the present invention, the size of the MOS transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to the twenty-eighth aspect of the present invention, the gate width of the MOS transistor can be determined only by setting the distance between the first insulating wall and the second insulating wall.

In the semiconductor device manufacturing method according to claim 29 of the present invention, as a first case, the first MOS transistor and the second MOS transistor having drains connected to each other are provided, and the drains are connected to each other. It can be formed without being connected by wiring.

As a second case, the first MOS transistor and the second M-transistor having sources connected to each other are provided.
The OS transistor can be formed without connecting the sources with wiring.

Further, as a third case, a structure in which the source of the first MOS transistor and the drain of the second MOS transistor are connected can be realized without connecting them by wiring.

In the method of manufacturing a semiconductor device according to claim 30 of the present invention, the first MOS having a drain connected to each other and a source connected to each other.
The transistor and the second MOS transistor can be formed without connecting the drains to each other and the sources to each other with a wiring.

In the method of manufacturing a semiconductor device according to claim 31 of the present invention, the first MOS transistor and the second MOS transistor having gates connected to each other and sources (or drains) connected to each other are provided. Can be formed without connecting the gates and the sources (or the drains) with each other by wiring.

In the method of manufacturing a semiconductor device according to a thirty-second aspect of the present invention, the first MOS transistor and the second MOS transistor having the gates connected to each other can be formed without connecting the gates with each other by wiring. Can be formed.

In the method of manufacturing a semiconductor device according to a thirty-third aspect of the present invention, since the gate region is selectively etched using the patterned nitride film as a mask, the source / drain regions are etched at that time. Never.

In the method of manufacturing a semiconductor device according to a thirty-fourth aspect of the present invention, the capacitance value can be determined only by setting the distance between the first insulating wall and the second insulating wall.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the structure of the semiconductor device according to the first example of the present invention.

FIG. 3 is a sectional view showing the structure of the semiconductor device according to the first example of the present invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first example of the invention in the order of steps.

FIG. 13 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first example of the invention in the order of steps.

FIG. 14 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 15 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the present invention in the order of steps.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the present invention in the order of steps.

FIG. 17 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first example of the invention in the order of steps.

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the present invention in the order of steps.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the present invention in the order of steps.

FIG. 20 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 21 is a plan view showing the structure of the semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 23 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 24 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the invention.

FIG. 25 is a circuit diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 26 is a plan view showing the structure of the semiconductor device according to the third embodiment of the present invention.

FIG. 27 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 28 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 29 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 30 is a plan view showing the structure of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 31 is a sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

32 is a sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention. FIG.

FIG. 33 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 34 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 35 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 36 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 37 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 38 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 39 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 40 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 41 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 42 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 43 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 44 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 45 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 46 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth example of the present invention in the order of steps.

FIG. 47 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth example of the present invention in the order of steps.

FIG. 48 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 49 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 50 is a circuit diagram showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

51 is a circuit diagram showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. FIG.

52 is a plan view showing the structure of the semiconductor device according to the fifth example of the present invention. FIG.

FIG. 53 is a sectional view showing the structure of the semiconductor device according to the fifth example of the present invention.

FIG. 54 is a sectional view showing the structure of the semiconductor device according to the fifth example of the present invention.

FIG. 55 is a sectional view showing the structure of the semiconductor device according to the fifth example of the present invention.

FIG. 56 is a circuit diagram showing a configuration of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 57 is a plan view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 58 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 59 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 60 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 61 is a circuit diagram showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 62 is a plan view showing the structure of the semiconductor device according to the seventh example of the present invention.

FIG. 63 is a sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 64 is a sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 65 is a sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 66 is a circuit diagram showing a configuration of a semiconductor device according to an eighth example of the present invention.

FIG. 67 is a plan view showing the structure of the semiconductor device according to the eighth example of the present invention.

FIG. 68 is a sectional view showing the structure of a semiconductor device according to an eighth example of the present invention.

FIG. 69 is a sectional view showing the structure of a semiconductor device according to an eighth example of the present invention.

FIG. 70 is a sectional view showing the structure of a semiconductor device according to an eighth example of the present invention.

71 is a plan view showing the structure of the semiconductor device according to the ninth embodiment of the present invention. FIG.

72 is a sectional view showing the structure of a semiconductor device according to a ninth embodiment of the present invention. FIG.

FIG. 73 is a sectional view showing the structure of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 74 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 75 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 76 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth example of the present invention in the order of steps.

FIG. 77 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 78 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 79 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 80 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 81 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 82 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 83 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 84 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth example of the present invention in the order of steps.

FIG. 85 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 86 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 87 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 88 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

FIG. 89 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

90 is a plan view showing the structure of the semiconductor device according to the tenth embodiment of the present invention. FIG.

FIG. 91 is a sectional view showing the structure of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 92 is a sectional view showing the structure of the semiconductor device according to the tenth embodiment of the present invention.

FIG. 93 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 94 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 95 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 96 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 97 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 98 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 99 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

FIG. 100 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention in the order of steps.

101 is a plan view showing the structure of the semiconductor device according to the eleventh embodiment of the present invention. FIG.

102 is a sectional view showing the structure of a semiconductor device according to an eleventh embodiment of the present invention. FIG.

103 is a sectional view showing the structure of a semiconductor device according to an eleventh embodiment of the present invention. FIG.

FIG. 104 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 105 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 106 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 107 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 108 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 109 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 110 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 111 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 112 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 113 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 114 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 115 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 116 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 117 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 118 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

FIG. 119 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention in the order of steps.

120 is a plan view showing the structure of the semiconductor device according to the twelfth embodiment of the present invention. FIG.

121 is a sectional view showing a structure of a semiconductor device according to a twelfth embodiment of the present invention. FIG.

122 is a sectional view showing the structure of a semiconductor device according to a twelfth embodiment of the present invention. FIG.

FIG. 123 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 124 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 125 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 126 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 127 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 128 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 129 is a sectional view showing a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention in the order of steps.

FIG. 130 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

131A and 131B are cross-sectional views showing a method of manufacturing a semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 132 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 133 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 134 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 135 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 136 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 137 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 138 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the twelfth embodiment of the present invention in the order of steps.

FIG. 139 is a plan view showing the structure of a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 140 is a sectional view showing the structure of a semiconductor device according to a thirteenth embodiment of the present invention.

141 is a sectional view showing the structure of a semiconductor device according to a thirteenth embodiment of the present invention. FIG.

FIG. 142 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 143 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 144 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 145 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 146 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 147 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 148 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 149 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 150 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 151 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 152 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 153 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 154 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 155 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 156 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 157 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention in the order of steps.

FIG. 158 is a plan view showing a structure of a semiconductor device according to a conventional technique.

FIG. 159 is a sectional view showing a structure of a semiconductor device according to a conventional technique.

FIG. 160 is a cross-sectional view showing a structure of a semiconductor device according to a conventional technique.

FIG. 161 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional technique in the order of steps.

162 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps. FIG.

FIG. 163 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 164 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 165 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 166 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 167 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 168 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 169 is a sectional view showing a structure of a semiconductor device according to a conventional technique.

FIG. 170 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 171 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional technique in the order of steps.

FIG. 172 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 173 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 174 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 175 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

FIG. 176 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps.

177 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps. FIG.

178 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional technique in the order of steps. FIG.

[Explanation of symbols]

1 substrate, 2 buried layer, 3 epitaxial layer, 4
Field oxide film, 5, 5a to 5d collector wall, 50, 50a to 50c, 56, 56a to 56c, 5
7, 57a to 57c, 91, 95, 95a to 95c Impurity diffusion layer, 9, 9a to 9d External base, 11, 11
a to 11c Intrinsic base, 12 Interlayer film, 15, 15
a, 15b, 15c Emitter, 20-22, 22a-
22h, 32a to 32h, 52a to 52f, 72a to 7
2f, 82a to 82f, 92a to 92f, 93, 93a
To 93c oxide film, 40 wells, 41, 41a to 41
c gate, 42, 42a to 42d source region, 43,
43a-43d gate oxide film, 44, 44a-44d
Drain region, 45, 45a to 45c, 94, 94a
~ 94c polysilicon film, 60 nitride film, 14, 14
a to 14i, 74a to 74h contact holes, 16, 1
6a to 16i, 36a to 361, 59a to 59f, 76
a-76h, 86a-86f, 96a-96f Aluminum electrode, 8a-8h, 24, 38a-38f, 58a-5
8f, 78a to 78f, 88a to 88f, 98a to 98
f Trench, M1 to M3 MOS transistors, B1
~ B3 bipolar transistor, C1 to C3 capacitance, R
1 to R6 resistors, J1 to J3PN diodes.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 21/8249 27/06 27/08 331 A H01L 27/06 321 C

Claims (34)

[Claims] 1. (a) A first member extending in the same direction
(B) a gap between the first insulating wall and the second insulating wall along a direction from the first insulating wall toward the second insulating wall; And at least one impurity region made of a semiconductor, each of the impurity regions is divided by the first insulating wall and the second insulating wall, and at least one impurity region is provided. A semiconductor device that is continuous between the first insulating wall and the second insulating wall, and the impurity region constitutes a semiconductor element between the first insulating wall and the second insulating wall. 2. The impurity regions are a first conductivity type collector region, a second conductivity type base region, and the first conductivity type emitter region, and the semiconductor element is a bipolar transistor. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the collector region, the base region, and the emitter region are all continuous between the first insulating wall and the second insulating wall. 4. (c) A third insulating wall, which extends in the same direction and divides the base region and the emitter region, is further provided between the first insulating wall and the second insulating wall. The semiconductor device according to claim 2. 5. The method according to claim 2, further comprising: (c) a third insulating wall that extends in the same direction and divides the emitter region between the first insulating wall and the second insulating wall. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the impurity regions are a first conductivity type anode region and a second conductivity type cathode region, and the semiconductor element is a diode. 7. The semiconductor device according to claim 1, wherein the impurity region is a resistor, and the semiconductor element is a resistor. 8. The impurity region is a resistor of a first conductivity type and a support layer of a second conductivity type, and the resistor and the support layer are electrically separated by applying a reverse bias. The semiconductor device according to claim 7. 9. (c) is provided longer than a distance between the first insulating wall and the second insulating wall along a direction from the first insulating wall toward the second insulating wall, An insulating layer further divided by the first insulating wall and the second insulating wall, wherein the resistor is separated by the first insulating wall, the second insulating wall and the insulating layer. 7. The semiconductor device according to 7. 10. (a) a first insulating wall and a second insulating wall formed to extend in the same direction, and (b) (b-1) the first insulating wall to the second insulating wall. Along the direction toward the first insulating wall and the second insulating wall.
At least one conductive region that is longer than the distance from the insulating wall and is made of a semiconductor into which an impurity that determines the conductivity type is introduced; and (b-2) the first insulating wall to the second insulating region.
Along the direction toward the insulating wall of the first insulating wall, a longer than the distance between the first insulating wall and the second insulating wall, and a configuration region having an insulating insulating region. The area is also the first insulating wall and the second insulating wall.
Is separated by an insulating wall of, at least one of the constituent regions is continuous between the first insulating wall and the second insulating wall, and the constituent region is the first insulating wall and the A semiconductor device in which a semiconductor element is formed between the second insulating walls. 11. The conductive region is a first conductive type substrate having an upper surface, a pair of second conductive type source / drain regions formed on the upper surface of the substrate, and a gate region, 11. The region is formed on a region between the pair of source / drain regions on the upper surface of the substrate, the gate region is formed above the insulating region, and the semiconductor element is a MOS transistor.
13. The semiconductor device according to claim 1. 12. The pair of source / drain regions, the gate region, and the insulating region are all the first regions.
12. The semiconductor device according to claim 11, which is continuous between the insulating wall and the second insulating wall. 13. (c) Between the first insulating wall and the second insulating wall, one of the gate region, the insulating region, and the source / drain region is divided by extending in the same direction. The third insulating wall is further provided.
1. The semiconductor device according to 1. 14. (c) A third insulating wall, which extends in the same direction and divides the gate region and the insulating region, is further provided between the first insulating wall and the second insulating wall. The semiconductor device according to claim 11. 15. (c) A third insulating wall, which extends in the same direction and divides only one of the source / drain regions, is further provided between the first insulating wall and the second insulating wall. The semiconductor device according to claim 11, further comprising: 16. (d) A fourth insulating wall extending between the first insulating wall and the second insulating wall in the same direction and dividing only the other of the source / drain regions. The semiconductor device according to claim 15, further comprising: 17. The conductive region is a first conductor and a second conductor, the insulating region is formed by being sandwiched between the first conductor and the second conductor, and the semiconductor element is a capacitor. 11. The semiconductor device according to claim 10. 18. (a) forming at least one impurity region extending in a first direction and made of a semiconductor and having a length of a predetermined value or more; and (b) after the step (a), Orthogonal to the first direction,
Dividing any of the impurity regions to form a first insulating wall and a second insulating wall separated by a distance shorter than the predetermined value, and (c) after the step (b), the first insulating wall Wiring the semiconductor element constituted by the impurity region between the insulating wall and the second insulating wall, wherein at least one of the impurity regions is the first insulating wall and the second insulating wall. A method of manufacturing a semiconductor device, which is continuous between insulating walls. 19. The impurity region is a collector region of a first conductivity type, a base region of a second conductivity type, and an emitter region of the first conductivity type, and the semiconductor element is a bipolar transistor. Of manufacturing a semiconductor device of. 20. The collector region, the base region,
20. The method of manufacturing a semiconductor device according to claim 19, wherein all of the emitter region is continuous between the first insulating wall and the second insulating wall. 21. The step (c) after the step (a).
(D) between the first insulating wall and the second insulating wall, a third insulating wall that is orthogonal to the first direction and divides the base region and the emitter region is formed. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising: 22. The step (c) after the step (a).
Before (d) a step of forming a third insulating wall, which is orthogonal to the first direction and divides the emitter region, between the first insulating wall and the second insulating wall. The method for manufacturing a semiconductor device according to claim 19, further comprising: 23. The method of manufacturing a semiconductor device according to claim 18, wherein the impurity regions are a first conductivity type anode region and a second conductivity type cathode region, and the semiconductor element is a diode. 24. The method of manufacturing a semiconductor device according to claim 18, wherein the impurity region is a resistor, and the semiconductor element is a resistor. 25. The impurity region is a first-conductivity-type resistor and a second-conductivity-type support layer, and the resistor and the support layer are electrically separated by applying a reverse bias. 25. The method of manufacturing a semiconductor device according to claim 24. 26. (a) At least one conductive region extending in the first direction and made of a semiconductor into which an impurity that determines the conductivity type is introduced, the conductive region having a length of a predetermined value or more; Extending and forming a constituent region having an insulating insulating region having a length equal to or greater than the predetermined value, (b) after the step (a), orthogonal to the first direction,
Dividing any of the constituent regions to form a first insulating wall and a second insulating wall separated by a distance shorter than the predetermined value, and (c) after the step (b), the first insulating wall Wiring the semiconductor element formed of the constituent region between the insulating wall and the second insulating wall, wherein at least one of the constituent regions includes the first insulating wall and the second insulating wall. A method of manufacturing a semiconductor device, which is continuous between insulating walls. 27. The conductive region is a first conductivity type substrate having an upper surface, a pair of second conductivity type source / drain regions formed on the upper surface of the substrate, and a gate region, 27. The region is formed on a region between the pair of source / drain regions on the upper surface of the substrate, the gate region is formed above the insulating region, and the semiconductor element is a MOS transistor.
The manufacturing method of the semiconductor device described in the above. 28. The pair of source / drain regions, the gate region, and the insulating region are all the first regions.
28. The method of manufacturing a semiconductor device according to claim 27, wherein the insulating wall is continuous with the second insulating wall. 29. (c) Between the first insulating wall and the second insulating wall, extending in the same direction and dividing one of the gate region, the insulating region, and one of the source / drain regions. The second insulating wall is further provided.
7. The method for manufacturing a semiconductor device according to 7. 30. (c) A third insulating wall, which extends in the same direction and divides the gate region and the insulating region, is further provided between the first insulating wall and the second insulating wall. A method of manufacturing a semiconductor device according to claim 27. 31. (c) A third insulating wall which extends in the same direction and divides only one of the source / drain regions between the first insulating wall and the second insulating wall. The method for manufacturing a semiconductor device according to claim 27, comprising. 32. (d) A fourth insulating wall extending between the first insulating wall and the second insulating wall and extending in the same direction to divide only the other of the source / drain regions. The method for manufacturing a semiconductor device according to claim 31, further comprising: 33. The conductive region is a first conductivity type substrate having an upper surface, a pair of second conductivity type source / drain regions formed on the upper surface of the substrate, and a gate region, The region is a gate oxide film provided between the gate region and a region sandwiched by the pair of source / drain regions on the upper surface of the base, and a nitride film covering the source / drain region and the gate region. The step (a) includes (a-1) a step of forming the gate oxide film on the upper surface of the substrate, and (a-2) a step of selectively forming the gate region on the gate oxide film. (A-3) a step of forming a pair of the source / drain regions on the upper surface of the substrate, and (a-4) forming the nitride film on the structure obtained by the step (a-3). Process, (a- ) A step of forming an oxide film on the structure obtained in the step (a-4), (a-6) a step of selectively removing the oxide film until the nitride film is exposed, and (a- 7) patterning by selectively removing the nitride film at a location where the oxide film is removed, and using the mask as a mask to selectively remove the gate region, the oxide film, the nitride 27. The method of manufacturing a semiconductor device according to claim 26, wherein a portion where the film and the gate region are removed corresponds to a portion where the first insulating wall and the second insulating wall are provided. 34. The conductive region is a first conductor and a second conductor, the insulating region is formed by being sandwiched between the first conductor and the second conductor, and the semiconductor element is a capacitor. 27. A method of manufacturing a semiconductor device according to claim 26.