JPH08115879A - Semiconductor manufacturing apparatus - Google Patents
Semiconductor manufacturing apparatusInfo
- Publication number
- JPH08115879A JPH08115879A JP24808694A JP24808694A JPH08115879A JP H08115879 A JPH08115879 A JP H08115879A JP 24808694 A JP24808694 A JP 24808694A JP 24808694 A JP24808694 A JP 24808694A JP H08115879 A JPH08115879 A JP H08115879A
- Authority
- JP
- Japan
- Prior art keywords
- chamber
- flat plate
- side wall
- cylindrical portion
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造に用い
るプラズマＣＶＤ装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma CVD apparatus used for manufacturing semiconductor devices.
【０００２】[0002]
【従来の技術】半導体基板上に薄膜を形成する一つの方
法として、プラズマＣＶＤ（ChemicalVapor Depositio
n）法がある。このプラズマＣＶＤ法では、減圧下での
放電で発生したプラズマ（ラジカル，イオン，原子，分
子）によって、低温で薄膜を堆積する。2. Description of the Related Art As one method for forming a thin film on a semiconductor substrate, plasma CVD (Chemical Vapor Depositio) is used.
n) There is a law. In this plasma CVD method, a thin film is deposited at low temperature by plasma (radicals, ions, atoms, molecules) generated by discharge under reduced pressure.
【０００３】プラズマＣＶＤ装置は、図３に示される様
に、チャンバ１０１の内部に設けられ多数の噴出穴を有
する上部電極１０２と、その上部電極１０２に対向する
ように設けられ図示しない半導体基板を載置する下部電
極１０３と、上部電極１０２の上方に設けられたガス供
給管１０４とを有する。As shown in FIG. 3, the plasma CVD apparatus includes an upper electrode 102 provided inside a chamber 101 and having a large number of ejection holes, and a semiconductor substrate (not shown) provided so as to face the upper electrode 102. It has a lower electrode 103 to be placed and a gas supply pipe 104 provided above the upper electrode 102.
【０００４】このような構造の装置を用いて、下部電極
１０３上に載置された半導体基板上にＣＶＤ膜を形成す
ると、その際に下部電極１０３上及びチャンバ１０１の
側壁にも不所望なＣＶＤ膜が形成される。これら不所望
なＣＶＤ膜はピンホール等の原因となるため、チャンバ
１０１内を定期的にクリーニングすることが必要であ
る。When a CVD film is formed on the semiconductor substrate mounted on the lower electrode 103 by using the apparatus having such a structure, undesired CVD is also formed on the lower electrode 103 and the sidewall of the chamber 101 at that time. A film is formed. Since these undesired CVD films cause pinholes and the like, it is necessary to regularly clean the inside of the chamber 101.
【０００５】クリーニング方法として、ガス供給管１０
４からエッチングガスを導入してチャンバ１０１内をド
ライエッチングする。このとき上部電極１０２と下部電
極１０３の間はプラズマが発生し下部電極１０３は負に
自己バイアスされる。そのため不所望なＣＶＤ膜は、プ
ラズマの発生範囲である下部電極１０３上ではエッチン
グ除去されるが、チャンバ１０１の側壁はエッチングさ
れにくい。そこで、例えば圧力の条件を変えたりして、
プラズマの発生範囲をチャンバ１０１の側壁まで広げよ
うとするが、側壁に形成された不所望なＣＶＤ膜を完全
に除去することは困難である。As a cleaning method, the gas supply pipe 10
An etching gas is introduced from 4 to dry-etch the inside of the chamber 101. At this time, plasma is generated between the upper electrode 102 and the lower electrode 103, and the lower electrode 103 is negatively self-biased. Therefore, the undesired CVD film is removed by etching on the lower electrode 103 where plasma is generated, but the side wall of the chamber 101 is hard to be etched. So, for example, by changing the pressure condition,
Although an attempt is made to expand the plasma generation range to the side wall of the chamber 101, it is difficult to completely remove the unwanted CVD film formed on the side wall.
【０００６】[0006]
【発明が解決しようとする課題】本発明の目的は、上記
問題を鑑みて、チャンバの側壁に不所望なＣＶＤ膜が形
成されることを防ぐと共に、チャンバの側壁に形成され
た不所望なＣＶＤ膜を容易に除去することができるプラ
ズマＣＶＤ装置を提供する。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to prevent an unwanted CVD film from being formed on the side wall of a chamber, and to prevent an unwanted CVD film formed on the side wall of the chamber. Provided is a plasma CVD apparatus capable of easily removing a film.
【０００７】[0007]
【課題を解決するための手段】本発明によるプラズマＣ
ＶＤ装置はチャンバと、上記チャンバ内に設けられた平
行平板型の上部電極及び下部電極とを具備し、上記上部
電極は上記下部電極に平行な平板部と上記平板部の周縁
上に設けられた円筒部とからなり、上記平板部はその上
下面に貫通する複数の吹出穴を有し、上記円筒部はその
外壁面のみに貫通する複数の吹出穴を有する。また、上
記平板部と上記円筒部は、各々別系統のガス供給管を有
する。Plasma C according to the present invention
The VD device includes a chamber and parallel plate type upper and lower electrodes provided in the chamber, and the upper electrode is provided on a flat plate portion parallel to the lower electrode and on a peripheral edge of the flat plate portion. The flat plate portion has a plurality of blowout holes penetrating the upper and lower surfaces thereof, and the cylindrical portion has a plurality of blowout holes penetrating only the outer wall surface thereof. Further, the flat plate portion and the cylindrical portion each have a gas supply pipe of a different system.
【０００８】[0008]
【作用】上記プラズマＣＶＤ装置は、上記平板部と上記
円筒部とからなる上部電極を有する。上記平板部と上記
下部電極とを用いて、上記下部電極上に載置された半導
体基板上にＣＶＤ膜を形成すると同時に、上記円筒部か
ら上記チャンバの側壁に不活性ガスを吹き付け該側壁に
不所望なＣＶＤ膜が形成されるのを防ぐ。The plasma CVD apparatus has an upper electrode composed of the flat plate portion and the cylindrical portion. A CVD film is formed on the semiconductor substrate placed on the lower electrode by using the flat plate portion and the lower electrode, and at the same time, an inert gas is blown from the cylindrical portion to the side wall of the chamber so that the side wall is protected. Prevent formation of desired CVD film.
【０００９】また、上記チャンバ内をクリーニングする
際には、上記平板部から噴出するエッチングガスは上記
下部電極上に形成された不所望なＣＶＤ膜を除去し、上
記円筒部から噴出するエッチングガスは上記側壁に形成
された不所望なＣＶＤ膜を除去する。When cleaning the inside of the chamber, the etching gas ejected from the flat plate portion removes the unwanted CVD film formed on the lower electrode, and the etching gas ejected from the cylindrical portion is removed. The unwanted CVD film formed on the sidewall is removed.
【００１０】[0010]
【実施例】以下、本発明による一実施例を図面を参照し
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１１】本発明によるプラズマＣＶＤ装置は、円柱
状のチャンバ１１と、その内部に設けられた円筒部１２
ａ及び平板部１２ｂからなる上部電極１２と、該上部電
極１２に平行に設けられ半導体基板（図示せず）を載置
する下部電極１３と、上部電極の平板部１２ｂの上方に
設けられた第１のガス供給管１４と、上部電極の円筒部
１２ａに接続された第２のガス供給管１５と、上部電極
１２と下部電極１３に接続する高周波電源１６とからな
る。それら上部電極１２と下部電極１３は丸型平行平板
電極構造である。また、上部電極の円筒部１２ａはチャ
ンバ１１の側壁と平行な形状であり、チャンバ１１内の
中心に位置する（図１）。The plasma CVD apparatus according to the present invention has a cylindrical chamber 11 and a cylindrical portion 12 provided therein.
a and a flat plate portion 12b, an upper electrode 12 which is provided in parallel with the upper electrode 12 and on which a semiconductor substrate (not shown) is mounted, and a first electrode which is provided above the flat plate portion 12b of the upper electrode. One gas supply pipe 14, a second gas supply pipe 15 connected to the cylindrical portion 12a of the upper electrode, and a high frequency power supply 16 connected to the upper electrode 12 and the lower electrode 13. The upper electrode 12 and the lower electrode 13 have a circular parallel plate electrode structure. The cylindrical portion 12a of the upper electrode has a shape parallel to the side wall of the chamber 11 and is located at the center of the chamber 11 (FIG. 1).
【００１２】図２によれば、上部電極の平板部１２ｂに
は、その上下面を貫通するガスの吹出穴が多数設けられ
る。また、円筒部１２ａはその外壁面にガスの吹出穴が
多数設けられるが、内壁面及び上下面は穴のない平らな
面である。そのため、第２のガス供給管１５から円筒部
１２ａに導入されたガスは、円筒部１２ａの外壁面から
チャンバ１１の側壁に吹出す。According to FIG. 2, the flat plate portion 12b of the upper electrode is provided with a large number of gas outlet holes penetrating the upper and lower surfaces thereof. The cylindrical portion 12a has a large number of gas outlet holes on its outer wall surface, but the inner wall surface and the upper and lower surfaces are flat surfaces without holes. Therefore, the gas introduced from the second gas supply pipe 15 into the cylindrical portion 12a blows out from the outer wall surface of the cylindrical portion 12a to the side wall of the chamber 11.
【００１３】次に、このような構造のプラズマＣＶＤ装
置を用いた薄膜例えばＳｉ３Ｎ４の形成方法を説明す
る。まず、下部電極１３上に半導体基板を載置する。チ
ャンバ１１内を減圧し、上部電極１２と下部電極１３間
に高周波プラズマを発生させ、第１のガス供給管１４か
らＳｉ３Ｎ４を形成するための原料ガスとなるＳｉＨ４
及びＮＨ３を導入し、それらのガスを上部電極の平板部
１２ｂに設けられた吹出穴から上記半導体基板に対して
垂直に供給する。一方、薄膜は上記半導体基板上のみな
らず、チャンバ１１内の側壁にも形成されるため、第２
のガス供給管１５から上部電極の円筒部１２ａに不活性
ガス、例えばＮ２若しくはＨｅを導入し、円筒部１２ａ
の吹出穴から上記側壁に吹き付ける。それにより、上記
側壁への薄膜形成を妨げることができる。このように、
本装置であると、上記半導体基板上に薄膜を形成すると
同時に、チャンバ１１内の側壁に薄膜が形成されるのを
防ぐことできる。Next, a method of forming a thin film such as Si 3 N 4 using the plasma CVD apparatus having the above structure will be described. First, the semiconductor substrate is placed on the lower electrode 13. The inside of the chamber 11 is decompressed, high-frequency plasma is generated between the upper electrode 12 and the lower electrode 13, and SiH 4 is used as a raw material gas for forming Si 3 N 4 from the first gas supply pipe 14.
And NH 3 are introduced, and those gases are vertically supplied to the semiconductor substrate through the blowout holes provided in the flat plate portion 12b of the upper electrode. On the other hand, since the thin film is formed not only on the semiconductor substrate but also on the side wall inside the chamber 11,
Inert gas such as N 2 or He is introduced into the cylindrical portion 12a of the upper electrode from the gas supply pipe 15 of the cylindrical portion 12a.
Spray the above side wall from the blow-out hole. Thereby, formation of a thin film on the side wall can be prevented. in this way,
With this apparatus, it is possible to form a thin film on the semiconductor substrate and at the same time prevent the thin film from being formed on the sidewall of the chamber 11.
【００１４】また、上記プラズマＣＶＤ装置内をクリー
ニングするには、上部電極１２と下部電極１３間に高周
波プラズマを発生させた状態で、第１のガス供給管１４
からエッチングガス、例えばＣＦ４とＯ２を導入して、
上部電極の平板部１２ｂに設けられた吹出穴より下部電
極１３に吹き付ける。それにより、下部電極１３に形成
された薄膜をエッチング除去することができる。同様
に、第２のガス供給管１５からエッチングガスを導入し
て、上部電極の円筒部１２ａに設けられた吹出穴からチ
ャンバ１１の側壁に吹き付ける。それにより、平板部１
２ｂからの噴出するガスでは除去しにくい上記側壁に形
成された薄膜をエッチング除去することができる。In order to clean the inside of the plasma CVD apparatus, the first gas supply pipe 14 is used while high frequency plasma is being generated between the upper electrode 12 and the lower electrode 13.
From which an etching gas such as CF 4 and O 2 is introduced,
The lower electrode 13 is sprayed through a blowout hole provided in the flat plate portion 12b of the upper electrode. Thereby, the thin film formed on the lower electrode 13 can be removed by etching. Similarly, an etching gas is introduced from the second gas supply pipe 15 and blown onto the side wall of the chamber 11 through the blowout hole provided in the cylindrical portion 12a of the upper electrode. Thereby, the flat plate portion 1
The thin film formed on the side wall, which is difficult to remove by the gas ejected from 2b, can be removed by etching.
【００１５】これら上部電極の平板部１２ｂまたは円筒
部１２ａからの２方向のクリーニングによって、チャン
バ１１内部に形成されたＣＶＤ膜を容易に除去すること
ができる。２方向のクリーニングは、同時に行うことも
できるし、個別に行うこともできる。The CVD film formed inside the chamber 11 can be easily removed by cleaning the upper electrode from the flat plate portion 12b or the cylindrical portion 12a in two directions. The cleaning in the two directions can be performed at the same time or individually.
【００１６】[0016]
【発明の効果】本発明によるプラズマＣＶＤ装置は、下
部電極に平行な平板部とチャンバの側壁に平行な円筒部
とからなる上部電極を有する。従って、上記平板部から
噴出する原料ガスにより半導体基板上にＣＶＤ膜を形成
すると同時に、上記円筒部から噴出する不活性ガスによ
りチャンバ内の側壁にＣＶＤ膜が形成されることを防ぐ
ことができる。また、チャンバ内をクリーニングする場
合、上記平板部から噴出されるエッチングガスは下部電
極上に形成されたＣＶＤ膜を除去し、上記円筒部から噴
出するエッチングガスはチャンバ内の側壁に形成された
ＣＶＤ膜を除去するのに効果がある。このような構造の
上部電極により、チャンバ内の側壁にＣＶＤ膜が形成さ
れにくくすると同時にクリーニングを容易にすることが
できる。The plasma CVD apparatus according to the present invention has an upper electrode composed of a flat plate portion parallel to the lower electrode and a cylindrical portion parallel to the side wall of the chamber. Therefore, it is possible to prevent the CVD film from being formed on the side wall in the chamber by the inert gas ejected from the cylindrical portion while forming the CVD film on the semiconductor substrate by the source gas ejected from the flat plate portion. When cleaning the inside of the chamber, the etching gas ejected from the flat plate portion removes the CVD film formed on the lower electrode, and the etching gas ejected from the cylindrical portion is formed by the CVD gas formed on the sidewall of the chamber. Effective in removing the film. By the upper electrode having such a structure, it is possible to prevent the CVD film from being easily formed on the side wall in the chamber and to facilitate the cleaning.
【図１】本発明によるプラズマＣＶＤ装置の概略を示す
断面図。FIG. 1 is a sectional view showing an outline of a plasma CVD apparatus according to the present invention.
【図２】上部電極の構造を示し（ａ）は円筒部、（ｂ）
は平板部を示す概略図。2A and 2B show a structure of an upper electrode, FIG. 2A is a cylindrical portion, and FIG.
Is a schematic view showing a flat plate portion.
【図３】従来のプラズマＣＶＤ装置の概略を示す断面
図。FIG. 3 is a sectional view showing the outline of a conventional plasma CVD apparatus.
１１…チャンバ １２…上部電極 １３…下部電極 １４…第１のガス供給管 １５…第２のガス供給管 １６…高周波電源 11 ... Chamber 12 ... Upper electrode 13 ... Lower electrode 14 ... 1st gas supply pipe 15 ... 2nd gas supply pipe 16 ... High frequency power supply
───────────────────────────────────────────────────── フロントページの続き (72)発明者 秋山 龍雄 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuo Akiyama 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Tamagawa factory
Claims (3)
た平行平板型の上部電極及び下部電極とを具備するプラ
ズマＣＶＤ装置であって、上記上部電極は上記下部電極
に平行な平板部と上記平板部の周縁上に設けられた円筒
部とからなり、上記平板部はその上下面に貫通する複数
の吹出穴を有し、上記円筒部はその外壁面のみに貫通す
る複数の吹出穴を有することを特徴とする半導体製造装
置。1. A plasma CVD apparatus comprising a chamber and parallel plate type upper and lower electrodes provided in the chamber, wherein the upper electrode is a flat plate portion parallel to the lower electrode and the flat plate. The flat plate portion has a plurality of blow-out holes penetrating to the upper and lower surfaces thereof, and the cylindrical portion has a plurality of blow-out holes penetrating only the outer wall surface thereof. A semiconductor manufacturing apparatus characterized by:
のガス供給管を有することを特徴とする請求項１記載の
半導体製造装置。2. The semiconductor manufacturing apparatus according to claim 1, wherein the flat plate portion and the cylindrical portion each have a gas supply pipe of a different system.
は、上記チャンバの側壁に吹出すことを特徴とする請求
項１記載の半導体製造方法。3. The semiconductor manufacturing method according to claim 1, wherein the gas ejected from the ejection hole of the cylindrical portion is ejected to the side wall of the chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24808694A JPH08115879A (en) | 1994-10-13 | 1994-10-13 | Semiconductor manufacturing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24808694A JPH08115879A (en) | 1994-10-13 | 1994-10-13 | Semiconductor manufacturing apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08115879A true JPH08115879A (en) | 1996-05-07 |
Family
ID=17173006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24808694A Pending JPH08115879A (en) | 1994-10-13 | 1994-10-13 | Semiconductor manufacturing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08115879A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998005803A1 (en) * | 1996-08-05 | 1998-02-12 | Komatsu Ltd. | Surface treatment apparatus, surface treatment method using the apparatus, and surface treatment nozzle used for the apparatus and method |
| US6576202B1 (en) | 2000-04-21 | 2003-06-10 | Kin-Chung Ray Chiu | Highly efficient compact capacitance coupled plasma reactor/generator and method |
| JP2008218877A (en) * | 2007-03-07 | 2008-09-18 | Hitachi Kokusai Electric Inc | Substrate treatment device and method of manufacturing semiconductor device |
| JP2011060899A (en) * | 2009-09-08 | 2011-03-24 | Ulvac Japan Ltd | Apparatus for manufacturing thin film solar cell |
| JP2011109076A (en) * | 2009-10-23 | 2011-06-02 | Semiconductor Energy Lab Co Ltd | Method for manufacturing microcrystalline semiconductor and thin film transistor |
| JP2012028737A (en) * | 2010-06-22 | 2012-02-09 | Nuflare Technology Inc | Semiconductor manufacturing equipment, semiconductor manufacturing method and cleaning method of the semiconductor manufacturing equipment |
| JP2014012891A (en) * | 2012-06-25 | 2014-01-23 | Novellus Systems Incorporated | Suppression of parasitic growth in substrate processing system by suppressing precursor flow and plasma in outside of substrate area |
-
1994
- 1994-10-13 JP JP24808694A patent/JPH08115879A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998005803A1 (en) * | 1996-08-05 | 1998-02-12 | Komatsu Ltd. | Surface treatment apparatus, surface treatment method using the apparatus, and surface treatment nozzle used for the apparatus and method |
| US6576202B1 (en) | 2000-04-21 | 2003-06-10 | Kin-Chung Ray Chiu | Highly efficient compact capacitance coupled plasma reactor/generator and method |
| US6998027B2 (en) | 2000-04-21 | 2006-02-14 | Dryscrub, Etc | Highly efficient compact capacitance coupled plasma reactor/generator and method |
| US7241428B2 (en) | 2000-04-21 | 2007-07-10 | Dryscrub, Etc | Highly efficient compact capacitance coupled plasma reactor/generator and method |
| JP2008218877A (en) * | 2007-03-07 | 2008-09-18 | Hitachi Kokusai Electric Inc | Substrate treatment device and method of manufacturing semiconductor device |
| JP2011060899A (en) * | 2009-09-08 | 2011-03-24 | Ulvac Japan Ltd | Apparatus for manufacturing thin film solar cell |
| JP2011109076A (en) * | 2009-10-23 | 2011-06-02 | Semiconductor Energy Lab Co Ltd | Method for manufacturing microcrystalline semiconductor and thin film transistor |
| JP2012028737A (en) * | 2010-06-22 | 2012-02-09 | Nuflare Technology Inc | Semiconductor manufacturing equipment, semiconductor manufacturing method and cleaning method of the semiconductor manufacturing equipment |
| JP2014012891A (en) * | 2012-06-25 | 2014-01-23 | Novellus Systems Incorporated | Suppression of parasitic growth in substrate processing system by suppressing precursor flow and plasma in outside of substrate area |
| US11111581B2 (en) | 2012-06-25 | 2021-09-07 | Lam Research Corporation | Suppression of parasitic deposition in a substrate processing system by suppressing precursor flow and plasma outside of substrate region |
| US11725282B2 (en) | 2012-06-25 | 2023-08-15 | Novellus Systems, Inc. | Suppression of parasitic deposition in a substrate processing system by suppressing precursor flow and plasma outside of substrate region |
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