JPH08111089A - Power-on resetting signal generating circuit of sdram - Google Patents

Abstract

PURPOSE: To obtain a power-on resetting signal having the pulse of a sufficiently long period independently of the rise speed of an external power spource by newly providing a flip-flop circuit and an OR gate in a conventional circuit. CONSTITUTION: An OR circuit 110 having three signals of the inverse of RAC, the inverse of CAS and the inverse of WE as inputs generates a precharging signal, the inverse of PRE, to output it to the OR gate 16 of the inside of a flip-flop circuit 101, which inputs the opposite signal, the inverse of POR1, of the signal from a power-on resetting signal generating circuit 100 which is conventionally ordinarily used before a time when the precharging signal is applied and newly outputs a power-on resetting signal, the inverse of POR2. Thus, the power-on resetting signal having the pulse of a sufficiently long period is made possible to be obtained in an SDRAM independently of the rise speed of the external power source and then the resettings of the indefinite nodes of the inside of the SDRAM are surely performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset signal generating circuit for SDRAM, that is, a power-on reset signal generating circuit for resetting an indefinite node of an internal circuit at power-on and forcibly setting its potential.

[0002]

2. Description of the Related Art With the recent increase in speed of microprocessors, dynamic RAM (hereinafter referred to as DR
The access time and cycle time of (AM) becomes a bottleneck, and the performance of the entire system incorporating DRAM is degraded. In order to prevent this, in other words, to improve system performance, a method of interposing a high-speed memory called cache memory composed of static RAM (hereinafter referred to as SRAM) between the DRAM and the microprocessor. Is often taken. However, since SRAM is more expensive than DRAM, this method is not suitable for a system that is desired to be relatively inexpensive, such as a personal computer. Therefore, it is required to use inexpensive DRAM and improve the system performance. As one answer to this, there has been proposed a synchronous DRAM (hereinafter referred to as Synchronous DRAM: SDRAM) capable of accessing several consecutive bits at high speed by synchronizing the DRAM with a system clock. The operation of this SDRAM will be briefly described.

FIG. 7 shows a timing chart at the time of reading of a conventional general SDRAM. In conventional DRAM, / RAS,
While the address and input data were fetched in synchronization with the control signal called / CAS, in SDRAM, at the rising edge of the system clock CLK that is externally applied,
Take in / RAS, / CAS, address, and data to operate. Specifically, it is as follows.

In FIG. 7, 8-bit data (byte data) of the data input / output terminals DQ0-7 can be input and output.
In SDRAM, continuous 4-bit data (4 × 8 =
The operation to read (32 bits) is shown.

For example, an external control signal is synchronized with a rising edge of an externally applied system clock CLK, specifically, low active / RAS (row address strobe signal) and low active / CAS (column address). Strobe signal), low-active write enable signal / WE, address signals A0-A10, etc. are input. As the address signal, a row address signal X and a column address signal Y are multiplexed in a time division manner. At the rising edge of the clock CLK, the row address strobe signal / RAS becomes active (“L” level), the column address strobe signal / CAS and the write enable signal / WE.
If both are inactive (“H” level), the address signal at that time is the row address signal X.
Captured in SDRAM.

Next, if the column address strobe signal / CAS is active ("L" level) at the rising timing of the clock CLK, the address signal at that time is taken into the SDRAM as the column address signal Y. In this way, the row and column selecting operation is executed in the SDRAM in accordance with both address signals taken in the SDRAM. And row address strobe signal / RAS
From the time when the signal falls to the "L" level, the predetermined clock
The first 4-bit data is output from the SDRAM after a period (6 clocks in the example shown here). Thereafter, 4-bit data is output from the SDRAM every time the column address strobe signal / CAS falls.

As described above, the advantage of synchronizing the SDRAM with the external clock CLK is that there is no need to secure a data input / output margin for compensating for skews (timing deviations) such as addresses, and therefore the cycle time can be shortened. It can be realized. Also, depending on the system, there are cases in which several consecutive bits are accessed frequently, and it is also possible to make the average access time comparable to SRAM by increasing the continuous access time.

Furthermore, the concept of multiple banks has been introduced into SDRAM. This is configured by dividing the internal memory array into multiple parts, and activates each bank.
(Start up the word line and operate the sense amplifier),
It is designed so that precharging can be performed almost independently. In DRAM, it was necessary to precharge before access, which caused the cycle time to be almost twice as long as the access time. However, by dividing the inside of the SDRAM into multiple banks, if the second bank is precharged while the first bank is being accessed, the access to the second bank is apparently precharged. It will be possible in no time. In this way, by alternately accessing and precharging the two banks, it is possible to reduce the loss time due to the precharge. It can be said that this incorporates a method called interleaving, which was conventionally performed externally, into the DRAM.

On the other hand, when the power is turned on, the power-on reset signal is used to force the voltage indefinite node (eg, flip-flop circuit) inside the chip to the fixed voltage.
It is common practice in a conventional SDRAM to generate a pulse (hereinafter referred to as a POR signal) inside the chip. P
A conventional example of an OR signal generation circuit is shown in the circuit diagram of FIG.

In FIG. 8, reference numeral C1 is a capacitor, one end of which is at the power supply potential Vcc and the other end of which is connected to the input end of the inverter B1 and the N-channel transistor Q1 via the node N1.
Is connected to one end. The output terminal of the inverter B1 is connected to the input terminal of the inverter B2 and is output to the outside as a reverse phase signal / POR of the POR signal. In addition, the inverter
The output terminal of B2 is connected to the base of the N-channel transistor Q1 via the node N3, the timer T1 and the node N2. The other end of the N-channel transistor Q1 is grounded. The output terminal of the inverter B2, that is, the output signal from the node N3 is the POR signal.

The operation of this circuit will be described with reference to the timing chart of FIG. The external power supply ext.Vcc starts to rise at time t1, and the POR signal from the node N3 starts to rise as the potential of the node N1 rises due to the capacitor C1. From the time t2 when the POR signal reaches "H" level, the potential of the node N2 starts to rise from 0V after a lapse of a predetermined time ΔT set in the timer T1. The potential of this node N2 is the N-channel transistor Q1.
Since it is applied to the base of N, the N channel transistor Q1 is turned on at time t3 when it exceeds the threshold value Vth to ground the node N1. As a result, the potential of the node N1 is discharged to 0V. As a result, at time t3, the signal / POR
Starts rising, and on the contrary, the POR signal drops to 0V and thereafter remains at 0V unless the power is cut off.

By the way, the POR signal is input to a flip-flop circuit in the SDRAM, for example, as shown in the circuit diagram of FIG. 10, and is used for the purpose of resetting the indefinite node φ 3 to 0V.

In addition, the substrate voltage of SDRAM (Vbb: internally generated, a negative voltage is applied in the case of a P-type substrate) at power-on is slightly raised by the junction capacitance with the power source. In order to prevent this from happening, it is also used when the substrate is kept at the ground level as shown in the circuit diagram of FIG.

By the way, the POR signal is generated in accordance with the fluctuation of the external power supply as described above, but its generation timing is different depending on the rising and falling of the external power supply. this is,
An example is shown in the timing chart of FIG. 12, though it depends on what kind of configuration the power-on reset signal generating circuit is used. As shown in Fig. 12 (a), when the external power supply ext.Vcc rises rapidly, the external power supply is generated at time t3 when the POR signal is generated and the pulse starts to end.
Since the potential of ext.Vcc has already reached the "H" level, the indefinite node of the circuit as described above is surely reset. On the other hand, as shown in Fig. 12 (b), when the external power supply ext.Vcc rises slowly,
The POR signal pulse ends before the potential of the external power supply ext.Vcc reaches the "H" level, which causes a problem that the POR signal cannot perform its original function.

[0015]

SUMMARY OF THE INVENTION As described above, the conventional
In SDRAM, power-on reset signal (POR signal)
Is generated only in response to the rise of the external power supply, so before the external power supply does not rise reliably, in other words, before the potential of the external power supply reaches a sufficient potential as the “H” level potential, a power-on reset is performed. There was a problem that the indeterminate node inside the SDRAM was not reset surely because the signal pulse ended. The present invention has been made to solve such a problem, and an object of the present invention is to obtain a power-on reset signal having a pulse of a sufficiently long period in an SDRAM regardless of the rising speed of an external power supply.

[0016]

A power-on reset signal generating circuit according to the present invention is a conventional one that is generated before a precharge signal is given to a precharge signal of the signals given to a SDRAM at power-on. A flip-flop circuit, which receives a reverse-phase signal of a power-on reset signal that is normally used, is provided, and an output signal of this flip-flop circuit is newly used as a power-on reset signal.

Further, the power-on reset signal generating circuit according to the present invention is provided before the precharge signal, the refresh signal, and the precharge signal and the refresh signal are given to the SDRAM when the power is turned on. The output signal of the flip-flop circuit that receives the opposite phase signal of the conventionally used power-on reset signal that is conventionally used is newly used as the power-on reset signal, and such a signal is generated only once. It is configured.

[0018]

In the power-on reset signal generation circuit according to the present invention, the flip-flop circuit is set by the signal opposite in phase to the power-on reset signal and then reset by the precharge signal. The output signal of this flip-flop circuit is used as a new power-on reset signal to reset the internal power of the SDRAM.

Further, in the power-on reset signal generating circuit according to the present invention, the flip-flop circuit is temporarily reset by the opposite phase signal of the power-on reset signal before the refresh signal is given and then set by the precharge signal, After that, it is reset by a refresh signal. The output signal of this flip-flop circuit is used as a new power-on reset signal to reset the internal power of the SDRAM. Further, even if the precharge signal is given after that, the flip-flop circuit is not set.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

[Embodiment 1] FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of a power-on reset signal generating circuit according to the present invention. By the way, the power-on reset signal generation circuit of the present invention is suitable when it is mainly applied to SDRAM. However, in SDRAM, the clock is enabled and the precharge command is issued before the normal operation state after the external power is turned on. Therefore, there is a provision that an auto refresh command and a mode register set command must be input.

Normally, these commands are input to the SDRAM after several hundreds of ms have passed since the external power was turned on. The power-on reset signal generating circuit of the present invention inputs the precharge signal / PRE of these signals and the reverse phase signal / POR of the power-on reset signal (POR signal) described in the above-mentioned conventional example. The output signal of the flip-flop circuit is set as a new power-on reset signal.

In FIG. 1, reference numeral 100 denotes the above-mentioned FIG.
It is a conventional power-on reset signal generation circuit shown in FIG. In the following description of the present invention, the conventional power-on reset signal generation circuit indicated by reference numeral 100 is referred to as a first circuit. The first embodiment of the power-on reset signal generating circuit of the present invention is mainly the first circuit 100 and the second circuit which is a flip-flop circuit.
It is composed of 101 and an OR gate 110. Second circuit 101
In addition, inverter 10, OR gate 16, NAND gate 17, N
It is composed of an AND gate 18 and capacitors 1 and 12.

From the first circuit 100, a negative phase signal (hereinafter, referred to as first inverted power-on reset signal / POR1) of the conventional power-on reset signal POR (hereinafter, referred to as first power-on reset signal POR1) is externally supplied. And is input to one input terminal of the NAND gate 17 and the input terminal of the inverter 10.

In the first circuit 100, reference numeral C1 is a capacitor, one end of which is connected to the power supply potential Vcc and the other end of which is connected to the input end of the inverter B1 and one end of the N-channel transistor Q1 via the node N1. There is. The output end of the inverter B1 is connected to the input end of the inverter B2 and
It is output to the outside as a first inverted power-on reset signal / POR1 which is a reverse phase signal of the power-on reset signal POR1. Further, the output terminal of the inverter B2 is connected to the base of the N-channel transistor Q1 via the timer T1 and the node N2. The other end of the N-channel transistor Q1 is grounded. The output signal from the output terminal of the inverter B2 is the first power-on reset signal POR1, but is only given to the timer T1 in the power-on reset signal generation circuit of the present invention.

Reference numeral 110 is a three-input OR gate,
Functions as a precharge command decoder for generating the precharge signal / PRE. This OR gate 110 has a row active row address strobe signal / RAS
Is input to the positive logic input terminal, the low-active column address strobe signal / CAS is input to the negative logic input terminal, and the low-active write enable signal / WE is input to the positive logic input terminal. An active precharge signal / PRE is generated.

The timing chart of FIG. 2 shows the relationship between the input signal and the output signal of the OR gate 110 as the above-mentioned precharge command decoder. Specifically, the row address strobe signal / RAS is at the "L" level (active), the column address strobe signal / CAS is at the "H" level (nonactive), and the write enable signal / WE.
Is "L" level (active), OR gate
110 outputs an "L" level pulse as a precharge signal / PRE. The precharge signal / PRE output from the OR gate 110 is applied to one input terminal of the 2-input OR gate 16 of the second circuit 101.

The output signal 15 of the inverter 10 is input to the other input terminal of the above-mentioned OR gate 16, and this OR gate 16
The 16 output signals are input to one input terminal of a 2-input NAND gate 18. And the output signal of the NAND gate 18 is
It is input to the other input terminal of the NAND gate 17 and also output as the power-on reset signal of the present invention (hereinafter referred to as the second power-on reset signal / POR2) via the node 14. Further, the node 14 is grounded via the capacitor 12.

On the other hand, the output signal of the NAND gate 17 is input to the other input terminal of the NAND gate 18, and this input terminal is also connected to the power supply potential Vcc via the capacitor 11.

Next, the operation of the first embodiment of the power-on reset signal generating circuit of the present invention constructed as described above will be described with reference to the timing chart of FIG.

First, at time t1, the external power supply ext.Vcc
However, in the first circuit 100, the first inverted power-on reset signal / POR
1 is at the "L" level. Therefore, the first power-on reset signal POR1 rises with the rise of the external power supply ext.Vcc.

After the first power-on reset signal POR1 reaches the "H" level at time t2, the first inverted power-on reset signal / POR1 is changed at time t3 after the time ΔT set in the timer T1 has elapsed. While starting to rise, the first power-on reset signal POR1 starts to fall. However, at this point, the external power supply ext.Vcc has not reached the predetermined level ("H" level). However, since the first inverted power-on reset signal / POR1 is input to the NAND gate 17 of the flip-flop circuit directly to one input terminal and to one input terminal of the OR gate 16 via the inverter 10, the flip-flop circuit Second power-on reset signal / POR when the second circuit 101 is set
2 is maintained at "L" level.

After this, as shown in FIG. 2, by a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE which are externally applied after a sufficiently long period has passed since the external power was turned on. "L" level precharge signal / P from OR gate 110
RE is output and the flip-flop circuit (second circuit 101) is reset at time t5. As a result, the second power-on reset signal / P which is the power-on reset signal of the present invention.
OR2 is reset to "H" level. Therefore, the power-on reset signal having a sufficiently long active (“L” level) period that does not depend on the rising speed of the external power supply, that is, the low-active second power-on reset signal.
Can generate / POR2.

It should be noted that the capacitors 11 and 12 shown in FIG. 1 have a coupling capacitance when the flip-flop circuit (second circuit 101) cannot be set by the first inverted power-on reset signal / POR1. Node 13
Is held at "H" level and the node 14 is held at "L" level.
It is provided for surely setting 101). Also,
The first inverted power-on reset signal / POR1 is input to the OR gate 16 via the inverter 10. This is because even if the level of the precharge signal / PRE is unstable when the power supply rises, the first inverted power-on reset signal / POR1 is input. On-reset signal / POR
This is for surely setting the flip-flop circuit (second circuit 101) by 1.

[Second Embodiment] Next, a second embodiment of the power-on reset signal generating circuit of the present invention will be described.
FIG. 4 is a circuit diagram showing an example of the configuration. The second embodiment is a further development of the first embodiment shown in FIG. 1. The rising speed of the external power supply is very slow and the conventional power-on reset signal is Even when the power-on reset signal is not generated, it can be dealt with by generating a new one-time power-on reset signal which is set by the precharge command and reset by the auto-refresh command.

In FIG. 4, reference numeral 100 is the above-mentioned first
Similar to the first embodiment, the first circuit as a conventional power-on reset signal generation circuit is shown, and the first inverted power-on reset signal / POR1 is output.

Reference numeral 120 is a three-input OR gate,
Functions as a refresh command decoder for generating the refresh signal / REF. This OR gate 120 has a row active row address strobe signal / RAS
Is input to the positive logic input terminal, the low-active column address strobe signal / CAS is input to the positive logic input terminal, and the low-active write enable signal / WE is input to the negative logic input terminal. The signal / REF is generated.

The timing chart of FIG. 5 shows the relationship between the input signal and the output signal of the OR gate 120 as the above-mentioned refresh command decoder. Specifically, the row address strobe signal / RAS is at "L" level (active), the column address strobe signal / CAS is at "L" level (active), and the write enable signal / WE is "".
When it is at H "level (non-active), it outputs" L "level (active) pulse for refreshing SDRAM as refresh signal / REF.
The refresh signal / REF output from the gate 120 is the first
Is applied to one input terminal of a 2-input NAND gate 30 of the flip-flop circuit 31.

The first flip-flop circuit 31 includes a 2-input OR gate 28, a 3-input NAND gate 29, and a 2-input NAND.
It consists of a gate 30. The precharge signal / PRE is input to one input terminal of the OR gate 28, and the output signal / φA of the second flip-flop circuit 25 described later is input to the other input terminal.
The reverse-phase signal φ A of is input. The output signal of the NOR gate 28 is input to the first input terminal of the NAND gate 29, and the second input terminal thereof has the first inverted power-on reset signal / POR1 which is the output signal of the first circuit 100.
However, the output signal of the NAND gate 30 is input to each of the third input terminals. The refresh signal / REF, which is the output signal of the OR gate 120, is input to one input terminal of the NAND gate 30, and the output signal of the NAND gate 29 is input to the other input terminal. The output signal of the NAND gate 30 is output as the output signal of the first flip-flop circuit 31, that is, the power-on reset signal of the second embodiment (hereinafter referred to as the third power-on reset signal / POR3). There is.

Reference numeral 32 is a delay circuit, which is composed of an odd number of stages of inverters. The delay circuit 32 inputs the above-mentioned third power-on reset signal / POR3 and outputs an output signal 33 delayed by a predetermined time.

Reference numeral 34 is a two-input NAND gate,
The output signal 33 of the delay circuit 32 described above is input to one of the input terminals.
The third power-on reset signal / POR3, which is the output signal of the first flip-flop circuit 31, is input to the other input terminal. The output signal of the NAND gate 34 is input to the 2-input NAND gate 24 of the second flip-flop circuit 25 via the node 35.

The second flip-flop circuit 25 has two inputs.
It is composed of the NAND gate 23 and the above-mentioned NAND gate 24. The first inverted power-on reset signal / POR1 output from the first circuit 100 is input to one input terminal of the NAND gate 23.
However, the output signal of the NAND gate 24 is input to the other input terminal. The output signal of the NAND gate 23 is input to one input terminal of the NAND gate 24 and also output as the above-mentioned signal / φA via the node 26. A power supply potential is connected to the node 26 via the capacitor 21. The output signal of the NAND gate 34 is input to the other input terminal of the NAND gate 25 via the node 35, and the output signal is input to the other input terminal of the NAND gate 23 and also to the node 27. Is grounded via a capacitor 22.

Next, the operation of the second embodiment of the power-on reset signal generating circuit of the present invention constructed as described above will be described with reference to the timing chart of FIG.

First, at time t1, the external power supply ext.Vcc starts to rise very slowly, and accordingly, at time t3.
The first inverted power-on reset signal / POR1 also starts to rise, but since the rise of the external power supply ext.Vcc is very slow, the start timing of the rise of the first power-on reset signal POR1 is the rise of the external power supply ext.Vcc. It is quite late from the start time. Further, since the first inverted power-on reset signal / POR1 also starts to rise at time t3 with the rise of the external power supply ext.Vcc, the "H" level period of the first power-on reset signal POR1 is extremely short. However, in the second embodiment, the first inverted power-on reset signal / POR1, the auto-refresh pulse which is the "H" level pulse of the refresh signal / REF, the precharge signal / PRE, and the second flip-flop. Output signal of circuit 25
The first flip-flop circuit 31 is constituted by the two NAND circuits 29 and 30 which receive the OR signal of the OR gate 28 and the opposite phase signal φA of / φA, and the third power which is the output signal thereof. The on-reset signal / POR3 is used as the power-on reset signal.

Here, the second flip-flop circuit 25
Occurs through the delay circuit 32 including the first inverted power-on reset signal / POR1, the third power-on reset signal / POR3, and the third power-on reset signal / POR3 which are odd-numbered inverters. Inverted delay signal 33 and input
The output signal of the NAND circuit 34 is used as an input signal. When the third power-on reset signal / POR3 rises together with the external power supply ext.Vcc, the precharge signal / PRE at time t4
And even if the refresh signal / REF rises from "L" level to "H" level, the third power-on reset signal / P
OR3 is still at "H" level.

When the precharge command is input at time t5 and the precharge signal / PRE falls in the first circuit 100, the third power-on reset signal / POR3 also falls. In other words, the power-on reset signal of the present invention is newly generated from this point. The third power-on reset signal / POR3 maintains the "L" level, that is, the active state until the refresh command is input and the refresh signal / REF falls at time t6. Therefore, the active third power-on reset signal / POR3 can be obtained over a sufficiently long period.

At time t6, when the refresh command is input and the refresh signal / REF falls, the third power-on reset signal / POR3 changes from "L" level to "H".
Change to a level. At this time, the output signal of the NAND circuit 34, which receives the third power-on reset signal / POR3, generates a temporary "L" level pulse by the action of the delay circuit 32. Therefore, the level of the output signal from the second flip-flop circuit 25 at nodes 26 and 27 is inverted and
Inverted signal φA output from 26 changes from "L" level to "
It changes to the H "level. After that, the output signal of the NAND circuit 34
Even if (level of node 35) changes to "H" level, the second
Since the output of the flip-flop circuit 25 of the above maintains the previous state, the inverted signal φA of the output signal from the node 26 is
The signal φA is fixed to the H level. In this way, the signal φA is fixed to the "H" level, so that the signal φ
The OR signal by the OR gate 28 of A and the precharge signal / PRE is also fixed to the "H" level regardless of the precharge signal / PRE. Therefore, even if a precharge command is input thereafter, it does not affect the operation of this circuit.

Further, the first inverted power-on reset signal / P
Since OR1 is also fixed to "H" level, the third power-on reset signal / POR3 which is the output signal of the first flip-flop circuit 31 is "H" regardless of the refresh signal / REF and the precharge signal / PRE. It will be fixed at the level.

As described above, in the circuit of the second embodiment shown in FIG. 3, the "H" level pulse of the first power-on reset signal POR1 which is the conventional power-on reset signal is maintained for a sufficient period. Even if it does not occur, it is possible to generate a new one-time power-on reset signal that is set by the precharge pulse and reset by the auto-refresh pulse, that is, the third power-on reset signal / POR3. The indefinite node of the circuit can be surely reset.

The capacitors 21 and 22 shown in FIG. 4 have two NAND circuits 23 due to their coupling capacitances.
The node 26 when the power of the second flip-flop circuit 25, which is composed of 24 and 24, is turned to “H” level,
It is provided to forcibly set each to the L "level.

[0051]

As described above in detail, according to the power-on reset signal generation circuit of the present invention, in the SDRAM,
Since it becomes possible to obtain a power-on reset signal having a pulse for a sufficiently long period irrespective of the rising speed of the external power supply, the indefinite node inside the SDRAM is surely reset.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of a power-on reset signal generation circuit according to the present invention.

FIG. 2 is a timing chart of the precharge command decoder of the first embodiment of the power-on reset signal generating circuit according to the present invention.

FIG. 3 is a timing chart showing an operation of the first embodiment of the power-on reset signal generating circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a second embodiment of a power-on reset signal generation circuit according to the present invention.

FIG. 5 is a timing chart of a refresh command decoder of a second embodiment of the power-on reset signal generating circuit according to the present invention.

FIG. 6 is a timing chart showing the operation of the second embodiment of the power-on reset signal generating circuit according to the present invention.

FIG. 7 is a timing chart at the time of reading of a conventional general SDRAM.

FIG. 8 is a circuit diagram showing a configuration example of a conventional power-on reset signal generation circuit of SDRAM.

FIG. 9 is a timing chart showing the operation of the power-on reset signal generation circuit of the conventional SDRAM.

FIG. 10 is a circuit diagram showing an example of a circuit that is an operation target of a power-on reset signal generation circuit of a conventional SDRAM.

FIG. 11 is a circuit diagram showing an example of a circuit which is an operation target of a power-on reset signal generation circuit of a conventional SDRAM.

FIG. 12 is a timing chart for explaining that the generation timing of the power-on reset signal generated by the conventional power-on reset signal generation circuit differs depending on the speed of rising of the external power supply.

[Explanation of symbols]

31 first flip-flop circuit, 25 second flip-flop circuit, 32 delay circuit, 34 NAND gate, 100
1st circuit, 101 2nd circuit, 110 OR gate, 120 OR
Gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiji Sawada 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corp. Kita Itami Works

Claims (2)

[Claims] 1. An SD to which a first signal which is significant for precharging a data read / write signal line is applied after a lapse of a predetermined time from the time of turning on an external power supply.
The second signal for forcibly resetting the voltage indefinite node inside the RAM to the definite voltage is provided until the first signal is given according to the rise of the external power supply potential when the external power supply is turned on. In a power-on reset signal generating circuit that makes significant, the second signal is set when it becomes significant, the first signal is reset when it becomes significant, and the third signal is significant when it is in the set state. A flip-flop circuit that outputs an insignificant third signal when the signal is in a reset state is provided, and when the third signal is significant, an internal voltage indefinite node of the SDRAM is forced to a definite voltage. A power-on reset signal generation circuit for an SDRAM, wherein the power-on reset signal generation circuit is configured to be reset. 2. A first signal which becomes significant for precharging a data read / write signal line and a second signal which becomes significant for refreshing a memory cell after a lapse of a predetermined time from the time of turning on an external power supply. A third signal for forcibly resetting the internal voltage indefinite node of the SDRAM to which the signal is applied to the definite voltage according to the rise of the external power supply potential when the external power supply is turned on.
In the power-on reset signal generation circuit that makes significant until the time when the second signal and the second signal are given, the third signal or the second signal is reset by being ineffective, and the first signal is A first flip-flop circuit which is set by becoming significant and outputs a significant fourth signal when in the set state and an insignificant fourth signal when in the reset state; A delay circuit that delays and inverts a signal to output a fifth signal, and NA of the fourth signal and the fifth signal
A circuit configured to include a NAND gate that outputs an ND signal as a sixth signal, and that outputs a sixth signal that becomes temporarily significant when the fourth signal changes from significant to insignificant for the second time; Reset by the third signal becoming significant,
A second flip-flop circuit that is set when the sixth signal becomes significant, and outputs a significant seventh signal in the set state and an insignificant seventh signal in the reset state. And a circuit for invalidating the first signal when the seventh signal is significant, and a voltage indefinite node inside the SDRAM is forced to a definite voltage when the fourth signal is significant. A power-on reset signal generation circuit for an SDRAM, which is characterized in that the power-on reset signal generation circuit is reset.