JPH08110826A - Input device for digit - Google Patents

Abstract

PURPOSE: To provide a digit input device which is easy for use for an expert in abacus, too and enables a usser to perform carry-up and carry-down operations close to Japanese abacus. CONSTITUTION: Every time an input key for each digit is operated, the light emission part 3 of the directly operated input key blinks repeatedly, and the carry-down operation wherein the light emission parts 3 of all bead keys lower in order than a depressed bead key go out is performed by pressing one of the 1st-4th keys K1-K4 whose light emission parts of one digit are in illumination states, and carry-up operation wherein the light emission parts 3 of bead keys higher in order than a depressed bead key illuminate is performed by pressing the bead key whose light emission part 3 is off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digit input device which is easy to use even for an expert in abacus and can realize a carry-up and carry-down operation similar to that of abacus.

[0002]

2. Description of the Related Art Conventionally, as an input device for inputting a digit of a numerical value in an electronic computer or the like, generally, a numerical key corresponding to each of numbers 0 to 9 is sequentially pressed.

[0003]

However, such an input device handles numerical data to be input as a list of numbers 0 to 9 in which scale is ignored, and therefore, for example, 10
If the number of digits increases beyond the number of digits, digit errors are likely to occur at the time of input, accurate data cannot be input, and "0" must be input, which increases the input time.

On the other hand, the abacus is superior to the above-mentioned input device in that it always treats numerical values with the idea of place and does not input "0", but the input results and calculation results of the abacus are themselves read by humans. However, it is not possible to directly use it for calculation using an electronic computer or a CPU, and there is a problem that it is inferior in versatility.

The present invention has been devised in view of such a problem. It is possible to handle numerical values to be input with an idea of rank, and to realize the advantages of abacus such as raising and lowering operations as they are, and to input results. It is an object of the present invention to provide a digit input device that can be directly used for calculation by an electronic computer or a CPU, and can display the calculation result. In addition, a digit input device is possible only by hardware to increase the processing speed.
It is also an object to provide a digit input device that can achieve the integration of the hardware.

[0006]

According to the present invention, there is provided on the surface of the main body part, one 5-bead key showing a value of 5 arranged corresponding to 5 bead of abacus, 1 bead, and below the 5 bead key. The first 1-key, which indicates a value of 1, which is sequentially arranged at the position, this first 1
It is composed of a second 1-pearl key lower than the pearl key, a third 1-pearl key lower than the second 1-pearl key, and a fourth 1-pearl key lower than the third 1-pearl key. An input key, a light emitting portion provided for each input key, and a switch provided for each input key and for outputting a key operation signal indicating an operation state corresponding to the input key by operating the input key. A plurality of digits input section, key operation signals of all the switches of each digit input section are sequentially received based on the input time-division scanning signal, and the received key operation signals are sequentially output. Possible key matrix, the key operation signal of each input key output from this key matrix is input as a clock signal, and the state of each input key is changed by the input of this clock signal,
The five-jewel key having a key-state output terminal capable of storing and holding as a key-state signal by alternately inverting the signal and one D-flop for five-jewel key corresponding to the first to fourth one-jewel keys and four A key state holding circuit having first to fourth D-flops for the 1st ball key, and a key state signal of each input key stored and held in the 5th bead key and the D flip-flops for the 1st to 4th ball key. A register matrix in which a register capable of storing each input key is provided in a plurality of digits, and key status signals of digits are sequentially read from the register matrix, and the light emitting portion of each input key emits light in response to this signal. By having a light emitting display matrix that is turned on and off, each time the input key is operated, the light emitting portion of the directly operated input key is turned on and off at each digit. , With repeated off alternately,
At the time of operating the first to fourth beads, when the key state signal of the third beads of the register matrix of the operated digit is in the signal state of lighting the light emitting unit, or the keys. When a key operation signal for operating the first 1-ring key is output from the matrix, by detecting any one of the states, the D flip prop of the lower input key than the operated input key is detected. Is output to the D flip-flop of the key higher than the key operated by the non-detection of the state, and the carry-up is performed to invert the key state signal. By including an operation discriminating circuit that outputs a decision signal,
Of the fourth 1-key, pressing the 1-key whose light-emitting part is lit up causes the light-emitting part of all 1-keys lower than the 1-key in the digit to be turned off, By pressing the 1 beads key while the part is off,
It is based on the input device of the digit which carries out the carry-up operation of turning on the light emitting portion of the one-pearl key higher than the one-pearl key in the digit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Prior to the description, firstly, the concept of carry-up and carry-down referred to in the present invention will be explained, and secondly, the carry-up and carry-down. Will be explained focusing on what kind of key operation is performed, and the judgment conditions.

As is well known, the abacus has one bead and four bead placed under it (hereinafter, the first, the second,
It is called the first and third beads. ) And a one-digit value can be displayed. For example, in the case of registering 4
All the beads can be pushed up by pushing the fourth bead up. That is, “4” is displayed and displayed at the relevant digit by one finger operation. This is the raising operation on the abacus.

On the other hand, when changing the display from "4" to "0", all the beads can be pushed down by pushing the first beads downward. This is the lowering operation on the abacus. As is apparent from this, the raising and lowering operations on the abacus also change the positions of the beads other than the beads that are directly operated.

Next, unlike the abacus, the digit input device of the present invention corresponds to the abacus beads and is arranged in substantially the same manner as the abacus beads and can be turned on and off as shown in FIG. One 5-key K with a light-emitting part 3 on the surface showing a value of 5
5 and four 1st to 4th 1-keys K1, K2, K3, K4 showing a value of 1 sequentially arranged under this 5-key K5
A key is provided.

The input key with the light emitting portion 3 lit is in a state where the beads on the abacus are pushed up (5 beads are pushed down as opposed to 1 bead, and so on). ), And the key with the light emitting unit 3 turned off corresponds to the state in which the beads are pressed down on the abacus. In other words, the movement of the beads on the abacus is image-wise displayed by turning on and off the light emitting unit 3.

Further, when the input key is directly pressed by a finger, the light emitting portion 3 of the input key is alternately turned on and off. At this time, as described on the abacus, when inputting the value of 4 when the digit display is 0 (the state where all the light emitting parts 3 are turned off), press the lowest 4th bead key K4. Press. Then, the light emitting portion 3 of the fourth bead key K4 is turned on, and the light emitting portions 3 of the first to third first bead keys K1 to K3 which are not directly operated are also turned on. This is the "advance" in the present invention.

Similarly, when the display of "4" is changed to "0" when the display is changed to "0", when the first 1-key key K1 is pressed, the first 1-key key K1 is pressed. In addition to turning off the light emitting unit 3, the light emitting units 3 of the second to fourth 1st key keys K2 to K4 that are not directly operated are also turned off. This is the "lowering" referred to in the present invention.
Is.

Here, in the digit, the 5-key K1,
As a result of checking what kind of judgment condition exists regarding which one of the first to the fourth 1-keys K1 to K4 the light-emitting section 3 is moved up and down like an abacus, the 5-key K5 is determined. It is sufficient to simply turn on and off the light emitting portion 3 by operation, and it is not related to the operation such as raising, lowering, and lowering. For the other first to fourth 1-key keys K1 to K4, the operation as shown in Table 1 is necessary. It turned out to be sex.

[0015]

[Table 1]

As is clear from Table 1, when the digit values are "0", "1", "3", and "4", the third 1
It can be understood that only the raising operation is required when the state of the bead key K3 is at the L level, while only the lowering operation is required when the state of the third first bead key is at the H level. The light emitting unit 3 shows a case in which the light is turned on at the H level and turned off at the L level.

However, when the digit value is "2", both the raising operation and the lowering operation are required even if the state of the third 1-key K3 is at the L level, and the judgment condition is still insufficient. Absent. However, even in such a case, when the operation of the first key 1 K1 is performed, that is, the first key 1 is operated.
If the condition that the light emitting portion 3 of the ball key K1 is about to change is added, it is possible to judge whether the carry-up and carry-down operations should be performed for all digit values.

In summary of the above, the third 1-key K3
When the state of H is H level, when the operation of the first 1-key key K1 is performed, in any case of the change of the digit, only the carry-down is necessary, and in other cases, the carry-up is sufficient.

In the following, the hardware capable of realizing these concretely will be described in detail, based on the above-mentioned concept of carry-up and carry-down and the above-mentioned two judgment conditions as to which of the carry-up and carry-down is to be executed when a key is operated. explain.

In this embodiment, the digit input device 1 is exemplified as an external device adopted as a desk electronic abacus CL as shown in FIG. 1.
One 5 beads key K5 showing a value of 5 arranged corresponding to one bead, and a first 1 beads key K1 showing a value of 1 which is sequentially arranged below the 5 beads key, A second 1-pearl key K2 lower than the first 1-pearl key, a third 1-pearl key K3 lower than the second 1-pearl key, a lower-first key than the third 1-pearl key K3. An input key having a number 4 key key K4, a light emitting portion 3 provided for each input key, and an operation state provided for each input key and operated by operating the input key. Switches SW1 to SW5 for outputting the key operation signal S1 (shown in FIG. 2)
The digit input unit 5 having a plurality of digits, that is, 20 digits in this embodiment, is provided.

In the present embodiment, the input key has a vertically long rectangular shape, and in FIG. 1 when the electronic abacus CL is viewed from the front in the operating state, the five-key key K5 from the top and the first one-key key K are shown.
The 1st, 2nd 1-bead key K2, the 3rd 1-bead key K3, and the 4th 1-bead key K4 are arranged in this order. Contrary to the concept of the lower order, the upper order of the fourth 1-jewel key K4 indicates the 1st to 3rd 1-jewel keys.

In the present embodiment, each input key is provided with a light-emitting portion 3 which is composed of a light-emitting diode or the like and can be turned on and off so that it can be easily visually recognized from the outside. As described above, the light emitting unit 3 may be provided so as to be exposed from the input key as in the present embodiment, or may be housed inside when the input key is made of a translucent material. That is, it is necessary to be able to confirm from outside whether the light emitting unit 3 is on or off when the electronic abacus CL is used. The light emitting section 3 is an alternative to the above-mentioned light emitting diode.
A liquid crystal whose color change can be controlled by an electric signal may be used.

Further, in this embodiment, the five bead key K5 and the first one
The gap with the pearl key K1 is set to be larger than the gap with other keys to clarify the difference between the two keys and to display characters, patterns, etc. on the surface of each key to enhance their distinguishability. It may be appropriately attached or omitted.

Each of the switches SW1 to SW5 is hung at an H level in a non-operated state by a pull-up resistor R so that an operation signal S1 for each input key can be output when the input key is pressed. Is configured.

Next, as shown in FIGS. 2 to 3, the electronic abacus CL of this embodiment has a key matrix 6 as an internal electronic circuit and one 5-key D flip-flops 16 and 4.
D-flip flops 17-2 for the 1st to 4th 1st key
A key state holding circuit 7 having 0, a register matrix 9 in which a plurality of digits are provided for the register, and key state signals of the digits are sequentially read from the register matrix 9 to turn on and off the light emitting unit 3 of each input key. And a movement determination circuit 11 for determining and executing carry-down and carry-up, which will be described later.
It has a control circuit 12 capable of outputting a time-divisional scanning signal SCN or the like capable of controlling the signal transmission timing between them.

As shown in FIG. 4, the key matrix 6 is composed of a circuit network for connecting all the switches SW1 ... In a grid pattern, and the scan signal SC issued by the control circuit 12 is supplied.
By inputting N, all digits are sequentially selected one by one, and the key operation signal SS1 of each switch SW1 ... Of this digit is sequentially received, and the received key operation signal SS is received.
In this embodiment, the key input circuit 13 (FIG.
Output).

The key input circuit 13 determines whether or not each of the input keys has been pressed for a predetermined time, and if the key has been operated for a predetermined time or longer, the operation is regarded as a key operation, so-called chattering is absorbed. To do.

The key operation signal SS1 determined by the key input circuit 13 to be a key operation is bisected for each input key in this embodiment, and one of the key operation signals S1 is inputted.
1 is input to the register matrix 9 as signals S2 and S3 whose signal states are inverted through the NOT circuit G1 and NOR circuit G2, and the other key operation signal S1 is a key to be described later in this embodiment. It is output to the duplication operation prevention circuit 14.

As shown in FIG. 5, the register matrix 9 is constituted by providing 20 registers RG consisting of D flip-flop groups 9A ... Which can store 7-bit data, according to the number of digits. . In the D flip-flop group 9A, the scanning signal SCN is clocked, the signals S2 and S3 and a key status signal ST1 to be described later are input to the D terminal via the data bus, and the Q terminal is input to the above. The signals S2, S3 and the key state signal ST1 input to the D terminal by the clock input can be stored and held, and can be output as the signals OS2, OS3 and the key state signal ST2, respectively.

Further, in this embodiment, the signal S2 which is the output of the NOT circuit G1 which is the inverted key operation signal S1 of the 5-key key K5 at the first bit of the 7 bits of the register RG is inverted.
However, the signal S3, which is the output of the NOR circuit G2 of the key operation signal S1 of the first to fourth string keys, is stored and held in different storage areas at the upper 2nd bit. Note that the remaining 5 bits appropriately store and hold the key state signal ST1 of each input key.

The light emitting display matrix 10 outputs each key status signal S output from the register matrix 9.
In the present embodiment, when the key status signal ST2 is at the L level, the light emitting section 3 of the corresponding input key is turned on, and when the key status signal ST2 is at the H level, the T2 is sequentially read out. The light emitting unit 3 is configured to be turned off.

The key duplication operation prevention circuit 14 outputs the key operation signal S1 from each key input circuit 13 and the upper first bit and the second bit stored by inverting the key operation signal S1 in the register matrix 9. It is constituted by five AND circuits G3 to G7 which output an effective key operation signal SP1 which is a logical product output with the signal OS2 or OS3 output from

Now, for example, when the key input circuit 13 outputs the key operation signal S1 (H level) of the 5-string key at an arbitrary digit by the scanning signal SCN, one of the signals is inverted by the NOT circuit G1. As the signal S2 (L level), it is stored and held in the upper 1st bit of the register RG of the relevant digit.

Further, the held L level signal S2
Is read from the output side of the register matrix 9 as OS2 and input to one terminal of the AND circuit G3. Therefore, when the 5-key key K5 is continuously pressed for a plurality of scannings of the scanning signal SCN, AN
One output end of the D circuit G3 becomes L level, and this AN
The D circuit G3 once outputs the valid key scanning signal SP1 (H level) and then does not output it again. In other words, the key input operation until the hand is released from the 5-key key K5 is limited to one time, and the duplicate operation is prohibited.

The same applies to the first to fourth 1-keys K1 to K4. However, in the present embodiment, since the storage area of the register RG is different between the 5th beads key K5 and the 1st to 4th beads keys K1 to 4, one of the 1st to 4th beads keys K1 to 4 is stored. One input key and 5 beads key K5
In this relationship, it is possible to perform overlapping operations. For example, when entering "9", key operation can be performed by simultaneously operating the 5-key K5 and the fourth 1-key K4 to improve the input speed. It is preferable because it is possible.

The valid key operation signal SP1 output from the AND circuits G3 to G7 is output to the key state holding circuit 7. This key state holding circuit 7 includes the first key and the first key.
˜One four-key D flip-flop 16 corresponding to the fourth one-jewel key and four first to four one-key D flip-flops 17 to 20 are provided.

Each of the D flip-flops 16 to 20 has
Each of the AND circuits G3 to G7 of the key duplication operation prevention circuit 14
The valid key operation signal SP1 output from the
The input signal to the D terminal can be held and output at the Q terminal as the key status signal output terminal by inputting the input signal, and an inverted signal of the Q terminal is output to the Q- terminal (note that the D terminal, the Q terminal, -The terminal is displayed only for the D flip-flop 20 for the fourth 1st key).

Q-inversion of the signal at the Q terminal which is the key status signal output terminal of each of the D flip-flops 16 to 20.
The output of the terminal is input to the D terminal of each of the D flip-flops 16 to 20 and the D terminal of the D flip-flop group 9A ... Of the register matrix 9 via the three-state buffer G13. Therefore, in the register matrix 9, the D flip-flops 16 to 20
It is stored as a key state signal ST1 having a signal level inverted from that of the terminal.

Further, the D flip-flops 16 to 20 are
In the present embodiment, the set terminal P forcibly setting the signal state of the Q terminal to the H level by inputting the L level signal and the signal of the Q terminal by inputting the same L level signal. Reset terminal R forcibly set to L level
And have.

In this embodiment, the key status signal ST2 read from the register matrix 9 is the copy signal CP of the L level of the control circuit 12 which will be described later.
Through a negative logic AND circuit G9 that outputs a logical product of
It is input to each set terminal P of 6 to 20. Also the first to third
With respect to the D flip-flops 17 to 19 for the 1-key key, the negative logic OR circuits G10 to 12 for outputting a logical sum are interposed.

The three-state buffer G13 receives a Q signal in response to the L level signal output from the control circuit 12 in the normal state.
-Transmit the signal from the terminal to the output side.

Further, the operation discriminating circuit 11 reads the key status signal S of the third key string K3 read from the Q terminal of the D flip-flop group 9A ... Of the register matrix 9.
T2 (K3) and the A corresponding to the first 1 ball key K1
The valid key operation signal SP1 of the ND circuit G4 is sent to the NOT circuit G
It has a negative logic OR circuit G16 for inputting the inverted signal SP1-and the inverted signal SP1-.

With this configuration, the negative logic OR circuit G
Reference numeral 16 indicates that when the key operation signal of the third beads key K1 is at the L level (the light emitting portion 3 is in the lighting state), or when the first beads key K1 is operated by the inversion signal SP1-. Either state, that is, one of the two conditions for realizing the carry-down described above can be detected and the L-level carry-down condition signal SD can be output.

Further, the carry-down condition signal SD is input to the negative logic AND circuit G17 together with the carry-down execution timing signal TD output from the controller 12. In addition, L output from the negative logic AND circuit G17
The carry-down decision signal D for executing the level and carry-down is
The reset terminal R of the second to fourth one-key D flip-flops 18 to 20 is connected via the negative logic OR circuit G19A.
To the negative logic AND circuits G20 to G22.

At the other end of the negative logic AND circuit G20,
The Q terminal output of the first D-shaped flip-flop D for flip key 17 is input, and similarly, the Q terminal output of the D-flip-flop D for flipped second key 18 is connected to the other end of the negative logic AND circuit G21. , And the other end of the negative logic AND circuit G22,
The Q terminal outputs of the third D-shaped flip flops 19 for the 1st key are respectively inputted.

In other words, the reset terminal R of each of the second to fourth D-type flip-flops 18 to 20 for one key is a logical product of the output of the Q terminal of the upper D flip-flop and the output of the negative logic OR circuit G19A ( Negative logic) is input.

Further, the key state signal ST2 of the first to third 1st key is inputted to the negative logic OR circuits G10 to 12 via the negative logic AND circuit G9, and the negative logic as an input signal on the other end side. The output signals of the AND circuits G24 to G26 are input.

The negative logic AND circuit G24 outputs the timing signal TU for advancing the L level output from the control circuit 12 and the D flip-flop 18 for the second one-key.
Q-terminal output signal is input to the same negative logic AND circuit G
25 is the timing signal TU and the Q-terminal output of the third D-key flip-flop 19 for the 1st key, and the negative logic AND circuit G26 is the timing signal TU and the D flip-flop for the 4th 1st key. The output of the Q-terminal of the amplifier 20 is input.

The output signals of the negative logic OR circuits G10 to G12 are input to the set terminals P of the first to third D-key flip-flops 17 to 19 for the 1st key.

Therefore, the set terminal P of the first to third one-key D flip-flops 17 to 19 is logically connected to the Q-terminal output of the next lower D flip-flop and the carry timing signal TU. The product (negative logic) is input.

Further, the control device 12 controls the timing of each circuit by the time-divided scanning signal SCN, the digit clear signal AC for initializing the value of each digit, and any digit output from the register matrix 9. In the D flip-flops 16 to 20, a copy signal CP for issuing a copy command to the Q terminals of the D flip-flops 16 to 20, a timing signal TD for carry-down to confirm the carry-down operation of the digit, and a timing signal TU for carry-up operation of the digit. In addition to outputting the L-level internal / external control signal BF and the reset signal RT for initializing all states at the normal time for controlling the signal transmission of the 3-state buffer, the effective key operation signal S
An interrupt signal IP for notifying the control device that there is a key state change is input to P1 via the negative logic OR circuit G29.

The operation of the digit input device 1 of the present invention thus constructed will be described with reference to the timing chart of FIG. 6 in the case where "4" is set in an arbitrary digit.

When the power switch PW of the digit input device 1 is turned on, the control circuit 12 first outputs the L-level reset signal RT while the scanning signal SCN circulates all digits. The reset signal RT is input to the two negative logic OR circuits G19A and G19B, respectively, and as a result, an L level signal is output from the two negative logic OR circuits G19A and G19B.

This L level signal is input to the reset terminals R of the five D flip-flops 16 to 20,
D flip-flop 1 for 5 beads and 1st beads
The outputs of the Q terminals 6 and 17 are forcibly set to the L level and the output of the Q- terminal is set to the H level.

The second D-type flip-flop 1 for the 1st key
Reference numeral 8 denotes an L-level signal output from the negative logic OR circuit G19A and a first D-key flip-flop 17 for a key.
Negative logic A to which both Q terminal output (L level) is input
When the L level output of the ND circuit G20 is input to the reset terminal R, the Q terminal output is set to the L level. Similarly, the L level is also output to the reset terminals R of the third to fourth 1st key D flip-flops 19 and 20. That is, all D flip-flops 16 to 20
Q terminal output of is initialized to L level.

All such D flip-flops 16-2
The Q-terminal output of 0 (H level) passes through the 3-state buffer G13 whose gate is always opened by the internal / external control signal BF of L level, and the D of the D flip-flop group 9A ... Input to the terminal.

Further, the control circuit 12 constantly outputs a scanning signal SCN for repeatedly scanning the first digit to the 20th digit at regular intervals. This time-division scanning signal SC
N is input to the key matrix 6 and the register matrix 9, respectively, and the key matrix 6 successively obtains the key operation signal SS1 of each key of an arbitrary digit by this scanning signal SCN.

On the other hand, the register matrix 9 inputs the scanning signal SCN as a clock signal for each D flip-flop group 9A ...
Each D flip-flop 16 to 20 initialized by T
H-level signal of the Q- terminal, which is the inverted signal of the Q terminal of
The data is held in the D flip-flop group 9A ... And is output to the Q terminal, so that all the D flip-flops 16 to 20 are initialized. In terms of timing, it is held 1
It is output after the scanning cycle.

Further, the control circuit 12 outputs an L level digit clear signal AC for initializing the digit value at the first time when each digit is selected. The digit clear signal AC has two negative logic OR circuits G19, like the reset signal RT.
It is input to A and G19B, and the Q terminal outputs of all the D flip-flops 16 to 20 are initialized to the L level.

Next, the control circuit 12 outputs an L level copy signal CP. The copy signal CP is input to one end of the negative logic AND circuit G9, but since all the Q terminals of the D flip-flop groups 9A ... Of the register matrix 9 are at the H level, the first to fifth D flip-flops. The L-level signal is not output to the set terminal of the switch and the signal state does not change. In the 7-bit register of each digit of the register matrix 9, the upper 2 bits used for the key duplication operation prevention circuit 14 are the NOT circuit G1 and
An H level signal S2 inverted by the NOR circuit G2,
It is stored and held as S3.

In order to input the value of "4" in any digit in such a state, the fourth 1-neck key K4 of the digit is pressed with a finger. When this operation is detected by the key matrix 6, the key input circuit 13 outputs the key operation signal S1 of the H-level fourth bead key K4.

The key operation signal S1 of the fourth string key K4 is divided into two and one is input to one terminal of the AND circuit G7. The H-level signal OS3 read from the output side at the position of the upper 2nd bit of the register matrix 9 is input to the other terminal of the AND circuit G7, which is the logical product output of both signals. A level valid key operation signal SP1 is output from the AND circuit G7.

On the other hand, the other halved fourth key operation signal S1 of the first string is inverted through the NOR circuit G2 and is stored in the position of the upper 2nd bit of the register matrix 9. During scanning, L level signal O
It is read out as S3.

Therefore, this is the case where the fourth key key K4 is continuously pressed and the key operation signal S1 of the fourth key key is continuously output from the key input circuit 13 at the next scanning of this digit. However, as a result of the L-level signal OS3 stored and read being input to one end of the AND circuit G7, the valid key operation signal S is output from the AND circuit G7.
P1 is preferable in that the key duplication operation can be prevented by outputting only once at the first time.

Further, the H output from the AND circuit G7
The valid key operation signal SP1 of the level is input to the clock terminal of the fourth D-shaped flip-flop 20 for the key 1 of the key state holding circuit 7. By this input, the fourth D-key D for flip-flops 20 sends the current state of the D terminal (that is, the Q-terminal), that is, the H level signal to the Q terminal at the rising edge of this clock signal. Then, the inverted signal, that is, the L level signal is output and held at the Q-terminal.

Next, the control circuit 12 first outputs the timing signal TD for lowering the L level. The timing signal TD is input to one end of the negative logic AND circuit G17. Further, the other end of the negative logic AND circuit G17 has the above-mentioned negative logic OR circuit G for determining whether or not to carry it down.
16 outputs are input.

The negative logic OR circuit G16 inverts the state of the third string key read from the D flip-flop group 9A ... The signal SP1-, which is the inversion of the key operation signal S1 of the 1st key key K1, is input.
Here, the key state signal ST2 (K3) indicating the state of the third bead key K3 is at the H level, and the first bead key K1 is not operated in this case, resulting in the signal SP1.
-Becomes H level.

Therefore, in such a case, neither of the two conditions for the carry-down is satisfied and the negative logic O for carrying-down is carried out.
The L level signal from the R circuit G16 is not output, but becomes the H level output. The negative logic AND circuit G17 which inputs the H level output to one terminal also outputs the H level signal and inputs it to one end of the negative logic OR circuit G1.
9A outputs an H level signal because the other reset signal RT and digit clear signal AC are both at H level.

Therefore, the outputs of the negative logic AND circuits G20 to G22 are all at the H level, and the reset terminals R of the first to fourth D-key flip-flops 18 to 20 for L are L.
No level signal is output. So in this case,
The carry-down operation is not performed.

Next, the control circuit 12 outputs the L-level carry timing signal TU. The timing signal TU is input to one end of the negative logic AND circuits G24 to G26. Further, the Q-terminal outputs of the second to fourth D-key flip-flops 18 to 20 for a 1-key key are input to the other ends of the negative logic AND circuits G24 to G26 as described above.

Therefore, since the Q-terminal of the fourth D flip-flop holds the L level by the key operation as described above, the negative logic AND circuit G26 makes the carry determination signal U of the L level negative. Output to the logical OR circuit G12.

Upon receipt of the L-level carry determination signal U, the negative logic OR circuit G12 outputs an L-level signal to the set terminal P of the D flip-flop 19 for the third bead key to output the third bead. In the key D flip-flop 19, the Q terminal is forcibly changed to the H level and the Q- terminal is changed to the L level, and the state is maintained.

Further, the L level output from the Q-terminal of the third D-key for the 1st key is a negative logic AN by the timing signal TU for carrying the L level forward.
The D circuit G25 outputs the L level carry determination signal U. The negative logic OR circuit G11, to which the carry determination signal U is input, outputs an L level signal to the set terminal P of the second D-key flip-flop 18 for the 1st key. Therefore, also in the second one-key D flip-flop 18, the Q terminal is forcibly changed to the H level and the Q- terminal is changed to the L level, and the state is maintained.

Further, the L-level output from the Q-terminal of the second D-shaped flip-flop 18 for the key is output from the negative logic AND circuit G24 to the carry determination signal U of the L level by the timing signal TU. Let The negative logic OR circuit G10 to which the carry decision signal U is input
Outputs a signal of L level to the set terminal P of the first D key flip flop 17 for the 1st key, and its Q terminal is held at H level and Q- terminal is held at L level.

Next, the control circuit 12 changes the time division scanning signal SCN from the L level to the H level in order to end the scanning of this digit. From the L level of this time division scanning signal to H
At the time of changing to the level, the D flip-flop group 9A ...
The output of the Q-terminals of the D-type flip-flops 16 to 20 for the 1st to 4th key is stored and retained as the inverted key state signal ST1 at its own Q terminal. That is, the 5-ball key is at the H level, and the first to fourth 1-key keys are at the L level.

Further, in the light emitting display matrix 10, the key status signal ST2 of each digit read from the output side of the register matrix 9 is used for the 5-key key and the first to fourth keys.
When the signal is read into the D-key flip-flops 16 to 20 for the bead key, this signal is halved and taken into consideration. In the present embodiment, the light-emitting portion 3 of the L-level input key is turned on as described above, and the H-level input key is turned on. The light emitting unit 3 is configured to be turned off.

Therefore, as shown in FIG. 7, all the light emitting portions 3 of the first to fourth 1st beads keys K1 to K4 are turned on only by pressing the fourth 1st beads key K4 of an arbitrary digit. It is possible to perform a carry-up operation. As described above, in the present invention, the key in which the light emitting unit 3 is lit realizes the same image as a bead that has been inserted into the abacus by means different from the abacus that moves the bead.

Next, the digit where this "4" is displayed is
The case of returning to the display of "0" will be described. In general, in the case of abacus, in such a case, it can be carried out by lowering the first bead.
This can be performed by pressing the 1st beads key K1.

That is, when the first 1-key key K1 is pressed from the above state, the AND circuit G4 outputs the valid key operation signal SP1 and the D-key for the first 1-key key of the key state holding circuit 7 is outputted. It is input to the clock terminal of the flip-flop 17. Therefore, the D flip-flop 17 outputs the current state of the D terminal, that is, the state of the L-level Q-terminal to the Q terminal at the time of the rising edge of the clock signal, and outputs the inverted signal, that is, the H level. Output and hold signal at Q-terminal.

Further, the output from the AND circuit G4 is divided into two H
The effective key operation signal SP1 of the level is the NOT circuit G15.
Is inverted to L level by the negative logic OR circuit G16.
Is input at one end of. In this case, one of the first carry-down keys K1 is operated to satisfy one of the carry-down conditions. Therefore, the negative-logic OR circuit G16 outputs the L-level carry-down condition signal SD to the negative-logic AND circuit. G17
Output to. Further, the negative logic AND circuit G17 outputs the L level carry-down decision signal D to the negative logic OR circuit G19A by the input of the carry-down timing signal TD by receiving the L-level carry-down decision signal SD.

The carry-down determination signal D is the second to fourth signals.
To the reset terminal R of the D flip-flops 18 to 20 for the 1-key key
The terminal output is input via both negative logic AND circuits G20 to G22.

Therefore, the negative logic AND circuit G20 has the same L level signal as the L level signal output from the negative logic OR circuit G19A.
L of the first D-flip flop 17 for the first level 1 key
The second Q-key D flip-flop 18 is input together with the level Q terminal output signal.
The L level signal is output to the reset terminal R of the. In other words, the second flip key D flip-flop 18 for forcibly changes the Q terminal to the L level and the Q- terminal to the H level, and maintains the state.

Similarly, the negative logic AND circuit G21 has the same L level signal as the L level signal output from the negative logic OR circuit G19A.
When the Q terminal output signal of L level 8 is also input, the third flip key D flip-flop 19 for a key is output to the reset terminal R of an L level signal.
In other words, Q of the third D-key D flip-flop 19
The terminal is at L level and the Q- terminal is at H level. Fourth D
The same applies to flip-flops.

In summary, the D flip-flop 1 for the 5 ball key is operated by operating the first 1 ball key K1.
No. 6 has no change in signal state, and its Q terminal is held at L level and its Q- terminal is held at H level. Also, the Q of the 1st to 4th D-type flip flops 17 to 20
The terminal is changed to an L level signal and the Q-terminal is changed to an H level signal and held.

Therefore, the Q of these D flip-flops
The -terminal output is stored in the register matrix 9 at the time of rising of the scanning signal SCN of this digit.
Further, by reading this state from the register matrix 9, the light emitting portions 3 of all the input keys of the relevant digit are turned off and the carry-down operation can be performed.

In this embodiment, the AND circuits G3 ...
The output of 7 is divided into two and input as an interrupt signal IP to the control circuit 12 via the NOR circuit G29. Therefore,
A CPU separately provided and connected to the control circuit 12 by informing the control circuit 12 that an input key has been operated.
In, the versatility can be enhanced by facilitating the interface such as the read timing for reading the latest key state from the digit input device and the reverse write timing.

Further, in the present embodiment, the hardware which uses the element which is particularly easy to integrate is exemplified. Especially, the one-dot chain line portion in FIG. 2 shows an element such as an independent capacitor or resistor which is not suitable for integration. By not using it,
It goes without saying that such a part can be easily integrated, which can contribute to low cost and downsizing of the device.

In addition to the above, in this embodiment, as shown in FIG. 2, an externally provided CPU is provided and connected. Therefore, the light emitting unit 3 can be forcibly turned on and off by an external CPU without key operation. At this time, the control device can communicate with each other by the interface signal CTL, and for example, the CPU forces the light emitting unit 3
When is turned on, the key operation may be invalidated by setting the internal and external control signals BF to H level. Therefore, the user of the electronic abacus CL can use the abacus as a practice machine for abacus when registering the abacus by, for example, pressing an input key that emits light, and by adding an LCD display etc. The present invention can be modified into various modes, such as a system in which the visibility can be improved by displaying the number with a numeral and the operability for a beginner of abacus can be assisted.

[0089]

As described above, according to the present invention, each digit of the numerical data to be inputted can be inputted to each of the plural digit input sections, and as a result, the numerical data always has an idea of scale. It can be handled as a whole, and it is possible to reduce the occurrence of digit errors due to the increase in the number of digits, and by turning on and off the light emitting part provided on the key, it is possible to express an image similar to the movement of the abacus beads, so the input result from the outside Can be easily confirmed, and the usability can be improved by an abacus expert.

Furthermore, the digit input device of the present invention can be interfaced with the outside, and the digit input result can be easily used for calculation by a computer, CPU, etc. and the display of the result, and only hardware resources are required. The digit input device can be realized by this, and electronic circuits can be integrated.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is an electrical block diagram of the present embodiment.

FIG. 3 is an electric circuit diagram of the present embodiment.

FIG. 4 is a circuit diagram illustrating a key matrix.

FIG. 5 is a circuit diagram illustrating a register matrix.

FIG. 6 is a timing chart of the present embodiment.

FIG. 7 is a diagram illustrating the operation of the present invention.

[Explanation of symbols]

 2 Main body section 3 Light emitting section SW1 to 5 switch 5 digit input section 6 Key matrix 7 Key state holding circuit 9 Register matrix 10 Light emitting display matrix 11 Operation determination circuit 12 Control circuit 13 Key input circuit 14 Key duplicate operation prevention circuit 16 5 beads key D flip-flop 17 for the first 1-ball key 18 D-flip flop for the 2nd 1-key 19 D flip-flop for the 3rd 1-key 20 D flip-flop for the 4th 1-key

Claims (2)

[Claims] 1. A five-ball abacus on the surface of the main body, one 5-bead key indicating a value of 5, which is arranged corresponding to one bead, and one each placed one below the five-bead key. First indicating the value of
The 1st Pearl Key, the 2nd 1 that is lower than this 1st Pearl Key
An input key consisting of a pearl key, a third pearl key lower than the second pearl key, and a fourth pearl key lower than the third pearl key, and each input key is provided. A plurality of digits input section having a light emitting section provided for each of the input keys and a switch for operating the input keys to output a key operation signal indicating an operation state corresponding to the input keys, A key matrix capable of sequentially receiving the key operation signals of all the switches of each digit input section based on the input time-divided scanning signals and sequentially outputting the received key operation signals, and outputting from this key matrix. The key operation signal of each of the input keys is input as a clock signal, and the state of each of the input keys is alternately inverted by the input of this clock signal so that the key state signal is transmitted. And a key state output terminal capable of storing and storing as a key, a D flip-flop for one 5-key key corresponding to the five-key key and the first-fourth key key, and four D-flip-flops for one first-four key key. And a register capable of storing a key state signal of each input key stored and held in the D-flip flops for the 5-key key and the first to fourth 1-key keys for each input key. By having a register matrix provided with a plurality of digits, and a light emission display matrix for sequentially reading each key status signal of the digits from the register matrix and causing the light emitting unit of each input key to emit light and extinguish in response to the signal. In each of the digits, each time the input key is operated, the light emitting unit of the directly operated input key alternately repeats lighting and extinguishing, and When the key string signal of the third string key of the register matrix of the operated digit is in a signal state for lighting the light emitting portion, or when the key string is operated from the key matrix. When any one of the states is detected when the key operation signal for operating the first ball key is output, the state is output to the D flip prop of the input key lower than the operated input key. To output a carry-down determination signal for inverting the key state signal, and output a carry-down determination signal for inverting the key state signal by being output to the D flip-flop of a key higher than the key operated by non-detection of the state. By providing an operation discriminating circuit for outputting, by pressing one of the 1st to 4th beads of each digit whose light-emitting section is lit, the digit is pressed. Definitive 1
By lowering the light emitting parts of all the 1 bead keys lower than the bead key and turning off the light emitting part of the bead key, pressing the 1 bead key when the light emitting part is off, the 1 key above the 1 bead key
A digit input device that performs a raising operation to turn on the light emitting part of the pearl key. 2. The register matrix can store and hold an inversion signal obtained by inverting one signal obtained by halving the key operation signal output from the key matrix, separately for a 5-key key and a 1-key key. At least two storage areas are provided, and between the key matrix and the key state holding circuit,
By interposing an AND circuit capable of outputting a logical product of the other one of the halved key operation signals and the inversion signal stored in the register matrix as a clock signal to the D flip-flop when the scanning signal is input. 2. The digit input device according to claim 1, further comprising a key duplication operation prevention circuit capable of inhibiting a duplication operation when the input key is continuously pressed for several cycles of the scanning signal.