JPH08107402A - Data receiving circuit - Google Patents

Abstract

PURPOSE: To provide a data receiving circuit with which the phases of a clock signal and received data can be matched only with simple hardware configuration. CONSTITUTION: A received signal 23 is latched by a flip flop 33 synchronously with a clock signal 12 and latched by a flip flop 31 synchronously with an inverted clock signal 12A, and those latched data are further latched by a flip flop 32 synchronously with the clock signal 12. On the other hand, a received clock generating circuit 22 generates a received clock 24 synchronized with the received signal 23. A phase comparator circuit 36 detects phase difference between the received clock 24 and the clock signal 12 and corresponding to that phase difference, the switching of a switching circuit 34 is controlled. When this detected phase difference is larger than a reference value, the switching circuit 34 selects latch data D1 of the flip flop 33 but when the phase difference is smaller, latch, data D2 of the flip flop 32 are selected and defined as received data 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving circuit of a bidirectional data transmitting / receiving apparatus having an interface for sharing a clock signal for transmitting / receiving a data signal with an external device for transmission and reception.

[0002]

2. Description of the Related Art FIG. 6 shows a schematic configuration of a bidirectional data transmission / reception apparatus to which the present invention is applied. This data transmission / reception device is used, for example, for personal computer communication or data communication between computers.

In FIG. 6, transmitting / receiving devices 1 and 2 are devices for performing bidirectional data communication, and external devices 3 and 4 such as a personal computer or a computer are connected thereto. The one transmitter / receiver 1 includes a receiver circuit 5 and a transmitter circuit 6, and the other transmitter / receiver 2 includes a receiver circuit 7 and a transmitter circuit 8 to perform data communication using optical space transmission or the like as a communication medium 9. .

The data transmitted between the transmitter / receivers 1 and 2 is transferred to the external devices 3 and 4, and the transfer interfaces 10 and 11 include a clock signal 12, transmission data 13 and reception data 14. , The interface signal is passed to the receiving circuits 5 and 7 and the transmitting circuits 6 and 8. That is, the transmission circuits 6 and 8 perform the transmission operation by the transmission data 13 and the clock signal 12, and the reception circuits 5 and 7
Outputs the reception data 14 to the external devices 3 and 4 in synchronization with the clock signal 12. In this way, the clock signal 12 for exchanging data signals with the external devices 3 and 4 is shared by transmission and reception. In this case, the received data 14 has a cycle N times that of the clock signal 12, for example.

In the receiving circuits 5 and 7, the phase of the received data 14 and the clock signal 12 are conventionally matched as shown in FIG. Since the receiving circuits 5 and 7 have the same configuration, only one receiving circuit 5 will be described here.

The reception circuit 5 comprises a buffer device 21 and a reception clock generation circuit 22, and the reception clock 2 is synchronized with the reception signal 23 by the reception clock generation circuit 22.
4 is generated, and the reception signal 23 is generated by the reception clock 24.
Are stored in the buffer device 21. Then, the received data accumulated in the buffer device 21 is output to the external device 3 in synchronization with the clock signal 12 on the interface so that the clock signal 12 and the received data 14 are phase-matched.

[0007]

However, the conventional method of providing the buffer device 21 for performing the phase adjustment not only has a complicated circuit configuration provided with a microcomputer and a shift register, but also transmits and receives data. Depending on the format, transmission speed, etc., it may be necessary to change the software or hardware.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data receiving circuit capable of performing phase matching between a clock signal and received data with a simple hardware configuration.

[0009]

The present invention provides a data receiving circuit of a bidirectional data transmitting / receiving apparatus having an interface for sharing a clock signal for transmitting / receiving a data signal with an external device for transmission data and reception data. ,
A reception clock generation circuit that generates a reception clock synchronized with the received signal, a one-stage flip-flop that latches the received signal in synchronization with the clock signal of the interface, the received signal with the clock signal and this A two-stage flip-flop that latches the clock signal inverted in synchronism with the inverted clock signal, a phase difference detecting means for detecting the phase difference between the received clock and the clock signal of the interface, and this phase difference detecting means. When the phase difference is larger than the reference value, the latch data of the one-stage flip-flop is selected, and when the phase difference is smaller than the reference value, the phase difference is smaller than the reference value.
And a means for selecting latched data of the flip-flop of the stage and outputting it as received data.

[0010]

The reception clock generation circuit generates a reception clock synchronized with the received signal. Also, the received signal is
The flip-flops are latched in one-stage flip-flops in synchronization with the interface clock signal, and are latched in two-stage flip-flops in synchronization with the clock signal and an inverted clock signal obtained by inverting the clock signal. Further, the phase difference between the received clock and the clock signal is detected by the phase difference detecting means, and the detected phase difference is compared with the reference value. If the phase difference is larger than the reference value, the latch data of the one-stage flip-flop is selected, and if the phase difference is smaller than the reference value, the latch data of the two-stage flip-flop is selected and externally received as the reception data. Output to the device.

As described above, depending on the phase difference between the clock signal and the received clock, one-stage flip-flop or two flip-flops are provided.
By switching the data latched in the flip-flops of the stages and using it as the received data, the phase of the clock signal and the received data can be matched with only a simple hardware configuration.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. In the present invention, the reception circuit 5 of the transmission / reception device 1 in FIG. 6 is configured as shown in FIG. Note that FIG. 1 shows a main part of the receiving circuit 5. Also,
The receiving circuit 7 in the transmitting / receiving apparatus 2 has the same configuration as the receiving circuit 5, and thus detailed description thereof will be omitted.

The reception circuit 5 inputs the reception signal 23 to the reception clock generation circuit 22 and also inputs it to the data input terminals D of the D-type flip-flops 31 and 33, and further outputs the output signal of the flip-flop 31 to the D-type flip-flop. Data is input to the data input terminal D of the group 32. The clock signal CK is applied to the clock terminal CK of the flip-flop 31.
2 is inverted by the inversion circuit 35, and the inverted clock signal 1
Input as 2A. In addition, the flip-flop 32,
The clock signal 12 is directly input to the clock terminal CK 33. And the flip-flop 3
The output signals of 2, 33 are switched by the switching circuit 34,
The received data 14 is sent to the external device 3. The switching circuit 34 performs a switching operation according to the signal from the phase comparison circuit 36.

The phase comparison circuit 36 has a NAND (NAN)
D) The gate 41, the integrating circuit 42 and the comparing circuit 43 are provided, and the clock signal 12 and the reception clock 24 from the reception clock generating circuit 22 are input to the NAND gate 41. Then, the output of the NAND gate 41 is fed to the integrating circuit 4
2 and the integrated output is compared with the reference value by the comparison circuit 43 to obtain the clock signal 12 and the reception clock 2
The magnitude of the phase difference with respect to 4 is detected, and the switching circuit 34 is switched based on the phase difference. That is, the switching circuit 34
Selects the once latched data D1 latched in the flip-flop 33 when the phase difference between the clock signal 12 and the reception clock 24 is larger than the reference value, and when the phase difference is smaller than the reference value, the flip-flop It operates to select the twice latched data D2 latched in the flip-flop 32 via 31.

Next, the operation of the above embodiment will be described. When the reception signal 23 is input to the reception circuit 5, the reception signal 23
Is first latched in the flip-flop 33 in synchronization with the clock signal 12 and is once output to the switching circuit 34 as the latch data D1. Further, the received signal 23 is latched by the flip-flop 31 in synchronization with the inverted clock signal 12A output from the inversion circuit 35, and the latched data is further latched by the flip-flop 32 in synchronization with the clock signal 12 and 2 The time latch data D2 is output to the switching circuit 34.

On the other hand, the reception clock generation circuit 22 generates a reception clock 24 synchronized with the reception signal 23 and inputs it to the phase comparison circuit 36. The phase comparison circuit 36 detects the phase difference between the reception clock 24 and the clock signal 12 and outputs a switching signal to the switching circuit 34 according to the magnitude of the phase difference. The switching circuit 34 operates according to the switching signal from the phase comparison circuit 36, and the clock signal 1
When the phase difference between 2 and the reception clock 24 is larger than the reference value, the once latched data D1 latched in the flip-flop 33 is selected, and when the phase difference is smaller than the reference value, the flip-flop 31 is used. The twice latched data D2 latched in the flip-flop 32 is selected.
In this way, the switching circuit 34 switches the once latched data D1 or the twice latched data D2 and outputs it as the received data 14 to the external device 3.
Can be reliably synchronized with the clock signal 12.

The operation of synchronizing the received data 14 with the clock signal 12 will be described in detail below. Figure 2
FIG. 4 is a timing chart for explaining the relationship between the received data 14 and the clock signal 12.

As shown in FIGS. 2 (a) and 2 (b), the clock signal 12 and the received data 14 are required to have the same phase, that is, a synchronized relationship. However, the received signal 2
3 has a phase that does not match the clock signal 12 as shown in (c), it is necessary to latch the reception signal 23 with the clock signal 12 in order to perform the phase matching. In the reception signal 23, for example, one cycle of data indicates "1" or "0", and code information is indicated by a predetermined bit length.

The phase of the received signal 23 is the clock signal 1
If it is deviated by about 180 ° with respect to 2, the received signal 2
By latching 3 in the flip-flop 33 with the clock signal 12, the once latched data D1 shown in (d) can be obtained, and the received data 14 synchronized with the clock signal 12 can be obtained.

Further, when the received signal 23 is close to the original data timing of (b) as shown in (e), latching with the clock signal 12 causes latching in an unstable state due to waveform distortion or the like. Become. Therefore, in this case, first, the reception signal 23 is latched in the flip-flop 31 by the inverted clock signal 12A shown in (f) to obtain the latch data shown in (g), and this latched data is flip-flopted by the clock signal 12. Latch on the hoop 32 (h)
The clock signal 12 and the transmission data 13 can be synchronized by obtaining the latch data D2 twice as shown in FIG.

That is, the phase difference of the received signal 23 with respect to the original data phase shown in (b) above is + 90 ° to 2 °.
In the case of about 70 °, the once latched data D1 of (d) is used, and in the case of 0 ° to + 90 ° and 270 ° to 360 °, the twice latched data D2 of (h) is used. Therefore, the received data 14 and the clock signal 12 can be phase-aligned stably regardless of the phase shift of the received signal 23.

Next, the operation of the phase comparison circuit 36 for detecting the phase shift of the received signal 23 will be described with reference to FIGS. The phase comparison circuit 36 detects the phase shift of the reception signal 23 by comparing the phase difference between the reception clock 24 output from the reception clock generation circuit 22 and the clock signal 12. The clock signal 12 shown in FIG. 3A and the reception clock 24 shown in FIG. 3C synchronized with the reception signal 23 shown in FIG. 3B are input to the NAND gate 41. As a result, from the NAND gate 41, (d)
As shown in, a signal corresponding to the phase difference is output. In this case, the signal output from the NAND gate 41 has substantially the same pulse width as that of the clock signal 12 as shown in FIG. 4A when the phases of the clock signal 12 and the reception clock 24 are substantially the same. Have. On the other hand, when the phase difference is close to 180 °, the “L” level portion becomes a very narrow pulse as shown in FIG. Also,
If the phase difference is between 0 ° and 180 °,
As shown in (b), the pulse width is between (a) and (c).

The pulse signal output from the NAND gate 41 is integrated by the integrating circuit 42 and becomes a signal having a level corresponding to the pulse width as shown in FIG. That is,
The phase difference between the clock signal 12 and the reception clock 24 is 0 °
When changing at 360 °, the value of the integrated output is V0 / 2 → V0 → V when the ON voltage of the NAND gate 41 is V0.
It changes to 0/2. This integrated output is sent to the comparison circuit 43, and a switching signal is output to the switching circuit 34 by comparison with the threshold voltage VR as a reference value. That is, the comparison circuit 43 sets the threshold voltage VR to V0 / V0 as shown in FIG.
Between 2 and V0, the latch data D1 is selected once in the portion B where the integrated output is larger than the threshold VR, and twice in the portion A and C where the integrated output is smaller than the threshold VR. A switching signal is output to the switching circuit 34 so as to select D2.

As described above, the phase difference between the clock signal 12 on the interface and the received clock 24 is detected by the phase comparison circuit 36, and the switching circuit 34 is controlled to switch in accordance with the magnitude of the phase difference, so that one-stage flip-flop is used. Once latched data D1 latched by the flip-flop 33 or twice latched data D latched by the two-stage flip-flops 31, 32
By using 2 as the reception data 14, the phase alignment of the clock signal 12 and the reception data 14 can be performed stably.

[0025]

As described above in detail, according to the present invention, the phase difference between the clock signal on the interface and the received clock is detected, and the one-stage flip-flop or the two-stage flip-flop is latched by the phase difference. Since the received signal is switched and used as the received data, the phase of the clock signal and the received data can be surely matched with only a simple hardware configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data receiving circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a relationship between received data and a clock signal in the embodiment.

FIG. 3 is a timing chart for explaining a phase comparison operation between a clock signal and a reception clock in the embodiment.

FIG. 4 is a diagram showing a pulse output waveform of a NAND gate according to a phase difference between a clock signal and a received clock in the embodiment.

FIG. 5 is an operation explanatory diagram of the phase comparison circuit in the embodiment.

FIG. 6 is a block diagram showing an overall schematic configuration of a data transmission / reception device which is an object of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional data receiving circuit.

[Explanation of symbols]

 1, 2 Transmitter / receiver 3,4 External device 5,7 Receive circuit 6,8 Transmitter circuit 9 Medium 10, 11 Interface 12 Clock signal 13 Transmitted data 14 Received data 21 Buffer device 22 Received clock generating circuit 23 Received signal 24 Received clock 31 , 32, 33 D-type flip-flop 34 Switching circuit 35 Inversion circuit 36 Phase comparison circuit 41 NAND gate 42 Integration circuit 43 Comparison circuit

Claims (1)

[Claims] 1. A data receiving circuit of a bidirectional data transmitter / receiver having an interface for sharing a clock signal for transmitting / receiving a data signal with an external device for transmission data and reception data, reception in synchronization with a received signal. A reception clock generation circuit for generating a clock, a one-stage flip-flop for latching the received signal in synchronization with the clock signal of the interface, an inverted clock obtained by inverting the received signal with the clock signal and the clock signal. Two-stage flip-flops that latch in synchronization with signals, phase difference detection means for detecting the phase difference between the received clock and the clock signal of the interface, and the phase difference detected by the phase difference detection means and the reference value. If the phase difference is greater than the reference value, Data receiving circuit selects the latch data, when the phase difference is less than the reference value, characterized by comprising a means for outputting the received data by selecting the data latched in the flip-flop of the two-stage.