JPH08107344A - Cmos output circuit - Google Patents

Abstract

PURPOSE: To obtain a CMOS output circuit in which production of a through- current is prevented. CONSTITUTION: A P channel MOS transistor(TR) 1, an N-channel MOS TR 2 are connected in series between a high voltage power supply Vcc and a low voltage power supply GND, and an input signal IN is inputted to the gates of the TRs 2, 1 as in-phase gate signals SG3, SG4 via inverter circuits 1c, 1d respectively. An output signal OUT is outputted from an output terminal To connecting to the drains of both TRs 1, 2. The input signal IN and the gate signals SG3, SG4 are inputted to a control circuit 5, which provides an output of a control signal used to invert the gate signal of a TR being a nonconductive state to the inverter circuits 1c, 1d after the gate signal of a TR in the conductive state based on the inversion of the input signal IN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS output circuit used as an output circuit of a semiconductor integrated circuit device.

In recent years, semiconductor integrated circuit devices have been used in various portable electronic devices. In such a portable electronic device, it is necessary to reduce power consumption in order to reduce the size and weight of the power supply. Therefore, it is necessary to reduce the power consumption of the output circuit of the semiconductor integrated circuit device used in the portable electronic device.

[0003]

2. Description of the Related Art As a conventional example, an output circuit of a switching regulator will be described with reference to FIG. Input signal IN is C
It is input to the input terminals of the MOS inverter circuits 1a and 1b. The inverter circuits 1a and 1b are supplied with a power source Vcc as a high potential side power source and a ground GND as a low potential side power source.

The output signal SG1 of the inverter circuit 1a
Is input to the gate of an N-channel MOS transistor Tr2 forming the CMOS output circuit 2, and the output signal SG2 of the inverter circuit 1b is input to the gate of a P-channel MOS transistor Tr1 forming the CMOS output circuit 2.

The source of the output transistor Tr1 is connected to the power source Vcc, and the source of the output transistor Tr2 is connected to the ground GND. The output transistor T
The drains of r1 and Tr2 are connected to the output terminal To via the inductance L and also to the cathode of the diode D. The anode of the diode D is connected to the ground GND. The output terminal To has a capacitance C
Is connected to the ground GND via.

When the pulse signal shown in FIG. 5 is input as the input signal IN, the output circuit thus configured is inverted by the inverter circuits 1a and 1b to output the output signals SG1 and SG2. , To the gates of the output transistors Tr1 and Tr2.

Then, the output transistors Tr1 and Tr2 are alternately turned on, the drain currents I1 and I2 alternately flowing through the output transistors Tr1 and Tr2, and the diode D,
Due to the action of the inductance L and the capacitance C, the output terminal T
A constant voltage output signal OUT is output from o.

[0008]

In the above output circuit, the output transistors Tr1 and Tr2 are large in size,
Since the gate capacitance is large, if the frequency of the input signal IN becomes high, the inverter circuits 1a, 1
The time in which the output signals SG1 and SG2 of b are at the H level and the L level is relatively long in the rising and falling transient states.

Then, in this transient state, at the time t1 when both the output signals SG1 and SG2 are at the intermediate level between the power source Vcc and the ground GND, the transistors Tr1 and Tr2 are provided.
At the same time, drain currents I1 and I2 flow, and a through current flows from the power supply Vcc to the ground GND.

When such a shoot-through current occurs, a predetermined voltage may not be output as the output signal OUT, which may cause a malfunction of the circuit of the next stage. Moreover, the power consumption increases due to the through current, and the transistors Tr1 and Tr2
The temperature may rise or the element may be destroyed.

An object of the present invention is to provide a CMOS output circuit capable of preventing the occurrence of shoot-through current.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, the P-channel MOS transistors Tr1 and N1 are connected between the high potential side power source Vcc and the low potential side power source GND.
The channel MOS transistor Tr2 is connected in series,
The input signal IN is input as the in-phase gate signals SG3 and SG4 to the gates of the transistors Tr2 and Tr1 via the inverter circuits 1c and 1d, respectively. The output signal OUT is output from the output terminal To connected to the drains of the transistors Tr1 and Tr2. The input signal IN and the gate signals SG3 and SG4 are input to the control circuit 5, and the control circuit 5 inverts the gate signal of the transistor in the ON state based on the inversion of the input signal IN,
A control signal for inverting the gate signal of the transistor in the off state is output to the inverter circuits 1c and 1d.

Further, as shown in FIG. 2, the control circuit is
An OR circuit 3 to which the input signal IN is input, a gate signal SG4 of the P-channel MOS transistor Tr1 is input via an inverter circuit 1f, and the input signal IN are input, and the N-channel MO is input.
A gate signal SG3 of the S-transistor Tr2 is composed of an AND circuit 4 which is input via an inverter circuit 1e,
The output signal of the OR circuit is input to an inverter circuit that drives the N-channel MOS transistor, and the AN
The output signal of the D circuit is input to the inverter circuit that drives the P channel MOS transistor.

[0014]

When the input signal IN is inverted, the control circuit 5 turns off the transistor which has been turned on until then, and turns on the transistor which has been turned off until then.

In FIG. 2, when the input signal IN rises from the L level to the H level, the output signal of the AND circuit 4 becomes the H level after the N channel MOS transistor Tr2 is turned off, and the P channel MOS transistor Tr1.
Is turned on. When the input signal IN falls from the H level to the L level, the P channel MOS transistor T
After r1 is turned off, the output signal of the OR circuit 3 becomes L level, and the N-channel MOS transistor Tr2 is turned on.

[0016]

2 shows an embodiment in which the present invention is embodied in an output circuit of a switching regulator. The same components as those in the conventional example will be described with the same reference numerals.

The input signal IN is the OR circuit 3 and the AND circuit 4
Is input to The output signal of the OR circuit 3 is input to the inverter circuit 1c. The output signal SG3 of the inverter circuit 1c is input to the gate of the output transistor Tr2 and the inverter circuit 1e, and the output signal SG5 of the inverter circuit 1e is input to the AND circuit 4.

The output signal SG6 of the AND circuit 4 is input to the inverter circuit 1d, and the output signal SG4 of the inverter circuit 1d is input to the gate of the output transistor Tr1 and the inverter circuit 1f. The output signal SG7 of the inverter circuit 1f is input to the OR circuit 3.

Next, the operation of the output circuit configured as described above will be described. When the input signal IN is at L level, AN
The output signal SG6 of the D circuit 4 becomes L level, and the output signal SG4 of the inverter circuit 1d becomes H level. Then, since the output signal SG7 of the inverter circuit 1f becomes L level and the output signal of the OR circuit 3 becomes L level, the output signal SG3 of the inverter circuit 1c becomes H level.

Then, the output transistor Tr1 is turned off, the output transistor Tr2 is turned on, and the drain current I2 flows through the output transistor Tr2. Next, when the input signal IN rises to the H level, the output signal SG3 of the inverter circuit 1c gently falls due to the gate capacitance of the output transistor Tr2, the output transistor Tr2 is turned off, and the drain current I2 is cut off.

When the output signal SG3 falls below the threshold value V1 of the inverter circuit 1e, the output signal SG5 of the inverter circuit 1e rises to the H level. Then AND
The output signal SG6 of the circuit 6 rises to the H level, and the output signal SG4 of the inverter circuit 1d falls gently due to the gate capacitance of the output transistor Tr1.

Then, the output transistor Tr1 is turned on and the drain current I1 flows. Also, the output signal SG4
Becomes lower than the threshold value V2 of the inverter circuit 1f, the output signal SG7 of the inverter circuit 1f becomes H level.

Therefore, when the input signal IN changes from the L level to the H level, the output transistor Tr2 is turned off and then the output transistor Tr1 is turned on, so that no through current flows through the transistors Tr1 and Tr2.

Next, when the input signal IN falls to L level, the output signal SG6 of the AND circuit 4 becomes L level, and the output signal SG4 of the inverter circuit 1d rises gently based on the gate capacitance of the output transistor Tr1. Then, the output transistor Tr1 is gradually turned off,
The drain current I1 of the output transistor Tr1 decreases.

When the output signal SG4 of the inverter circuit 1d exceeds the threshold value V2 of the inverter circuit 1f, the output signal SG7 of the inverter circuit 1f becomes L level. At this time, the output transistor Tr1 is completely turned off and the drain current I1 is cut off.

Then, the output signal of the OR circuit 3 becomes L level, and the output signal SG3 of the inverter circuit 1c rises gently due to the gate capacitance of the output transistor Tr2. Then, the output transistor Tr2 is turned on and the drain current I2 flows. When the output signal SG3 becomes equal to or higher than the threshold value V1 of the inverter circuit 1e, the output signal SG5 of the inverter circuit 1e becomes L level.

Therefore, when the input signal IN shifts from the H level to the L level, the output transistor Tr1 is turned off and then the output transistor Tr2 is turned on, so that no through current flows through the transistors Tr1 and Tr2.

As described above, in this output circuit, the CMOS
When the input signal IN of the output circuit 2 is inverted, the gate capacitance of the output transistors Tr1 and Tr2 can be used to turn off the other transistor prior to the on operation of one transistor.

Therefore, it is possible to prevent the generation of a through current flowing through the output transistors Tr1 and Tr2.

[0030]

As described above in detail, the present invention is a CMO.
It is possible to prevent the occurrence of shoot-through current in the S output circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a waveform diagram showing the operation of one embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a waveform diagram showing an operation of a conventional example.

[Explanation of symbols]

 1c, 1d Inverter circuit 5 Control circuit Vcc High potential side power supply GND Low potential side power supply SG3, SG4 Gate signal Tr1 P channel MOS transistor Tr2 N channel MOS transistor To output terminal IN input signal OUT output signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiaki Sano 1844-2 Kozoji Town, Kasugai City, Aichi Prefecture

Claims (2)

[Claims] 1. A P between a high potential side power source and a low potential side power source.
A channel MOS transistor and an N-channel MOS transistor are connected in series, an input signal is input to each gate of the transistors as an in-phase gate signal through an inverter circuit, and an output signal is output from an output terminal connected to the drains of both transistors. A CMOS output circuit that outputs the input signal and the gate signal to a control circuit, and the control circuit turns off after the gate signal of the transistor in the on state is inverted based on the inversion of the input signal. A CMOS output circuit, which outputs a control signal for inverting a gate signal of the transistor in a state to the inverter circuit. 2. The control circuit receives the input signal, an OR circuit to which the gate signal of the P-channel MOS transistor is input via an inverter circuit, and the input signal to the control circuit. An AND circuit to which a gate signal of an N-channel MOS transistor is input via an inverter circuit is provided, and an output signal of the OR circuit is input to an inverter circuit which drives the N-channel MOS transistor, and an output signal of the AND circuit. Is input to an inverter circuit that drives the P-channel MOS transistor.
The described CMOS output circuit.