JPH0810551B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a circuit suitable for suppressing a transient current or suppressing a pulse voltage amplitude.

[Conventional technology]

Conventionally, when charging and discharging a large load capacity at high speed, it has been considered a problem that the transient current becomes excessive. For example, in a dynamic random access memory (DRAM) using a dynamic memory cell, an excessive transient current when charging / discharging a large number of data lines at once is a problem. A solid-state device conference digest, pp.307-310, a voltage limiter circuit system as shown in FIG. 1 has been proposed.

[Problems to be solved by the invention]

However, this method charges the data line using the internal power supply voltage that drops the external power supply voltage in the chip,
Only by realizing a low current by effectively lowering the power supply voltage, charging was in an open state.

In addition, the charging transient current, which changes in response to changes in the load driving capacity of the transistor due to variations in the gate length or threshold voltage of MOS transistors due to manufacturing variations, is not actively controlled, so there is a limit to lowering the current. was there.

An object of the present invention is to provide a semiconductor device that realizes a low transient current that does not depend on manufacturing variations, etc. by performing charge / discharge of a load capacity with a predetermined constant current. Another object of the present invention is to provide a semiconductor device with low transient current and low power consumption by combining with a voltage limiter circuit system.

[Means for solving problems]

The above object is to provide a first MOS transistor, a second MOS transistor whose drain and gate are connected,
A current source connected in series to the source / drain path of the second MOS transistor, an internal circuit to which the output current flowing through the source / drain path of the first MOS transistor is input, and the output current A comparator for comparing the magnitude relationship between the voltage of the node of the internal circuit that flows and a reference voltage, and the second comparator based on the output of the comparator and the pulse signal.
Control means for controlling whether or not the potential formed at the connection point by the MOS transistor and the current source is transmitted to the gate of the first MOS transistor on the chip, By controlling the control means, the potential is connected to the gate of the first MOS transistor to start the supply of the output current to the internal circuit, and the voltage of the node of the internal circuit reaches the reference voltage. Then, the output of the comparator controls the control means to change the potential to the first level.
It is achieved by a semiconductor device characterized in that transmission to the gate of the MOS transistor is stopped to stop the output current.

[Action]

By transmitting the potential of the connection point formed by the second MOS transistor and the current source to the gate of the first MOS transistor, the current flowing through the source / drain path of the first MOS transistor has a constant value. Therefore, the peak current is reduced and the quick charge is performed as much as possible. The first and second MOS transistors and the current source only maintain the output current at a constant value. If this is left as it is, the output voltage may rise and the internal circuit may be destroyed. The output voltage is limited to a certain value or less by the means.

〔Example〕

An embodiment of the circuit of the present invention will be described below with reference to FIG. 1 and its operation timing with reference to FIG.

In DRAM, one of the data pair lines is used as a memory cell (one
There is an example of a memory cell including a MOST and one capacitor), and charging is performed by a well-known sense amplifier formed by pMOST. In this case, the latest megabit DRAM requires high speed charging of 1024 pairs of data lines at the same time. Since the total capacitance of this data line reaches 500 to 1000 pF, overcurrent becomes a problem. This charging is performed by the drive circuit DRV connected to the common line cl of the flip-flop which is also the sense amplifier formed by pMOST. The present embodiment is characterized in that this drive circuit is composed of a current mirror circuit and a comparator. The current mirror circuit includes transistors Q ₁ and Q
It is controlled by a kind of inverter consisting of _two . When Q ₂ is on and Q ₁ is off, a current mirror circuit is formed between Q ₃ and the constant current source (i / n) and output drive transistor Q _D, and Q ₂ is off and Q ₁ is on. If _QD is off. If the current source in the mirror circuit is i / n, the gate width of the MOST is w / n, and the gate width of Q _D is w, the ON current of Q _D is the constant power supply i. Even if w or the gate length or the threshold voltage of the transistor changes due to variations in the manufacturing process, the constant driving current of Q _D becomes constant if i / n is kept constant. The constant current source is set to i / n, w / n here because the current consumption is small,
In addition, the occupied area is reduced, and the larger n is, the better.

The comparator has a predetermined internal power supply V _CL (eg 4
V) and the output voltage V _O. The output of the comparator becomes a high voltage when V _CL > V _O , and becomes a low voltage when V _CL <V _O. V _CL may be generated from V _CC (externally applied power supply voltage) in the chip.

 The operation will be described based on the above preparations.

In normal DRAM, the data line is
Since it is a so-called half precharge method that is set to almost half the value of V _CL , the common drive line cl or all data pair lines are precharged to V _CL / 2 during the precharge period. When a pulse is applied to the selected word line in this state, a minute differential read signal appears on each data pair line. This state is representatively shown in FIG. 2 with D _O , _O symmetry. After that, in the sense amplifier formed by nMOST and pMOST, the low voltage side is discharged to 0V and the high voltage side is charged to V _CL . Discharge is common drive line cl ′ of each nMOST
By applying a low voltage pulse to the. Here, only an example of charging by the pulse applied to the common drive line cl of the pMOST will be described below. cl is driven by applying an input pulse φ. When the input pulse φ is turned on (high voltage is input), the output voltage of the control circuit AND becomes high voltage, and the gate voltage V _G of Q _D becomes the output voltage of the constant current source.
It becomes V _S , and Q _D drives the load with a constant current i. As a result, the load voltage V _O rises at a constant rate from V _CL / 2, but when it exceeds V _CL , the comparator operates and the output of the control circuit AND becomes a low voltage, turning on Q _{1 and} turning on Q _2. Turns off, Q _D turns off, and V _O is clamped to almost V _CL . This charges one of the data pair lines from V _CL / 2 to approximately V _CL .

The above embodiment is an example of constant current by combining with a voltage limiter using a comparator. However, even when the voltage limiter is not used (when there is no output loop of the comparator), the mirror circuit can be controlled by the input pulse φ, so that the constant current can be obtained. A circuit using a well-known bipolar transistor is suitable as the constant current source. The response time of the comparator, V _O The faster than the response time of the release V _O is because it is close as possible to V _CL, it is also possible to configure the comparator in such a bipolar transistor suitable for high speed in some cases . Further, the idea of the present invention can be applied to the driving of the common drive line cl ′ of the sense amplifier composed of nMOST. With this, the charge waveform and the discharge waveform can be arbitrarily controlled. For example, if both waveforms are completely complementary, the noise that couples from the data line to other conductors (Si substrate, word line, etc.) can be completely canceled, and a memory with a wide operating margin can be designed.

Further, the present invention is not limited to the application to the data line charging circuit of DRAM, and the transient current is a particular problem. When applied to the data output section of all memories having a multi-bit configuration (configuration in which a plurality of data outputs are output from one chip) or the address output section of a microcomputer or the like, it is effective as a countermeasure against transient current.

〔The invention's effect〕

As described above, according to the present invention, since the supply current started by the pulse signal is limited to a certain value or less, the peak current of the semiconductor device is reduced, and the current is supplied while maintaining the constant value as much as possible. Can charge the load rapidly,
Further, by making the voltage applied to the internal circuit lower than the reference voltage by the comparator and the control means, the breakdown of the elements in the internal circuit is prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram in which the present invention is applied to a DRAM chip, and FIG. 2 is a diagram showing operation timing of the present invention. DRV: Constant current, constant voltage drive circuit V _CL : Comparison voltage

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/04 (72) Inventor Yoshiki Kawajiri 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Central Inside the research institute (72) Takao Watanabe 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Takayuki Kawahara 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (56) ) References JP-A-60-95620 (JP, A)

Claims (7)

[Claims] 1. A first MOS transistor, a second MOS transistor having a drain and a gate connected to each other, a current source connected in series to a source / drain path of the second MOS transistor, and An internal circuit to which an output current flowing through the source / drain path of the first MOS transistor is input, and a comparator for comparing the magnitude relation between the voltage of the node of the internal circuit through which the output current flows and a reference voltage, According to the output of the comparator and the pulse signal, the second
Control means for controlling whether or not the potential formed at the connection point between the MOS transistor and the current source is transmitted to the gate of the first MOS transistor is provided on the chip, and the control is performed by the pulse signal. Controlling the means to connect the potential to the gate of the first MOS transistor to start the supply of the output current to the internal circuit, and the voltage of the node of the internal circuit reaches the reference voltage. At times, the output of the comparator controls the control means to stop the transfer of the potential to the gate of the first MOS transistor to stop the output current. . 2. The semiconductor device according to claim 1, wherein the first MOS transistor and the second MOS transistor form a current mirror circuit, and the first and second MOS transistors have the same structure. A source is connected to a power supply voltage, a drain of the first MOS transistor is connected to the internal circuit, a drain and a gate of the second MOS transistor are connected to the current source, and the first MOS is connected. A semiconductor device characterized in that the gate of the transistor and the gate of the second MOS transistor are connected via a first switch means, and the first switch means is controlled by the pulse signal. 3. The semiconductor device according to claim 2, wherein the gate width of the first MOS transistor is equal to that of the second M transistor.
A semiconductor device characterized by being larger than the gate width of the OS transistor. 4. The semiconductor device according to claim 3, wherein the first MOS transistor and the second MOS transistor are P-channel MOS transistors. 5. The semiconductor device according to any one of claims 1 to 4, wherein the internal circuit is a semiconductor memory. 6. The semiconductor device according to claim 5, wherein the semiconductor memory is a dynamic random access memory, and the output current flows through a sense amplifier drive line of the dynamic random access memory. Semiconductor device. 7. The semiconductor device according to any one of claims 1 to 6, wherein the internal circuit includes a data output section of the chip.