JPH08102505A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To reduce fabrication cost by reducing the number of fabrication steps. CONSTITUTION: In the first step, poly-Si film 4 is deposited, as a first conductive film, on the surface of a semiconductor substrate 1 and an insulation film 5 is deposited on the film 4 as shown at (a). The insulation film 5 is then patterned in the first region 1a of the semiconductor substrate 1 as shown at (b). In the second step, a WSi film 6 is deposited as a second conductive film on the poly-Si film 4 while covering the pattern of the insulation film 5 as shown at (c). In the third step, a resist film 7 is patterned in the second region 1b of the semiconductor substrate 1 as shown at (d). In the fourth step, the poly-Si film 4 and the WSi film 6 are removed by anisotropic etching as shown at (e). In the fourth step, the anisotropic etching is effected to leave the poly-Si film 4 in the first region 1b while the poly-Si film and WSi film 6 are left in the second region 1b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including, for example, a MOS transistor and a resistor or a bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, the gate of a MOS transistor is n ⁺
In the case of forming with polycide which is a laminated structure of type polysilicon (Poly-Si) and refractory metal silicide, polycide is formed separately from the polycide in order to reduce the resistance of the gate.
A resistor made of -Si is formed. FIG. 8 shows a conventional example of a method for manufacturing a semiconductor device including a MOS transistor having such a polycide gate and a resistor.

In the conventional method, as shown in FIG. 8A, a field oxide film 51 is first formed on the surface 50 of a substrate made of silicon (Si). After that, the field oxide film 51
A polycide gate 56 formed by sequentially stacking a gate oxide film 53, an n-type Poly-Si film 54, and a tungsten silicide (WSi) film 55 is formed on the surface of the substrate 50 in the element formation planned region 52 surrounded by. Form. Then, for example, an n ⁻ -type LDD (Lightly Doped Drain) region 57, an n ⁺ -type source / drain region 58, and the like are formed on the base body 50 of the element formation planned region 52.

Next, as shown in FIG. 8B, silicon oxide (S) is formed on the entire surface of the substrate 50 including the polycide gate 56.
An iO ₂ ) film 59 is formed. Then, the p-type Poly-Si film 60 is formed on the SiO ₂ film 59 on the field oxide film 51.
A pattern of the resistor 61 is formed. And FIG.
As shown in (c), S in the state in which the Poly-Si film 60 is included.
After forming the insulating film 62 on the iO ₂ film 59, poly-Si
A contact hole 63 and a wiring 64 which communicate with the film 60 and the source / drain region 58 are formed. Through the above steps, the semiconductor device 66 including the MOS transistor 65 of the polycide gate 56 and the resistor 61 is formed.

[0005]

As described above, according to the conventional method, the polycide forming the gate cannot be used to form the resistor, and therefore the poly-Si for the resistor is formed separately from the gate.
A film is formed and patterned. For this reason, the number of manufacturing steps is increased, resulting in an increase in manufacturing cost. The present invention has been made to solve the above problems,
It is an object of the present invention to provide a semiconductor device manufacturing method capable of reducing the number of manufacturing steps and manufacturing costs.

[0006]

According to a first method of the present invention for solving the above problems, first, in a first step, a first conductive film and an insulating film are sequentially formed on a surface of a semiconductor substrate. Then, an insulating film pattern is formed in the first region of the semiconductor substrate. Next, in a second step, a second conductive film is formed on the first conductive film so as to cover the pattern of the insulating film. Then, in a third step, a pattern of a resist film is formed on the second region of the semiconductor substrate. Further, in the fourth step, anisotropic etching is performed to remove the first conductive film and the second conductive film to manufacture a semiconductor device. In this fourth step,
Anisotropic etching is performed so as to leave the first conductive film in the first region and leave the first conductive film and the second conductive film in the second region.

In the second method, first, the first step of the first method is performed. At that time, the first conductive film is formed of a material containing at least silicon as a main component. In the second step, a refractory metal film is formed on the first conductive film so as to cover the pattern of the insulating film. After that, heat treatment is performed to cause a silicidation reaction between the first conductive film other than the first region and the refractory metal film,
A second conductive film made of a silicide film is formed. Further, the unreacted refractory metal film is removed. Then, the third step and the fourth step of the first method are sequentially performed.

The unreacted refractory metal film removed in the second step of the second method can be removed by anisotropic etching in the third step without performing the second step.

Further, in the first method and the second method, a step of introducing impurities into the first conductive film other than the first region by using the pattern of the insulating film as a mask between the first step and the second step. You may go. Alternatively, a step of introducing an impurity into at least one of the first conductive film and the second conductive film other than the first region is performed between the second step and the third step by using the pattern of the insulating film as a mask. May be. Further the first method,
In each third step of the second method, it is possible to form the resist film pattern in the second region of the semiconductor substrate so as to overlap a part of the insulating film pattern in the first region.

The second conductive film of each of the first method and the second method is made of WSi, for example. The first conductive film formed in the first step has, for example, boron (B) or boron difluoride (BF ₂ ) introduced therein.

[0011]

According to the first method of the present invention, the pattern of the first conductive film is formed in the first region by one-time anisotropic etching, and at the same time, the same first conductive film as that of the first region is formed in the second region. A pattern including the film and the second conductive film is formed.

In the second method, the silicidation reaction is performed using the pattern of the insulating film as a mask, so that the first conductive film remains in the first region. Furthermore, by performing anisotropic etching once in the same manner as described above, a pattern made of the first conductive film is formed in the first region, and at the same time, in the second region, the same first conductive film as the first region and the first conductive film are formed. A pattern composed of two conductive films is formed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the first method and the second method of the present invention will be described below with reference to the drawings. FIG. 1 is a process diagram showing a first embodiment of the first method, showing a case where a resistor is formed in a first region of a semiconductor substrate and an nMOS transistor gate is formed in a second region.

First, the first step shown in FIGS. 1A and 1B is performed. That is, using the existing LOCOS technology,
Thermal oxidation is performed at 50 ° C. for about 120 minutes, and FIG.
As shown in FIG.
A field oxide film 2 having a thickness of about m is formed. At this time, the field oxide film 2 is formed so as to surround the second region 1b of the semiconductor substrate 1. A part of the region where the field oxide film 2 is formed becomes the first region 1a. Thereafter, although not shown, the oxidation mask such as a nitride film used in the LOCOS technique is removed by etching.

Then, thermal oxidation is carried out at about 950 ° C. for about 18 minutes to apply 2 to the surface of the semiconductor substrate 1 in the second region 1b.
A gate oxide film 3 having a thickness of about 0 nm is formed. Then, the temperature is about 650 ° C. by a chemical vapor deposition method (hereinafter, referred to as a CVD method).
Field oxide 2 and gate oxide 3 at the temperature of
A Poly-Si film 4 is formed on top. This becomes the first conductive film. The film thickness of the Poly-Si film 4 is, eg, about 150 nm.

Next, the entire surface of the Poly-Si film 4 is doped with an impurity that determines the resistance value of the resistor 8 to be formed. The impurity to be doped may be the same n-type as the gate 9 to be formed, but a p-type such as B or BF ₂ having a small temperature dependence of the resistance value is desirable. For example, the sheet resistance is 2kΩ
When forming a p-type resistor 8 of about / □, BF ₂ is 30
Ions may be implanted at a keV of about 4.5 × 10 ¹⁴ cm ^-2 .

Then, as shown in FIG. 1B, S is formed on the Poly-Si film 4 at a temperature of about 400 ° C. by the CVD method.
an insulating film 5 made of iO ₂ formed to a thickness of about 150 to 300 nm. Subsequently, after forming a resist film (not shown) on the insulating film 5, the resist film is patterned by lithography, and further, for example, with a mixed gas system of oxygen (O ₂ ) / trifluoromethane (CHF ₃ ). Perform anisotropic etching. Then, the Po of the first region 1a of the semiconductor substrate 1 is
A pattern of the insulating film 5 is formed on the ly-Si film 4.

Next, in the second step shown in FIG. 1C, CV
The WSi film 6 is formed on the Poly-Si film 4 at a temperature of about 400 ° C. by the D method. This becomes the second conductive film. WS
The i film 6 is formed in a state of also covering the pattern of the insulating film 5, and is formed to have a film thickness of, for example, about 100 nm.

Then, using the pattern of the insulating film 5 as a mask, impurities are doped into at least one of the first conductive film and the second conductive film other than the first region 1a. This doping is a doping for forming the gate 9.
In the first embodiment, since the second conductive film is formed of the WSi film 6, for example, P is added to the Poly-Si film 4 of the first conductive film.
Ion implantation is performed at 5 keV and 5 × 10 ¹⁵ cm ^-2 . The ion implantation may be performed before forming the WSi film 6, that is, after forming the pattern of the insulating film 5.

Next, in the third step shown in FIG. 1D, W
A resist film 7 is formed on the Si film 6. After that, a pattern of the resist film 7 is formed on the WSi film 6 in the second region 1b by lithography.

Subsequently, in a fourth step shown in FIG. 1 (e), anisotropic etching using a mixed gas system of, for example, sulfur hexafluoride (SF ₆ ) / dichlorotetrafluoroethane (C ₂ Cl ₂ F ₄ ). I do. Then, Poly-S is added to the first area 1a.
The i-film 4 is left and the Poly-Si film 4 and WS are formed in the second region 1b.
The Poly-Si film 4 and the WSi film 6 are removed while leaving the i film 6 left. Then, the resist film 7 is removed.

Through the above steps, the poly in the first area 1a is formed.
The pattern of the resistor 8 made of the -Si film 4 is formed, and the gate 9 of polycide having a laminated structure of the Poly-Si film 4 and the WSi film 6 is formed in the second region 1b. When manufacturing a semiconductor device including an nMOS transistor having a resistor 8 and a gate 9, the following steps are further performed.

FIG. 2 is a sectional view of a semiconductor device formed according to the first embodiment. As shown, after the fourth step,
An n ⁻ type LDD region 10 and an n ⁺ type source / drain region 11 are formed on the semiconductor substrate 1 in the second region 1b by the existing technique. Then, the gate 9 and the insulating film 5
Of the insulating film 1 on the entire surface of the semiconductor substrate 1 including the pattern of
2, a Poly-Si film 4, which forms a resistor 8;
A contact hole 13 and a wiring 14 which communicate with each of the source / drain regions 11 are formed. By performing the above process, n of the resistor 8 and the gate 9 of polycide is
A semiconductor device including the MOS transistor 15 is formed.

In the first embodiment described above, the pattern of the insulating film 5 is the same as the poly of the first region 1a during anisotropic etching.
-It serves as a protective film for the Si film 4 and also serves as an etching mask. Therefore, the pattern of the resistor 8 made of the Poly-Si film 4 is formed in the first region 1a by one-time anisotropic etching, and at the same time, the Poly-Si film 4 and WSi are formed in the second region 1b.
A polycide gate 9 consisting of the film 6 is formed.

Therefore, the step of etching the pattern of the resistor 8 separately from the gate 9 is not required, so that the number of manufacturing steps can be reduced as compared with the conventional method,
Manufacturing costs can be reduced.

Further, in the above embodiment, when a high-concentration p-type impurity such as B or BF ₂ is introduced to the entire surface of the Poly-Si film 4 in order to form the p-type resistor 8 different from the n-type gate 9. A p-type impurity is also introduced into the Poly-Si film 4 in the gate 9 portion. However, since the second conductive film is formed of the WSi film 6, the n-type gate 9 can be easily formed even if p-type impurities are introduced into the Poly-Si film 4 in the gate 9 portion. This is for the following reasons.

That is, in the first embodiment, in order to form a surface channel nMOS transistor, polycide is n-type doped. Therefore, in the first step, Poly-Si
When the n-type impurity is ion-implanted on the entire surface of the film 4, the n-type impurity concentration of the Poly-Si film 4 of the gate 9 is sufficiently high and the Poly-Si film 4 is degenerated. However, the n-type resistor 8
Has a drawback that its resistance value has a large temperature dependency.

In the p-type resistor 8, the temperature dependence of the resistance value is n.
It has the advantage of being small, about half the size of the mold. When the p-type resistor 8 is formed, as in the above-described embodiment, the Po process is performed in the first step.
P-type impurities are ion-implanted into the ly-Si film 4. However, when p-type impurities are ion-implanted, the p-type ions cancel out the n-type ions introduced into the Poly-Si film 4 in the second step, and the n-type impurity concentration of the Poly-Si film 4 of the gate 9 is lowered. . As a result, when a voltage is applied to the gate 9,
A depletion layer may spread in the Poly-Si film 4.

However, when the gate 9 is formed of tungsten (W) polycide of the Poly-Si film 4 and the WSi film 6 as in the first embodiment, at the time of forming the source / drain regions 11 to be added in a later step. The p-type impurity introduced into the Poly-Si film 4 is diffused into the WSi film 6 by a thermal process such as annealing. That is, the p-type impurities introduced into the Poly-Si film 4 are absorbed in the WSi film 6. As a result, the p-type impurity concentration in the Poly-Si film 4 of the gate 9 decreases.

As an example, B concentration in the Poly-Si film 4, P
The concentration is about 2 × 10 ²⁰ cm ^-3 , about 900
FIG. 3 shows the SIMS analysis result of the B concentration in the W polycide when the heat treatment was performed at 20 ° C. for about 20 minutes. As shown in the figure, Poly-Si, which originally had about 2 × 10 ²⁰ cm ⁻³
It can be seen that the B concentration in the film 4 decreased to about 2 to 5 × 10 ¹⁸ cm ⁻³ after the heat treatment, and conversely, the WSi film 6 increased to about 1 × 10 ²¹ cm ⁻³ .

On the other hand, since the P introduced into the Poly-Si film 4 is not sucked up by the WSi film 6, the P concentration in the Poly-Si film 4 is 2 × 10 ²⁰ cm ^{-3 although not shown.}
The degree remains high. The B concentration remaining in the Poly-Si film 4 is about 40 to 1/100, and
Membrane 4 degenerates with little effect. Therefore, by forming the second conductive film with the WSi film 6 and forming the gate 9 made of W polycide, the p-type resistor 8 is formed.
The n-type gate 9 can be easily formed also when forming the.

In the first embodiment, the poly of the first conductive film is
After the formation of the -Si film 4, impurities that determine the resistance value of the resistor 8 are introduced into the Poly-Si 4, but the Poly-Si
It is also possible to introduce impurities when the film 4 is formed. Further, in the first embodiment, the first conductive film is formed of the Poly-Si film 4 and the second conductive film is formed of the WSi film 6, but the present invention is not limited to this. For example, the second conductive film may be formed of W, titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (M).
It is also possible to use a refractory metal such as o) and platinum (Pt) or a silicide film thereof.

In order to form the gate 9 having a conductivity type different from that of the resistor 8, impurities are introduced in the second step. If the conductivity types of the resistor 8 and the gate 9 are the same, the impurity introducing step is performed. You don't have to.

Next, a second embodiment of the first method will be described. FIG. 4 is a process chart of the second embodiment, and FIG.
It is a reduction top view of (a). In the second embodiment, after performing the same steps as the first and second steps of the first embodiment, FIG.
The third step shown in (a) and FIG. 5 is performed. For convenience of description, the WSi film 6 is omitted in FIG.

That is, the resist film 7 is formed on the WSi film 6. Then, by lithography, the first region 1
A pattern of the resist film 7 is formed on the WSi film 6 in the second region 1b in a state of overlapping a part of the pattern of the insulating film 5 of a. Then, similar to the fourth step of the first embodiment, anisotropic etching is performed using the pattern of the insulating film 5 and the pattern of the resist film 7 as a mask, and then the resist film 7 is removed.

In the second embodiment, since the pattern of the resist film 7 is formed so as to overlap a part of the pattern of the insulating film 5, after the anisotropic etching, the pattern shown in FIG.
As shown in (b), the pattern of the gate 9 and the resistor 8 is W.
It is formed in a state of being connected by the Si film 6. Therefore,
In the step of forming the contact hole 13 and the wiring 14 after forming the insulating film 12 on the entire surface of the semiconductor substrate 1, it is not necessary to form the contact hole 13 and the wiring 14 for connecting the gate 9 and the pattern of the resistor 8. Become. Therefore, according to the second embodiment, the wiring process can be simplified.

Next, a third embodiment of the first method will be described with reference to the process chart shown in FIG. The semiconductor device according to the third embodiment is a bipolar device having a two-layer Poly-Si structure (hereinafter, referred to as Bip).
This is an example of manufacturing a BiCMOS having a transistor. Here, B is formed in the first region of the semiconductor substrate.
The base electrode of the ip transistor is formed, and M is formed in the second region.
The gate of the OS transistor is formed. Further, the emitter and collector of the Bip transistor are formed in the third region of the semiconductor substrate. The collector of the Bip transistor is omitted in FIG.

First, as shown in FIG. 6A, the field oxide film 2 is formed on the surface of the semiconductor substrate 1 made of Si in the same manner as the first step of the first embodiment. At that time, the field film 2 is formed so as to surround the second region 1b and the third region 1c. A part of the region where the field oxide film 2 is formed becomes the first region 1a. Then, the second thermal oxidation is performed.
A gate oxide film 3 is formed in the region 1b, and an oxide film (not shown) is formed on the surface of the semiconductor substrate 1 in the third region 1c.

Next, the oxide film in the third region 1c is removed by lithography and etching. Then, as a first conductive film is formed on the entire surface of the semiconductor substrate 1 by the CVD method.
The ly-Si film 4 is formed. The film thickness of the Poly-Si film 4 is, eg, about 150 nm. Next, the entire surface of the Poly-Si film 4 is doped to form the base electrode 21. For example
P-type BF _{2 is applied} to the entire surface of the Poly-Si film 4 at 30 keV and 3 keV.
Ion implantation is performed at about 10 ¹⁵ cm ^-2 . Base electrode 21
In order to reduce the resistance, the p-type impurity concentration is higher than that of the resistance 8 described in the first embodiment.

Then, in the same manner as in the first embodiment, Poly-S is used.
An insulating film 5 made of SiO ₂ is formed on the i film 4. Further, by lithography and anisotropic etching, Poly-S of the first region 1a and the third region 1c of the semiconductor substrate 1 is
The pattern of the insulating film 5 is formed on the i film 4. Then, in the same manner as the second step of the first embodiment, a second film is formed on the Poly-Si film 4.
A WSi film 6 as a conductive film is formed. The WSi film 6 is formed so as to cover the pattern of the insulating film 5 as well.
It is formed to a film thickness of about nm.

Then, using the pattern of the insulating film 5 as a mask, impurities are doped into at least one of the first conductive film and the second conductive film other than the first region 1a and the third region 1b. This doping is a doping for forming the gate 9. In the third embodiment, since the second conductive film is formed of the WSi film 6, P is ion-implanted into the Poly-Si film 4 of the first conductive film at, for example, 25 keV and 5 × 10 ¹⁵ cm ^-2 . The ion implantation may be performed after forming the pattern of the insulating film 5 and before forming the WSi film 6.

Then, similarly to the third step of the first embodiment, a pattern of the resist film 7 is formed on the WSi film 6 in the second region 1b. Then, as shown in FIG. 6B, the first
Anisotropic etching is performed in the same manner as in the fourth step of the embodiment to leave the Poly-Si film 4 in the first region 1a and the third region 1c and the Poly-Si film 4 and the WSi film in the second region 1b. The poly-Si film 4 and the WSi film 6 are removed while leaving 6 and 6. Then, the resist film 7 is removed.

By the above steps, the Poly in the first region 1a is formed.
The base electrode 21 made of the -Si film 4 is formed, and the polycide gate 9 having a laminated structure of the Poly-Si film 4 and the WSi film 6 is formed in the second region 1b.

After removing the resist film 7, a two-layer Poly-Si layer is formed by further performing the step shown in FIG.
A BiCMOS having a Bip transistor having a structure is formed. That is, for example, an n ⁻ type LDD region 10 and an n ⁺ type source / drain region 11 are formed in the semiconductor substrate 1 of the second region 1b by the existing technique. After that, the semiconductor substrate 1 including the pattern of the gate 9 and the insulating film 5 is included.
An insulating film 12 is formed on the entire surface of the.

Further, after forming the contact hole 24 reaching the semiconductor substrate 1 in the third region 1c forming the emitter 22, the p-type diffusion layer 25 is formed in the semiconductor substrate 1 below the contact hole 24. The Poly-Si film 4
Since a high-concentration p-type impurity B is introduced into the p-type diffusion layer 26, a p ⁺ -type diffusion layer 26 is formed around the p-type diffusion layer 25 of the semiconductor substrate 1 by, for example, annealing at the time of forming the source / drain regions 11. Are formed.

Next, after forming the n ⁺ type Poly-Si film 28 on the insulating film 12 including the surface of the contact hole 24, the pattern of the Poly-Si film 28 is formed in the third region 1c. Then, the Po formed on the surface of the contact hole 24
An insulating film 29 is further formed on the entire surface of the insulating film 12 except on the ly-Si film 28, and the Poly-Si film 4 in the first region 1b is further formed.
A contact hole 13 and a wiring (not shown) that communicate with each of the source / drain regions 11 are formed. As a result, the Bip transistor 23 having the two-layer Poly-Si structure and the nMOS transistor 1 having the polycide gate 9 are formed.
5 is formed.

Also in the third embodiment, the pattern of the gate 9 and the pattern of the base electrode 21 are formed by one-time anisotropic etching. Therefore, the Bip CMOS including the Bip transistor 23 having the two-layer Poly-Si structure and the nMOS transistor 15 having the polycide gate 9 can be manufactured in a smaller number of steps and at a lower cost than the conventional method.

In the above embodiment, the Poly-S of the gate 9 is used.
The i film 4 is doped with B and P in an amount of about 2 × 10 ²⁰ cm ⁻³ . However, since the second conductive film forming the polycide is formed of the WSi film, WSi film is formed in the subsequent thermal process.
Membrane 6 absorbs B, the concentration of B is 2-5 × 10 ¹⁸ cm
^-Decrease to around ^-3 . As a result, Poly-S of gate 9
The i film 4 is highly n-doped and degenerates. Therefore, even when the p-type base electrode 21 is formed,
The mold gate 9 can be easily formed.

In the Bip transistor 23 having the two-layer Poly-Si structure, when the base electrode 21 is formed of W polycide, for example, p-type impurities in Poly-Si of W polycide, for example, B is absorbed in WSi of W polycide. Be done. Then, the p-type impurity concentration in Poly-Si is reduced, B diffusion into the semiconductor substrate 1 is suppressed, and the contact resistance between Poly-Si and Si of the semiconductor substrate 1 increases. Therefore, when the Bip transistor 23 having the two-layer Poly-Si structure is formed, the base electrode 21 is not formed of W polycide, and as described in the third embodiment, Poly-Si is used.
It is desirable to form by.

Next, an example of the second method of the present invention will be described with reference to the process chart shown in FIG. In this embodiment, the resistor is formed in the first region of the semiconductor substrate and the gate of the nMOS transistor is formed in the second region. First, the first of the first method
The first step described in the embodiment is performed. Then, the second step shown in FIG. 7A is performed.

In the second step, a refractory metal film made of, for example, Ti, W, Co, Ni, Mo and Pt is formed on the Poly-Si film 4 of the first conductive film. In this embodiment, for example, by using a mixed gas system of tungsten hexafluoride (WF ₆ ) / hydrogen (H ₂ ), a first CVD method at about 700 ° C. is performed.
A W film 31 is formed on the Poly-Si film 4 which is a conductive film. The W film 31 is formed so as to cover the pattern of the insulating film 5 as well, and has a film thickness of, for example, about 80 nm. The W film 31 may be formed by a sputtering method.

After that, at a temperature of about 700 to 800 ° C., 1
Annealing is performed for about 0 to 30 minutes. By performing the annealing, as shown in FIG.
The poly-Si film 4 and the W film 31 undergo a silicidation reaction.
Then, WSi is formed on the Poly-Si film 4 other than the first region 1a.
The film 6 is formed. Further, the W film 31 on the patterning of the insulating film 5 remains unreacted.

Then, similar to the second step of the first embodiment, impurities are doped into at least one of the first conductive film and the second conductive film other than the first region 1a. In this embodiment, since the second conductive film is made of WSi,
For example, P is added to the Poly-Si film 4 at 25 keV, 5 × 10 ¹⁵ c
Ion implantation is performed at about m ⁻² .

Next, in a third step, as shown in FIG. 7B, the unreacted W film 31 is selectively removed by using, for example, wet etching. Then, similarly to the third step of the first embodiment, a pattern of the resist film 7 is formed on the WSi film 6 in the second region 1b. And the fourth of the first embodiment
Anisotropic etching is performed as in the process. Note that the unreacted W film 31 is formed by the Poly-Si film 4,
It may be removed at the same time as the WSi film 6 or may be removed by dry etching before anisotropic etching.

Through the above steps, the poly in the first region 1a is formed.
The pattern of the p-type resistor 8 formed of the -Si film 4 is formed, and the n-type polycide gate 9 having a laminated structure of the Poly-Si film 4 and the WSi film 6 is formed in the second region 1b. .

In this embodiment, since the pattern of the insulating film 5 in the first region 1a is used as a mask for the silicidation reaction,
The Poly-Si film 4 remains in the first region 1a. Further, similarly to the first embodiment of the first method, the pattern of the resistor 8 and the polycide of the gate 9 can be formed by one-time anisotropic etching. Therefore, the manufacturing cost can be reduced because the manufacturing can be performed with a smaller number of steps as compared with the conventional method.

In the above embodiment, as the first conductive film,
Although the Poly-Si film 4 is formed, it is not limited to this as long as it is made of at least a material containing Si as a main component. Further, in order to form a gate 9 having a conductivity type different from that of the resistor 8,
Although the impurities are introduced in the second step, if the resistance 8 and the gate 9 have the same conductivity type, it is not necessary to perform the impurity introduction step.

Further, in the above embodiment, the W of the second region 1b is
The pattern of the resist film 7 was formed on the Si film 6 while being completely separated from the pattern of the insulating film 5. However,
As in the second embodiment of the first method described above, the resist film 7
It is also possible to form the pattern in a state of overlapping a part of the pattern of the insulating film 5. By forming as described above, the gate 9 and the pattern of the resistor 8 can be connected by the WSi film 6 and the W film 31.

The numerical values used in the description of each of the above embodiments are examples, and the values are not limited to those values.

[0060]

As described above, according to the first method of the present invention, the anisotropic etching is performed once using the insulating film pattern and the resist film pattern as a mask, and the first region is first etched. At the same time that a pattern made of a conductive film can be formed, the second
The same pattern of the first conductive film and the second conductive film can be formed in the region. Therefore, it is possible to manufacture a semiconductor device with a smaller number of steps than the conventional one.
The manufacturing cost can be reduced. According to the second method, since the silicidation reaction is performed by using the pattern of the insulating film in the first region as a mask, the first conductive film can be left in the first region. Since anisotropic etching is performed using the pattern of the insulating film and the pattern of the resist film as a mask,
The same effect as the first method can be obtained.

[Brief description of drawings]

FIG. 1 is a process drawing showing a first embodiment of the first method.

FIG. 2 is a cross-sectional view of a semiconductor device formed according to the first embodiment.

FIG. 3 is a graph showing the results of SIMS analysis of B concentration in W polycide.

FIG. 4 is a process drawing showing a second embodiment of the first method.

5 is a reduced plan view of FIG.

FIG. 6 is a process drawing showing a third embodiment of the first method.

FIG. 7 is a process chart showing an example of a second method.

FIG. 8 is a process chart showing a conventional example of a method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 1a First Region 1b Second Region 4 Poly-Si Film (First Conductive Film) 5 Insulating Film 6 WSi Film (Second Conductive Film) 7 Resist Film 31 W Film (Refractory Metal Film)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/3205 27/04 21/822 H01L 27/04 P

Claims (6)

[Claims] 1. A first step of sequentially forming a first conductive film and an insulating film on a surface of a semiconductor substrate, and then forming a pattern of the insulating film in a first region of the semiconductor substrate, and a step of forming the pattern of the insulating film. A second step of forming a second conductive film on the first conductive film in a covered state; a third step of forming a resist film pattern in the second region of the semiconductor substrate; and anisotropic etching. Removing the first conductive film and the second conductive film in a state where the first conductive film is left in the first region and the first conductive film and the second conductive film are left in the second region; A method of manufacturing a semiconductor device, which comprises four steps. 2. A first conductive film made of at least a material containing silicon as a main component and an insulating film are sequentially formed on a surface of the semiconductor substrate, and then a pattern of the insulating film is formed in a first region of the semiconductor substrate. And a heat treatment is performed after forming a refractory metal film on the first conductive film in a state of covering the pattern of the insulating film.
A second step of forming a second conductive film formed by silicidation reaction of the first conductive film and the refractory metal film other than the region, and further removing the unreacted refractory metal film; A third step of forming a resist film pattern in the second region, and anisotropically etching to leave the first conductive film in the first region and the first conductive film and the second conductive film in the second region. A method of manufacturing a semiconductor device, comprising: a fourth step of removing the first conductive film and the second conductive film while leaving the second conductive film. 3. A first conductive film made of at least a material containing silicon as a main component and an insulating film are sequentially formed on a surface of the semiconductor substrate, and then a pattern of the insulating film is formed in a first region of the semiconductor substrate. And a heat treatment is performed after forming a refractory metal film on the first conductive film in a state of covering the pattern of the insulating film.
A second step of forming a second conductive film formed by the silicidation reaction of the first conductive film and the refractory metal film other than the region; and a step of forming a resist film pattern in the second region of the semiconductor substrate. Anisotropic etching is performed to remove the unreacted refractory metal film in the first region, leave the first conductive film in the first region, and remove the first conductive film in the second region. A method of manufacturing a semiconductor device, comprising: a fourth step of removing the first conductive film and the second conductive film while leaving the conductive film and the second conductive film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern of the insulating film is used as a mask between the first step and the second step. A step of introducing impurities into the first conductive film other than the first region is performed, or the pattern other than the first region is used as a mask between the second process and the third process. A method of manufacturing a semiconductor device, which comprises performing a step of introducing impurities into at least one of the first conductive film and the second conductive film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, the pattern of the resist film is one of the patterns of the insulating film in the first region. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is formed in the second region of the semiconductor substrate while being overlapped with the portion. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductive film is made of tungsten silicide and is formed in the first step. Is a method for manufacturing a semiconductor device, wherein boron or boron difluoride is introduced.