JPH08101791A - Circuit and method for processing variable length bit data - Google Patents

Abstract

PURPOSE: To shorten the processing time and to increase the data processing speed by providing a latch of 3 words in total and plural selectors and a subtractor constituting a barrel shift means. CONSTITUTION: When barrel shift is used, data is right or left shifted by plural bits at a time in response to one clock. The number of bits by which data is shifted in response to one clock is determined by the extent of shift given from a subtractor 30. Consequently, a barrel shifter 16 selects 32 bits b0 to b31 given from second and third registers 20 and 22 or '0' in accordance with the extent of shift indicated by the subtractor 30. Data is barrel-shifted by a required number of bits as the result, and shifted-out bits are lost by barrel shift, and '0' is written in these bits. Thus, variable length bit data is taken out at a higher speed with the simple circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-length bit data processing circuit and method, and more particularly to an efficient memory (without a blank space) such as compressed data of images and sounds.
The present invention relates to a processing circuit and method for processing stored variable length bit data.

[0002]

2. Description of the Related Art An example of a variable length bit data processing circuit of this type is disclosed in Japanese Patent Application Laid-Open No. 4-245778, which was published on September 2, 1992.
This prior art includes a 1-word shift register (11) for holding input code data, and a 3-word shift register (12) for holding data transferred in parallel from the shift register (11), The shift / transfer control unit (30) cuts out and transfers the data in the shift register (11) by an amount that fills the data margin portion in the shift register (12).

[0003]

In the prior art, since the previous unnecessary data is serially shifted by the shift register (12) and discharged, a total of four words of the shift register and those shift registers Shift / transfer control for controlling the shift operation is required. Although details of the shift / transfer control are not disclosed, a counter for counting the number of shifts, a shift clock control circuit, a transfer control circuit for parallel transfer of an arbitrary number of bits of data from the shift register 11 to the shift register 12, Also, a sequencer or the like is required, and the circuit scale becomes large. Further, in order to connect the next data with the bit stream, the margin bits are shifted by the shift register (12) by the amount pushed out by the shift register (11) and written to the shift register (11) in bit units, The conventional technology has a problem in that the number of processing steps is increased and the time for fetching data is long.

Therefore, a main object of the present invention is to provide a data processing circuit and method capable of extracting variable-length bit data with a simple circuit and at a higher speed.

[0005]

SUMMARY OF THE INVENTION According to the present invention, there is provided a 1-word first register for holding data provided in bit parallel, and 1 in which data from the first register is received in bit parallel.
The second register of the word, the third register of one word from which the variable length bit data is taken out, the effective bit number is compared with the remaining bit number of the data held in the second register, and the effective bit number is larger than the remaining bit number. When the comparing means outputs the first signal, and when the comparing means outputs the first signal,
First data that is barrel-shifted by the remaining number of bits from the second register and the third register and is loaded into the third register
When the first signal is output from the barrel shift means and the comparison means, the data in the first register is loaded into the second register in bit parallel, and the data in the first register is loaded into the second register by the loading means. rear,
Variable-length bit data processing, including second barrel shift means for loading the data of the second register and the third register barrel-shifted by the bit number of the difference between the effective bit number and the remaining bit number into the second register and the third register Circuit.

The present invention also provides a 1-word first register for holding data provided in bit parallel, and a 1-word second register for receiving data from the first register in bit parallel.
1 from which registers and variable-length bit data are fetched
A processing method in a variable length bit data processing circuit comprising a third register of a word, wherein when the number of effective bits is larger than the number of remaining bits of the data held in the second register, (a) the second register and the third register The data that is barrel-shifted by the number of remaining bits from is loaded to the third register, (b) the data of the first register is loaded to the second register in bit parallel, and (c) the data of the second and third registers is loaded. This is a processing method of barrel-shifting by the number of bits that is the difference between the number of effective bits and the number of remaining bits and loading it into the second and third registers.

[0007]

For example, one word of data read from the memory is bit-parallel loaded into the first register. The data in the first register is loaded into the second register in bit parallel, and the data in the second register is shifted by, for example, 16 bits by the first barrel shift means and loaded into the third register. Variable length bit data is taken out from the third register. For example, in the comparison means including a subtractor, the effective bit number set by the CPU, for example, is subtracted from the remaining bit number of the data held in the second register. And when the subtraction result becomes negative,
A borrow signal (first signal) is output from the subtractor. When this borrow signal is output, the barrel shifter operates,
The data in the second register and the third register is barrel-shifted by the remaining number of bits and loaded into the third register. At this time, the data protruding by the barrel shift of the first barrel shift means is lost and is not used. At the same time, the data in the first register is loaded into the second register, and the data in the second register is barrel-shifted by the second barrel means by the number of effective bits-the number of remaining bits together with the data in the third register to make the second data. The register and the third register are loaded. "0" is written in the blank portion of the second register which has been vacated by the barrel shift of the second barrel shift means.

[0008]

According to the present invention, a latch of 3 words in total and a plurality of selectors and subtractors for configuring the barrel shift means are sufficient, and the circuit configuration is simpler than that of the prior art. Since the effective data can be set by the barrel shift operation of at most two steps, the processing time is shortened and the data processing is further speeded up.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A variable length bit data processing circuit 10 shown in FIG.
Is a circuit for processing variable-length bit data output from a memory (not shown), and is a 1-word (16-bit) first register for receiving 1-word memory data from the memory in parallel. Including 12. The data in the first register 12 is applied to the selector 14 in bit parallel. The selector 14 selects and outputs any one of the two inputs (16 bits each), and the 16 bits from the above-mentioned first register 12 are given as one input and the upper 16 bits of the barrel shifter 16 are given as the other input. To be The selector 14 selectively selects the data from the first register 12 or the data from the barrel shifter 16 in bit parallel to the second register 20 in response to the select signal of “0” or “1” from the timing generator 18. To load. Therefore, the selector 14 constitutes a part of the first to fourth barrel shift means and also has the first
It functions as a loading unit that loads the data in the register 12 into the second register 20. The second register 20 is a 1-word (16-bit) register, and the data in the second register 20 is applied to the barrel shifter 16 in bit parallel. The third register 22 is also 1 word (16 bits)
Is a register of. Note that, for convenience, the second register 20 and the third register 22 are described as separate ones, but
Actually, it is configured as one register or latch of 2 words (32 bits). The data in the second register 20 is given to the upper 16 bits of the barrel shifter 16, and the data in the third register 22 is given to the lower 16 bits of the barrel shifter 16.
Given to a bit. The barrel shifter 16 barrel-shifts the 16-bit parallel data of the second register 20 and the third register 22 to the right as one 32-bit data. The upper 16 bits of the barrel-shifted data are supplied to the selector 14 as described above, but the lower 16 bits of the barrel-shifted data are supplied to the third register 2
2 in bit parallel. Therefore, it is obvious that the barrel shifter 16 constitutes a part of the first to fourth barrel shifting means. As a result, the data in the third register 22 is fetched from the three-state gate 24 as valid data by the CPU (not shown).

The barrel shift will be described below.
In data shift using a normal shift register, data is shifted by one bit to the right or left in response to a clock applied once. For example, when shifting data by 5 bits, the data is shifted by 5 bits to the right or left in response to 5 clocks. On the contrary,
When barrel shift is used here, data is shifted to the right or left by a plurality of bits at a time in response to one clock. The number of bits to shift in one clock is
It is determined by the shift amount given by the subtractor 30 (described later).

In order to carry out such a barrel shift, the barrel shifter 16 of this embodiment, as shown in FIG.
It can be configured using two selectors SBL0 to SBL31. The barrel shifter 16 has 1 from the third register 22.
A total of 32 bits of 6-bit parallel data b16-b31 and 16-bit parallel data b0-b15 from the second register 20 are provided. Each bit of this 32-bit data is set to b0-b31 from the lower order to the higher order.

On the other hand, as described above, the barrel shifter 1
6 can perform barrel shift of 16 bits at the maximum. This barrel shift is realized by the selectors SBL0 to SBL31. The operation of each of the selectors SBL0-SBL31 will be described below. The selector SBL0 that determines the output of the least significant bit of the barrel shifter 16 is one of bits b1 to b16.
It is a 16-1 selector that selects and outputs a bit (a selector that selects and outputs any one bit from 16 bits), and the selected bit responds to the shift amount given from the subtractor 30 (FIG. 1). Will be decided. Similarly, the selectors SBL1, SBL2, SBL3, ... It is a 16-1 selector that selects and outputs 1 bit.

On the other hand, each of the selectors SBL16-SBL31 cannot be composed of 16-1 selectors like those used for the selectors SBL0-SBL15. Because selector SB
This is because L16 cannot select and output one bit from bits b17-b32. The reason is that only 32 bits b0 to b31 of data are given to the barrel shifter 16, and the bit b32 not given to the barrel shifter 16 cannot be selected. Therefore,
The selector SBL16 outputs "0" instead of the bit b32 when instructed to perform 16-bit barrel shift according to the shift amount given from the subtractor 30. That is, the selector SBL16 has bits b17-b31 or "0".
16-1 selector for selecting and outputting 1 bit from the above. Further, since the selector SBL17 does not provide the bits b32 and b33 to the barrel shifter 16,
If one bit cannot be selected and output from b18-b33, and therefore the subtracter 30 is instructed to perform barrel shift of 15 bits or more, that is,
When instructed to select the bit b32 or b33, "0" is output. In other words, the selector SBL17
Is a 15-1 selector that selects and outputs one bit from bits b18-b31 or "0". Similarly, the selectors SBL18, SBL19, SBL20, ... SBL30 are respectively
Select and output one bit from bit b19-b31 or "0", bit b20-b31 or "0", bit b21-b31 or "0", ... bit b31 or "0" 14-
1 selector, 13-1 selector, 12-1 selector, ...
2-1 selector. The selector SBL31 is a 1-1 selector that outputs only "0" regardless of the value of the shift amount, and the output of the selector SBL31 is fixed to "0".

In this way, the barrel shifter 16 has 32 bits b0-b31 or "0" provided from the second register 20 and the third register 22 according to the shift amount instructed by the subtractor 30 (FIG. 1). Is selected, and as a result, barrel shift is performed by the required number of bits. As a result of the barrel shift, the protruding bits are lost, and "0" is written to the blank bits.

The first register 12 is loaded with memory data from a memory (not shown) in response to a memory data write clock (described later), and the data from the selector 14 is output from the timing generator 18. The second register 20 is loaded according to the latch clock. The 3-state gate 24 is controlled by the CPU read signal output from the address decoder (not shown). That is, when the CPU read signal is "1", 3
CPU read data is fetched from the state gate 24. The above-mentioned address decoder outputs a VBC start signal indicating the start of processing of variable length bit data (VBC: Variable Bit-length Code), and this VBC start signal is supplied to the above-mentioned timing generator 18 and at the same time, is initialized. It is given to the counter 26. The initial counter 26 also receives the memory data write clock and is incremented accordingly. The timing generator 18 is enabled in response to the VBC start signal and generates the VBC request signal. This VB
The C request signal is generated in synchronization with the memory data write clock.

CPU write data from a CPU (not shown) is supplied to the valid bit number register 28 and the timing generator 18. The effective bit number data is given by, for example, 4 bits, and is used to determine the barrel shift amount. When the effective bit number data is "0000", it represents the effective bit number of "16", when the effective bit number data is "0001", it represents the effective bit number of "1", and when the effective bit number data is "0010" It represents the number of effective bits of "2", and similarly, represents the number of effective bits of "15" when the effective bit number data is "1111". In addition, the effective bit number write clock from the address decoder (not shown) is the effective bit number register 2
8 and also to the timing generator 18.

The data of the effective bit number loaded in the effective bit number register 28 is given to one input of the subtractor 30. The other input of the subtractor 30 is supplied with the data of the remaining bit number output from the remaining bit number register 32.
That is, the subtractor 30 calculates "the number of remaining bits-the number of effective bits".
Since the subtraction is performed, the remaining bit number of the second register 20 can be known by itself. Therefore, the remaining bit number data is output from the subtractor 30 and the remaining bit number write clock is supplied from the timing generator 18 to the remaining bit number register 32, so that the remaining bit number data is held in the remaining bit number register 32. . In this way, the subtractor 30 performs the operation of "remaining bit number-effective bit number", outputs the subtraction result as new remaining bit number data, and when the latter is larger than the former,
It outputs a borrow signal of "1" (first signal), and outputs a zero signal of "1" (second signal) when the former and the latter are equal. Therefore, when both the borrow signal and the zero signal are “0”, it means that the third signal is output from the subtractor 30. Both the borrow signal and the zero signal are provided to the timing generator 18. Timing generator 18
Then, the select signal and the latch clock are output according to the borrow signal and the zero signal.

The subtractor 30 sets, in the barrel shifter 16, the number of bits to be barrel-shifted, that is, the shift amount. For example, when the first signal is output, the remaining bit number data is first given as the shift amount, then the "effective bit number-remaining bit number", that is, the absolute value of the subtraction result is given, and the second signal is output. Sometimes the remaining bit number data is given as the shift amount, and when the third signal is output, the effective bit number data is given as the shift amount.

The address counter 34 is preset with the start address data of the variable length bit data stored in the memory in response to the initial address write clock supplied from the address decoder 36 (FIG. 3). The address data preset in the address counter 34 is
It is incremented in response to the memory data write clock given from the arbiter 38. As a result, even if the variable-length bit data is continuously stored in the memory over a plurality of words, it is only necessary to preset the start address of the variable-length bit data once in the address counter 34, and then the variable-length bit data over a plurality of words can be stored. Data can be continuously read and latched in the first register 12.

The address selector 40 switches either the address data of the CPU address bus supplied from the CPU or the address data supplied from the address counter 34 and supplies it to the memory. This switching is based on the select signal from the arbiter 38. Is done. The arbiter 38 is a variable-length bit data processing circuit 10.
Operation and variable length bit data processing circuit 10 and CPU
It controls the timing of memory access by and.

As shown in FIG. 1, the arbiter 38 is supplied with a system clock, a CPU memory request signal from the address decoder 36, a select signal from the timing generator 18, and an initial flag.
The arbiter 38 determines that the select signal from the timing generator 18 is a signal that switches the selector 14 so as to supply the data latched in the first register 12 to the second register 20. In response to this, the arbiter 38 generates a count signal for incrementing the address counter 34, and subsequently generates a memory data write clock for latching the variable length bit data given from the memory in the first register 12. However, when the initial flag from the timing generator 18 indicates the initial state, the count signal is not generated. Further, the arbiter 38 generates a select signal instructing the address selector 40 to supply the address signal from the address counter 34 to the memory before generating the memory data write clock.

On the other hand, the arbiter 38 judges whether or not the CPU requests access to the memory by monitoring the CPU memory request signal from the address decoder 36 (FIG. 3). Then, when the CPU requests access to the memory and the address selector 40 is switched to give the address data from the address counter 34 to the memory, a wait signal is given to the CPU to put the CPU in the wait state. To

Referring to FIG. 3, a CPU address bus, a read signal line, and a write signal line are connected to the address decoder 36, and address data from the CPU, read signals from the CPU, and read signals from the CPU. And a write signal. The CPU has a memory space of a predetermined size, and at the predetermined address in this memory space, the above-mentioned memory, variable length bit data processing start, third register 2
2 and the effective bit number register 28 are assigned. The address decoder 36 always monitors the address data, read signal and write signal from the CPU,
When the CPU accesses the address assigned to the memory and outputs the read signal or the write signal, the CPU memory request signal is generated. Further, the address decoder 36 causes the variable length bit data processing circuit 10 to start the variable length bit data processing when the CPU accesses the address for starting the variable length bit data processing and outputs the write signal. To generate the VBC start signal. Further, the address decoder 36 generates an initial address write clock when the CPU is accessing an address assigned by the address counter and outputting a write signal. Further, the address decoder 36 generates a CPU read signal when the CPU accesses the address assigned to the third register and outputs a read signal. The address decoder 36 is a CPU
When the address is assigned to the valid bit number register 28 and the write signal is output, the valid bit number write clock signal is generated.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. Although the embodiment of FIG. 1 is actually composed of hardware, it operates as shown in the flowcharts of FIGS. 4 and 5. Therefore, the circuit of FIG. 1 may be replaced by a microcomputer that operates according to the flowcharts of FIGS. 4 and 5. Steps S1 to S7 in FIG. 4 are initial setting operations. That is, C
The timing generator 18 in response to the VBC start signal from the PU and thus the address decoder 36 (FIG. 3).
Are enabled, and in step S1, the timing signal generator 18 outputs the VBC request signal.
The address decoder 36 outputs the VBC start signal when the predetermined address data is output from the CPU as described above. At this time, the CPU simultaneously sets the memory read address in the memory address counter 34 (FIG. 1). Accordingly, in step S2, the memory data is read from the memory (not shown), and the memory data is loaded into the first register 12 in bit parallel in response to the memory data write clock. Then, the address counter 34 is incremented according to the memory data write clock. In the memory (not shown), variable bit length data, that is, data in which the number of effective bits changes, is efficiently (without a blank space) stored address-sequentially. The timing generator 18 counts this memory data write clock and again generates the VBC request signal in the next step S3. Therefore, in the next step S4, the memory data from the incremented address of the memory (not shown) is loaded into the first register 12 in bit parallel and the select signal from the timing generator 18 is "1". Therefore, the first register 1
The second data is bit-parallel to the second data via the selector 14.
It is loaded into the register 20. Timing generator 18
Further counts the memory data write clock, and in the next step S5, generates the VBC request signal again. Therefore, in the next step S6, the memory data from the memory (not shown) is loaded into the first register 12 in a bit-parallel manner, and the select signal from the timing generator 18 is "1". The data of the register 12 is loaded into the second register 20 in bit parallel via the selector 14. The initial flag from the timing generator 18 is the subtractor 3
0, and the subtractor 30 outputs "16", that is, "0".
000 ”is provided to barrel shifter 16. The data in the second register 20 is loaded into the third register 22 via the barrel shifter 16. Since the initial counter 26 has counted the three memory data write clocks so far, in the next step S7, the initial end signal is output and given to the timing generator 18. Therefore, the timing generator 18 finishes the initialization operation.

In this way, as shown in FIG. 6, the first
Register 12, second register 20, and third register 2
Data is loaded into each of the two. The third register 22 stores 16-bit data in order from the least significant bit.
a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b _6, c ₀ , c ₁ , c ₂ , c ₃ are loaded , The second register 20 stores 16-bit data c ₄ , c ₅ , c _6, c ₇ , c ₈ , c ₉ , c ₁₀ , in order from the least significant bit.
c ₁₁ , c ₁₂ , c ₁₃ , d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ are loaded, and 16-bit data d ₆ , is stored in the first register 12 in order from the least significant bit. e _0, f ₀ , f ₁ , f ₂ , f ₃ , f ₄ , f ₅ , f ₆ , f ₇ , f ₈ , f ₉ , f ₁₀ , g ₀ , g
Consider the situation where ₁ and g ₂ are loaded. The alphabet a,
, b, c, ... Show different data, the number of effective bits of data a is 5 bits, and the number of effective bits of data b is 7
The effective number of bits of data c is 14 bits, the effective number of bits of data d is 7, the effective number of bits of data e is 1 bit, the effective number of bits of data f is 11 and the effective number of bits of data g is It is undecided.

In the next step S8, the CPU (not shown) reads a ₀ -a ₄ from the third register 22 as valid data. In step S9, "5" which is the effective bit number of the data a is output from the CPU as the CPU write data. In response, the effective bit number write clock is output from the address decoder 36 (FIG. 3), so that the data of "5" is written in the effective bit number register 28.

In the next step S10, the subtractor 30
Executes the calculation of "remaining number of bits-effective number of bits". Here, the number of remaining bits means, among the data held in the second register 20, data other than “0” generated as a result of barrel shift, for example, c ₄ -c ₁₃ and d ₀ -d in FIG.
_It means 16-bit data of ₆ or 11-bit data of c ₉ -c ₁₃ and d ₀ -d ₅ in FIG. 7. In the example of FIG. 6, since the remaining bit number of the second register 20 is “16”, the subtraction result of step S10 is “16−5 = 11”.
Is positive, and it is determined to be “YES” in step S10. At this time, the subtractor 30 instructs the barrel shifter 16 to be "5" which is the number of effective bits as the shift amount in the barrel shifter 16. Therefore, the next step S
In 11, the data barrel-shifted by the effective bit number “5” is loaded into the second register 20 and the third register 22. The result is shown in FIG. 7. In Figure 7,
The data in the first register 12 remains unchanged, and the 5-bit data a held in the third register 22 is changed to the third data.
It is pushed out of the register 22. Therefore, 16-bit data b ₀ , b ₁ , b ₂ , b ₃ , b ₄ ,
_{b 5, b 6, c 0} , c 1, c 2, c 3, c 4, c 5, c 6, c 7, c 8 is maintained. Since both the borrow signal and the zero signal from the subtractor 30 are “0”, the timing generator 18 outputs “0”.
Select signal is output. In response, the selector 14 selects the data from the barrel shifter 16. Therefore, the second register 20 stores 11-bit data c ₉ , c ₁₀ , c
₁₁ bits, c ₁₂ , c ₁₃ , d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ and 5-bit “0” are held. “0” is a result of barrel-shifting the data in the second register 20 by 5 bits by the barrel shifter 16,
It is written in the second register 20.

In the state of FIG. 7, the number of effective bits of the data b in the third register 22 is "7", and the number of remaining bits of the second register 20 is "11". Therefore, steps S8 to S11 are repeatedly executed here. As a result, as shown in FIG. 8, 7-bit data b is discharged from the third register 22, and the data b is fetched as CPU read data. And the third
The register 22 stores 16-bit data c ₀ , c ₁ , c ₂ , c ₃ ,
_{c 4, c 5, c 6} , c 7, c 8, c 9, c 10, c 11, c 12, c 13, d 0, d 1 is held, in the second register 20, 4 bits of data d ₂ , d ₃ ,
d _4, d ₅ and "0" of 12 bits are held. Since there is a 5-bit "0" ahead and a 7-bit barrel shift is newly performed, at this stage, the second register 20
"0" of 12 becomes 12 bits.

In the state of FIG. 8, the effective bit number of the data c in the third register 22 is "14", and the remaining bit number of the second register 20 is "4". Therefore, the subtraction result of the subtractor 30 is "4-14 = -10", the borrow signal is output, and "NO" is determined in step S10. Therefore, the process is step S12 of FIG.
Then, in step S12, "remaining bit number-
It is determined whether or not the result of subtracting the “effective bit number” is “0”. In the above example, the subtraction result is "-10", so "NO" is determined in this step S12, and therefore the process proceeds to step S13.

The timing generator 1 is responsive to the borrow signal.
8 outputs a select signal of "0". Also, the subtractor 3
Since the subtraction result becomes negative from 0, the remaining bit number "4" is given to the barrel shifter 16 as the shift amount. Therefore, in step S13, as shown in FIG. 9, first, the data in the second register 20 and the third register 22 is barrel shifted by 4 bits, and the data is loaded into the second register 20 and the third register 22. At this time,
The lower 16 bits of data of the barrel shifter 16 are c ₄ , c ₅ ,
c ₆ , c ₇ , c ₈ , c ₉ , c ₁₀ , c ₁₁ , c ₁₂ , c ₁₃ , d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ and the upper 16 bits are all "0". "become. Here, next, in response to the select signal of "1" from the timing generator 18, the selector 14 is selecting the data of the first register 12, so the second register 20 has the first register 1
2 data is loaded in bit parallel, and the second register 2
0 is 16-bit data d ₆ , e _0, f ₀ , f ₁ , f ₂ , f ₃ , f ₄ , f ₅ , f ₆ , f
₇ , f ₈ , f ₉ , f ₁₀ , g ₀ , g ₁ , g ₂ are held.

In the next step S14, the subtracter 30
The shift amount of "effective bit number-remaining bit number" is barrel shift.
16 is instructed. In the state of FIG. 8, the third register 2
The number of effective bits of 2 is “14”, and the second register 20
The remaining number of bits is 4. Therefore, at this time
The shift amount is "10". Therefore, step S1
4, the second register 20 and the third register 22
10-bit barrel data by barrel shifter 16
The shifted data is stored in the second register 20 and the third register.
The data is loaded into the data 22 through the selector 14. as a result,
16-bit data d is stored in the third register 22.₀, d₁, d₂, d
₃, d_Four, d_Five, d₆, e_0,f₀, f₁, f₂, f₃, f_Four, f_Five, f₆, f ₇ Is held,
6-bit data f is stored in the second register 20.₈, f₉, f_Ten, g₀, g
₁, g₂And 10-bit "0" are held.

In the next step S15, the VBC request signal is output from the timing generator 18, and in response thereto, the next memory data is read from the memory (not shown). Therefore, in step S16, as shown in FIG. 10, the memory data is loaded into bit-parallel to the first register 12, the first register 12 16-bit data _{g 3, g 4, g 5} , g 6, g _7, h ₀ , h ₁ , h ₂ , h ₃ , h ₄ , h ₅ , h ₆ , h ₇ , h ₈ , h ₉ ,
h ₁₀ is retained.

The timing generator 18 is a memory.
Each time data is loaded from the first register 12 to the memory
Variable to increment the address counter 34
Store a long bit data string in memory in address order
Just put it, each variable length bit data will be automatically
The first register 12 is sequentially loaded from the memory. again
When step S12 is executed, in the state of FIG.
The effective bit number of the data d of the register 22 is "7"
The number of bits is "4", and as a result, from step S13
Step S16 is executed. That is, step S1
3 through 3, as shown in FIG.
16-bit data d₆, e_0,f₀, f₁, f₂, f₃, f_Four, f_Five, f₆, f₇,
f₈, f₉, f_Ten, g₀, g₁, g₂, g₃Is held and the second register 20
16-bit data g₃, g_Four, g_Five, g₆, g_7,h₀, h₁, h₂, h₃,
h_Four, h_Five, h₆, h₇, h₈, h₉, h_TenIs retained. 7 bits at the same time
Data d is captured as CPU read data
You. After steps S15 and S16
As shown in FIG. 10, 16 bits are stored in the third register 22.
Data e_0,f₀, f₁, f₂, f₃, f_Four, f_Five, f₆, f₇, g₀, g₁, g₂But
The second register 20 holds the 15-bit data.
g_Four, g_Five, g₆, g_7,h₀, h₁H before₂, h₃, h_Four, h_Five, h₆, h₇, h₈, h₉, h_Ten When
A 1-bit “0” is held and stored in the first register 12.
Memory data h from memory (not shown)₁₁, h₁₂, h₁₃, h₁₄, h
_Fifteen, i₀, i₁, i₂, i ₃, i_Four, i_Five, i₆, i₇, i₈, i₉, j₀Is loaded
You.

In the state of FIG. 10, the data of the third register 22 is
The effective bit number of data e is "1", and the remaining bit number is
Since it is “15”, in step S10 executed next
It is determined to be "YES" and step S11 is executed again.
Be done. As a result, as shown in FIG. 11, the third register 2
2 has 16-bit data f₀, f₁, f₂, f₃, f_Four, f_Five, f₆, f₇,
g₀, g₁, g₂, g₃, g_FourIs held, and the second register 20 stores 1
4-bit data g_Five, g₆, g _7,h₀, h₁, h₂, h₃, h_Four, h_Five, h₆, h₇,
h₈, h₉, h_TenAnd 2-bit "0" is held.

In the state of FIG. 11, the number of effective bits of the data f in the third register 22 is "11" and the number of remaining bits is "14", so that "YES" is determined in the next step S10. The determination is made, and step S11 is executed again. As a result, as shown in FIG. 12, the third register 2
2 is 16-bit data g ₀ , g ₁ , g ₂ , g ₃ , g ₄ , g ₅ , g ₆ , g
_7, h ₀ , h ₁ , h ₂ , h ₃ , h ₄ , h ₅ , h ₆ , h ₇ are held, and the second register 20 stores 3-bit data h ₈ , h ₉ , h ₁₀ and 13 The bit "0" is retained. At this time, the data of the first register 12 _{h 11, h 12, h 13} , h 14, h 15, i 0, i 1, i 2, i 3, i 4, i 5, i 6, i 7,
It is unchanged at i ₈ , i ₉ and j ₀ .

In the state shown in FIG. 12, the number of effective bits of the data g in the third register 22 is "8" and the number of remaining bits is "3". Therefore, in both step S10 and step S12 to be executed next. , "NO". Therefore, steps S13 to S16 are executed again. The result is shown in FIG. In the state of FIG. 13, the number of effective bits of the data h of the third register 22 is “16”, and the number of remaining bits of the second register 20 is “11”. Therefore, the subtraction result of the subtractor 30 is "11-16 = -5", the borrow signal is output, and it is determined "NO" in step S10. Therefore, in step S12, it is determined whether the subtraction result of "remaining bit number-effective bit number" is "0".
In the above example, the subtraction result is "-5", so "NO" is determined in this step S12, and therefore the process proceeds to step S13.

In response to the borrow signal, the timing generator 1
8 outputs a select signal of "0". Also, the subtractor 3
Since the subtraction result is negative from 0, the remaining bit number "11" is given to the barrel shifter 16 as the shift amount. Therefore, in step S13, as shown in FIG. 14, first, the second register 20 and the third register 2
The data of 2 is barrel shifted by 11 bits and loaded into the second register 20 and the third register 22. At this time, the lower 16-bit data of the barrel shifter 16 is
h ₁₁ ,, h ₁₂ , h ₁₃ , h ₁₄ , h ₁₅ , i ₀ , i ₁ , i ₂ , i ₃ , i ₄ , i ₅ , i ₆ , i ₇ , i ₈ , i ₉ ,
j ₀ , and the upper 16 bits of data are all “0”. Here, since the selector 14 selects the data of the first register 12 in response to the select signal of “1” from the timing generator 18, the data of the first register 12 is stored in the second register 20. The 16-bit data j ₁ , j ₂ , j ₃ , j ₄ ,
_{j 5, j 6, j 7} , j 8, k 0, k 1, k 2, k 3, k 4, k 5, k 6, k 7 is held.

In the next step S14, the subtractor 30
The shift amount of "effective bit number-remaining bit number" is barrel shift.
16 is instructed. In the state of FIG. 14, the third register
The number of effective bits of 22 is “16”, and the second register 2
The number of remaining bits of 0 is “11”. So with this
The shift amount of the mushroom is "5". Therefore, step S
In 14, the second register 20 and the third register 2
5 bit barrel for 2 data by barrel shifter 16
The shifted data is stored in the second register 20 and the third register.
The data is loaded into the data 22 through the selector 14. as a result,
The third register 22 stores 16-bit data i₀, i₁, i₂, i
₃, i_Four, i_Five, i₆, i₇, i₈, i₉, j₀, j₁, j₂, j₃, j_Four, j _FiveIs held,
The second register 20 stores 11-bit data j₆, j₇, j₈, k₀,
k₁, k₂, k₃, k_Four, k_Five, k₆, k₇And 5 bits of "0" are held
You.

At the next step S15, the VBC request signal is output from the timing generator 18, and in response thereto, the next memory data is read from the memory (not shown). Therefore, in step S16, as shown in FIG. 15, memory data is loaded into the first register 12 in bit parallel, and 16-bit data l ₀ , l ₁ , l ₂ , l ₃ , l, l is loaded in the first register 12. ₄ , m ₀ , m ₁ , n ₀ , n ₁ , n ₂ , s ₀ , s ₁ , s ₂ , s ₃ , s ₄ , s
₅ is retained.

In the state of FIG. 14, the third register 22
The number of effective bits of the data i is “10”, and the number of remaining bits of the second register 20 is “11”. Therefore,
The subtraction result of the subtractor 30 is “11-10 = 1”,
In step S10, "YES" is determined. Subtractor 3
From 0, at this time, "10" which is the effective bit number as the shift amount in the barrel shifter 16 is set in the barrel shifter 1.
Instruct 6 Therefore, in the next step S11, the data barrel-shifted by the effective bit number “10” is loaded into the second register 20 and the third register 22. The result is shown in FIG. In FIG. 15, the first
The data in the register 12 remains unchanged, and the 10-bit data i held in the third register 22 is pushed out from the third register 22. Therefore, 16-bit data j ₀ , j ₁ , j ₂ , j ₃ , j ₄ , j ₅ ,
_{j 6, j 7, j 8} , k 0, k 1, k 2, k 3, k 4, k 5, k 6 is maintained. In addition,
Both the borrow signal and the zero signal from the subtractor 30 are "0".
Therefore, the timing generator 18 outputs a select signal of "0". In response, the selector 14 selects the data from the barrel shifter 16. Therefore, the second
The register 20 holds 1-bit data k ₇ and 15-bit “0”. “0” is written in the second register 20 as a result of barrel shifting the data in the second register 20 by the barrel shifter 16 by 10 bits.

In the state of FIG. 15, the third register 22
The number of effective bits of the data j is “9”, and the number of remaining bits of the second register 20 is “1”. Therefore, the subtraction result of the subtractor 30 becomes "1-9 = -8", the borrow signal is output, and it is determined to be "NO" in step S10. Therefore, in step S12, it is determined whether the subtraction result of "remaining bit number-effective bit number" is "0". In the above example, the subtraction result is "-8", so "NO" is determined in this step S12, so the process proceeds to step S13.

In response to the borrow signal, the timing generator 1
8 outputs a select signal of "0". Also, the subtractor 3
From 0, the subtraction result became negative, so
The remaining bit number “1” to the barrel shifter 16.
You. Therefore, in step S13, as shown in FIG.
First, the second register 20 and the third register 22
1-barrel-shift the data of 1st, and transfer it to the 2nd register
Data into the register 20 and the third register 22. This and
The lower 16 bits of data of the barrel shifter 16 are
j₁, j₂, j₃, j_Four, j_Five, j₆, j₇, j_8,k₀, k₁, k₂, k₃, k_Four, k_Five, k₆, k₇When
Therefore, the upper 16 bits are all “0”. Where next
To the select signal of "1" from the timing generator 18.
In response, the selector 14 outputs the data in the first register 12
In order to make a selection, the second register 20 has the first register 12
Data of the second register 20 is loaded in bit parallel.
Is 16-bit data l₀, l₁, l₂, l₃, l_Four, m₀, m₁, n₀, n₁,
n₂, s₀, s₁, s ₂, s₃, s_Four, s_FiveIs retained.

In the next step S14, the subtractor 30 instructs the barrel shifter 16 to shift "the number of effective bits-the number of remaining bits". In the state of FIG. 15, the number of effective bits of the third register 22 is “9”, and the second register 20
The remaining number of bits is 1. Therefore, the shift amount at this time is "8". Therefore, step S14
, The data of the second register 20 and the third register 22 is 8-bit barrel-shifted by the barrel shifter 16, and the data is transferred to the second register 20 and the third register 2.
2 through the selector 14. As a result, the third
The 9-bit data j held in the register 22 is pushed out from the third register 22. Then, as shown in FIG. 16, 16-bit data is stored in the third register 22.
k ₀ , k ₁ , k ₂ , k ₃ , k ₄ , k ₅ , k ₆ , k ₇ , l ₀ , l ₁ , l ₂ , l ₃ , l ₄ , m ₀ , m ₁ , n ₀ , The second register 20 stores 8-bit data n ₁ , n
₂ , s ₀ , s ₁ , s ₂ , s ₃ , s ₄ , s ₅ and 8-bit "0" are held.

In the next step S15, the VBC request signal is output from the timing generator 18, and in response thereto, the next memory data is read from the memory (not shown). Therefore, in step S16, as shown in FIG. 17, the memory data is loaded into the first register 12 in bit parallel, and the first register 12 has 16-bit data s ₆ , s _7, s ₈ , s ₉ , s _10. , s ₁₁ , s ₁₂ , s ₁₃ , t ₀ , t ₁ , u ₀ , u ₁ , u ₂ , u ₃ ,
u ₄ and u ₅ are retained.

When step S12 is executed again, FIG.
In the state of 6, the valid bit of the data k of the third register 22 is
The number of bits is "8" and the number of remaining bits is "8".
Steps S17 to S19 of FIG. 5 are executed.
You. First, in step S17, the timing generator
In response to the select signal of "1" from 18, the selector
Since 14 selects the data of the first register 12,
The data of the first register 12 is stored in the second register 20.
16 bits are loaded in the second register 20 in parallel.
Data s₆, s_7,s₈, s₉, s_Ten, s₁₁, s₁₂, s₁₃, t₀, t ₁, u₀, u₁,
u₂, u₃, u_Four, u_Five Is retained. At the same time, the subtractor 30
To the shift amount corresponding to the number of effective bits is barrel shifter 1
6 is instructed. In the state of FIG. 16, the third register 22
The effective number of bits is "8". Therefore, at this time
The shift amount of is "8". Therefore, step S1
7, the second register 20 and the third register 22
Data of 8 bits by barrel shifter 16
The transferred data to the second register 20 and the third register.
22 through the selector 14. As a result,
The 8-bit data k held in the 3 register 22
It is pushed out from the third register 22. And in FIG.
As shown, the third register 22 contains 16-bit data.
Ta₀, l₁, l₂, l₃, l_Four, m₀, m₁, n₀, n₁, n₂, s₀, s₁, s₂, s₃, s_Four, s_Five 
Is held, and 16-bit data is stored in the second register 20.
s₆, s_7,s₈, s₉, s_Ten, s₁₁, s₁₂, s₁₃, t₀, t₁, u₀, u₁, u₂, u₃, u_Four, u
_Five Is retained.

In the next step S18, the timing generator 18 outputs the VBC request signal, and in response, the next memory data is read from the memory (not shown). Therefore, in step S19, as shown in FIG. 18, memory data is loaded into the first register 12 in bit parallel, and 16-bit data u ₆ , u _7, v ₀ , v ₁ , v is stored in the first register 12. ₂ , v ₃ , v ₄ , w ₀ , w ₁ , w ₂ , w ₃ , w ₄ , w ₅ , w ₆ , w ₇ , x
₀ is retained.

In the state of FIG. 17, the third register 22
The number of effective bits of the data 1 is “5”, and the number of remaining bits of the second register 20 is “16”. Therefore, the subtraction result of the subtractor 30 is "16-5 = 11", and "YES" is determined in step S10. Subtractor 30
From this, at this time, the barrel shifter 16 is instructed to enter "5", which is the number of effective bits, as the shift amount in the barrel shifter 16. Therefore, in the next step S11,
The second data is barrel-shifted by the effective bit number "5".
The register 20 and the third register 22 are loaded. The results are shown in the upper part of FIG. In this state, the data in the first register 12 remains unchanged and the 5-bit data 1 held in the third register 22 is pushed out from the third register 22. Therefore, 16-bit data m ₀ , m ₁ , n ₀ , n ₁ , n ₂ , s ₀ ,
s ₁ , s ₂ , s ₃ , s ₄ , s ₅ , s ₆ , s _7, s ₈ , s ₉ , s ₁₀ are held. Since both the borrow signal and the zero signal from the subtractor 30 are “0”, the timing generator 18 outputs “0”.
Select signal is output. In response, the selector 14 selects the data from the barrel shifter 16. Therefore, the second register 20 stores 11-bit data s ₁₁ , s ₁₂ ,
s ₁₃ , t ₀ , t ₁ , u ₀ , u ₁ , u ₂ , u ₃ , u ₄ , u ₅ and 5-bit “0” are held. “0” is written in the second register 20 as a result of barrel shifting the data in the second register 20 by the barrel shifter 16 by 10 bits.

In the upper state of FIG. 18, the number of effective bits of the data m in the third register 22 is "2", and the second bit
The remaining bit number of the register 20 is “11”. Therefore, the subtraction result of the subtractor 30 is "11-2 = 9", and "YES" is determined in step S10. At this time, the subtractor 30 instructs the barrel shifter 16 to be "2" which is the number of effective bits as the shift amount in the barrel shifter 16. Therefore, in the next step S11, the data barrel-shifted by the effective bit number "2" is loaded into the second register 20 and the third register 22. The result is shown in the lower part of FIG. In the lower part of FIG. 18, the data in the first register 12 does not change, and the 2-bit data m held in the third register 22 is pushed out from the third register 22. Therefore, 16-bit data n ₀ ,
n ₁ , n ₂ , s ₀ , s ₁ , s ₂ , s ₃ , s ₄ , s ₅ , s ₆ , s _7, s ₈ , s ₉ , s ₁₀ , s ₁₁ , s ₁₂ are held. Since both the borrow signal and the zero signal from the subtractor 30 are "0", the timing generator 18
Outputs a select signal of "0". In response, the selector 14 selects the data from the barrel shifter 16. Therefore, the second register 20 holds 9-bit data s ₁₃ , t ₀ , t ₁ , u ₀ , u ₁ , u ₂ , u ₃ , u ₄ , u ₅ and 7-bit “0”. “0” is the second value by the barrel shifter 16.
As a result of barrel-shifting the data in the register 20 by 10 bits, the data is written in the second register 20.

Thus, according to the above embodiment,
The valid data is fetched from the third register 22 only by performing the barrel shift operation up to two times.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a detailed block diagram of the barrel shifter of FIG. 1 embodiment.

FIG. 3 is a block diagram showing an address decoder of FIG. 1 embodiment.

FIG. 4 is a flowchart showing the operation of the embodiment in FIG.

5 is a flowchart showing the operation of the embodiment in FIG. 1. FIG.

FIG. 6 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 7 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 8 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 9 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 10 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 11 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 12 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 13 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 14 is an illustrative view showing a state of each register showing an operation of the embodiment in FIG. 1;

FIG. 15 is an illustrative view showing a state of each register showing an operation of the embodiment in FIG. 1;

FIG. 16 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 17 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

FIG. 18 is an illustrative view showing a state of each register showing the operation of the embodiment in FIG. 1;

[Explanation of symbols]

 10 ... Variable length bit data processing circuit 12 ... First register 14 ... Selector 16 ... Barrel shifter 20 ... Second register 22 ... Third register 30 ... Subtractor

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hideaki Terakawa 3-6 Chuomachi, Kawanishi City, Hyogo Prefecture Creative Design Co., Ltd.

Claims (6)

[Claims] 1. A 1-word first register for holding data applied in bit parallel, 1 for receiving data from the first register in bit parallel
Second register of word, third register of one word from which variable-length bit data is taken out, effective bit number is compared with remaining bit number of data held in the second register, and the effective bit number is the remaining bit A comparing unit that outputs a first signal when the number is larger than a number; and when the first signal is output from the comparing unit, the third register outputs data barrel-shifted by the remaining bit number from the second register and the third register. First barrel shift means for loading into a register; load means for loading data of the first register into the second register in bit parallel when the first signal is output from the comparing means; After loading the data in the first register into the second register, the number of bits is the difference between the number of valid bits and the number of remaining bits. A variable length bit data processing circuit comprising second barrel shift means for loading the barrel-shifted data of the second register and the third register into the second register and the third register. 2. The comparing means outputs a second signal when the effective bit number is equal to the remaining bit number, and when the second signal is output from the comparing means, the barrel is equal to the remaining bit number. When the second signal is output from the third barrel shift means for loading the shifted data in the second register and the third register into the third register, and the comparing means, the data in the first register is transferred to the aforesaid 2. The variable-length bit data processing circuit according to claim 1, further comprising loading means for loading the second register in bit parallel. 3. The comparing means outputs a third signal when the remaining bit number is larger than the effective bit number, and when the comparing means outputs the third signal, the second register and the third register. 3. The variable length bit data processing circuit according to claim 1, further comprising fourth barrel shift means for barrel-shifting register data by the effective number of bits and loading the data in the second register and the third register. 4. A 1-word first register for holding data applied in bit parallel, a 1-word second register for receiving data from the first register in bit-parallel, and 1-word from which variable-length bit data is extracted. In the processing method in the variable-length bit data processing circuit including the third register, when the effective bit number is larger than the remaining bit number of the data held in the second register, (a) the second register and the second register Data barrel-shifted by the remaining number of bits from three registers are loaded into the third register, (b) data of the first register is loaded into the second register in bit parallel, and (c) the second register And barrel-shifting the data in the third register by the number of bits that is the difference between the number of effective bits and the number of remaining bits, and the second register And a processing method of loading the third register. 5. When the number of valid bits is equal to the number of remaining bits, (d) the data of the second register and the third register barrel-shifted by the number of remaining bits is transferred to the second register and the third register. 5. The processing method according to claim 4, wherein the register is loaded, and (e) the data of the first register is loaded in the second register in bit parallel. 6. When the number of remaining bits is larger than the number of valid bits, (f) barrel shift the data in the second register and the third register by the number of valid bits to perform the second register and the third register. Load into a register,
The processing method according to claim 4 or 5.