JPH11191096A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start a series of data processing by mutually cascaded process units in specific timing, SOLUTION: A data memory 11, computing elements 12 to 14, and a data memory 15 which constitute five process units are mutually cascaded so as to constitute one arithmetic pipeline. Similarly, five control for 21 to 25 are mutually cascaded to supply a control signal CONTO requesting the start of a series of data processes to the controller 21 as the 1st stage. Each controller unit once detecting a process start request bit in the given controller signal starts supplying microinstructions to a corresponding process unit and supplies a signal generated by delaying the control signal by cycles needed for the process of the corresponding process unit to a controller as a following stage. Specially, the control unit 21 as the 1st stage is equipped with a loop counter for counting how many times the process is repeated, and automatically generates and supplies a process start request and a process end request to the controller 2 as the following stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus having a plurality of processing elements connected in cascade.

[0002]

2. Description of the Related Art DSPs (digital
In a signal processor (digital signal processing device), various arithmetic processes such as compression encoding / decoding of information, filtering, and error correction are required.

[0003] US Patent No. 5,572,453 discloses a data processing device suitably used for arithmetic processing of image data signals in a television. This is 1
A signal for controlling processing switching is transferred or generated in accordance with the flow of the data signal so that the processing of each processing unit is switched in accordance with the flow of the data signal in the plurality of processing units constituting the arithmetic pipeline. Was to do.

[0004]

The above-mentioned conventional data processing apparatus is suitable for successively processing image data signals. However, it cannot start a predetermined number of repetitions at a predetermined timing. Was. Also, there is no sequence for automatically ending this repetitive processing.

An object of the present invention is to enable a series of data processing by a plurality of processing units connected in cascade to be started at a predetermined timing.

[0006]

In order to achieve the above object, the present invention provides a method in which the processing of each processing unit starts sequentially according to the flow of data signals in a plurality of processing units constituting one arithmetic pipeline. Then, a control signal requesting the start of a series of data processing is transferred according to the flow of the data signal. That is, according to the present invention, each of the plurality of processing elements connected in cascade comprises a processing unit for data processing and a controller for controlling the operation of the processing unit. Then, a control signal requesting the start of a series of data processing is supplied to the first-stage controller.

Each processing unit processes a given data signal in accordance with a microinstruction, and supplies a data signal representing the result of the processing to the next processing unit. Each controller starts supplying a microinstruction to a corresponding processing unit when detecting a processing start request bit in a given control signal, and controls the control signal by the number of cycles required for processing of the corresponding processing unit. Is supplied to the next-stage controller.

The first stage controller has a loop counter for counting the number of repetitions of the process, automatically generates a process start request bit and a process end request bit, and supplies these to the next stage controller.

[0009]

FIG. 1 shows a configuration example of a data processing apparatus according to the present invention. In FIG. 1, 1 is a data bus, 2 is an external memory, 3 is a DMA controller, 4 is a control unit, 5 is an instruction memory, 6 is an instruction bus, 11 is a data memory, 12, 13 and 14 are arithmetic units,
5 is a data memory, 21, 22, 23, 24 and 25 are controllers. The control unit 4 is a CPU (central processing) that controls the entire data processing apparatus of FIG.
unit: central processing unit). The data signal representing the operand to be operated stored in the external memory 2 is supplied from the external memory 2 to the data memory 11 via the data bus 1 under the control of the DMA controller 3 instructed by the control unit 4. You. The instruction memory 5 supplies an instruction INST to each of the controllers 21 to 25 in advance via the instruction bus 6 according to an instruction from the control unit 4. When the given instruction INST is an instruction including an address assigned to the controller, each of the controllers 21 to 25 holds a micro instruction included in the instruction INST. . The data memory 11, the computing units 12, 13, 14 and the data memory 15 constituting the five processing units are cascaded with each other so as to constitute a first path returning from the data bus 1 and returning to the same data bus 1. I have. These five processing units 11 to 15 constitute one arithmetic pipeline for processing, for example, image data signals and audio data signals. Five controllers 21 to
Numerals 25 are cascade-connected to each other so as to form a second path returning from the control unit 4 and returning to the control unit 4, and 1 for controlling the five processing units 11 to 15.
Constitutes a control pipeline of books.

More specifically, the data memory 11
And the controller 21 constitute a first-stage processing element having a first input arranged on the first path and a second input arranged on the second path. The data memory 11 stores a data signal supplied from the data bus 1 via the first input, and supplies a data signal specified by a microinstruction (for example, a LOAD instruction) MI1 to the arithmetic unit 12. The controller 21 starts supplying the microinstruction MI1 to the data memory 11 when detecting the processing start request bit in the control signal CONT0 supplied from the control unit 4 via the second input, and A control signal CONT1 obtained by delaying the control signal CONT0 by the number of cycles required for the processing of step 11 is supplied to the controller 22.

The arithmetic unit 12 and the controller 22 constitute a second stage processing element having a first input arranged on a first path and a second input arranged on a second path. . The arithmetic unit 12 processes the data signal supplied from the data memory 11 via the first input according to the micro instruction MI2,
A data signal representing the result of the processing is supplied to the arithmetic unit 13. The arithmetic unit 12 outputs a flag signal F indicating the occurrence of an exception.
It also has a function of supplying LAG2 to the controller 23.
The controller 22 starts supplying the microinstruction MI2 to the arithmetic unit 12 when detecting the processing start request bit in the control signal CONT1 supplied from the controller 21 via the second input, and A control signal CONT2 obtained by delaying the control signal CONT1 by the number of cycles required for the processing of step 12.
Is supplied to the controller 23.

The arithmetic unit 13 and the controller 23 constitute a third stage processing element having a first input arranged on the first path and a second input arranged on the second path. . The arithmetic unit 13 processes the data signal supplied from the arithmetic unit 12 via the first input according to the microinstruction MI3, and supplies a data signal representing the result of the processing to the arithmetic unit 14. The arithmetic unit 13 outputs a flag signal FLAG indicating that an exception has occurred.
3 is also provided to the controller 24. The controller 23 starts supplying the microinstruction MI3 to the computing unit 13 when detecting the processing start request bit in the control signal CONT2 supplied from the controller 22 via the second input, and A control signal CONT3 obtained by delaying the control signal CONT2 by the number of cycles required for the processing of step 13 is supplied to the controller 24. Further, the controller 23 outputs the flag signal FL.
It also has a function of changing the microinstruction MI3 when AG2 is asserted.

The arithmetic unit 14 and the controller 24 constitute a fourth stage processing element having a first input arranged on a first path and a second input arranged on a second path. . The arithmetic unit 14 processes the data signal supplied from the arithmetic unit 13 via the first input in accordance with the microinstruction MI4, and supplies a data signal representing a result of the processing to the data memory 15. The controller 24 starts supplying the microinstruction MI4 to the arithmetic unit 14 when detecting the processing start request bit in the control signal CONT3 supplied from the controller 23 via the second input, and The control signal CON obtained by delaying the control signal CONT3 by the number of cycles required for the processing of step 14.
T4 is supplied to the controller 25. Further, the controller 24 has a function of changing the microinstruction MI4 when the flag signal FLAG3 is asserted.

The data memory 15 and the controller 25 are
It constitutes a fifth stage processing element having a first input arranged on the path and a second input arranged on the second path.
The data memory 15 converts the data signal supplied from the arithmetic unit 14 via the first input into a micro instruction (for example, STOR).
E instruction) Stored according to MI5. The data memory 15 also has a function of supplying the stored data signal to the data bus 1. The controller 25 is the second from the controller 24.
When a processing start request bit in the control signal CONT4 supplied via the input is detected, the supply of the microinstruction MI5 to the data memory 15 is started, and the control signal CONT4 is supplied for the number of cycles required for processing of the data memory 15.
Is supplied to the control unit 4.

FIG. 2 shows a field configuration of an instruction INST supplied from the instruction memory 5 in FIG. The instruction INST includes the first to sixth fields 31, 32, 3
3, 34, 35, and 36. The first field 31 is a field indicating an address ADRS (any one of addresses 1 to 5) for specifying any one of the five controllers 21 to 25. Controllers 22, 23 and 24 each include six microinstruction registers, as described below. Thus, the second field 32 contains an index INDEX (any of # 0 to # 5) that specifies any of the six microinstruction registers in the controller specified by address ADRS. Show. The third field 33 is 5
ADRS among the processing units 11 to 15
Is a field indicating the number of cycles CYCLE required for processing of the processing unit corresponding to the controller designated by. The data processing apparatus shown in FIG. 1 can automatically and repeatedly execute a series of processes a predetermined number of times as described later. Therefore, the fourth field 34 indicates the pipeline pitch PITCH indicating the maximum value of the number of cycles required for the processing of the five processing units 11 to 15, and the fifth field 34 indicates the fifth field.
Field 35 indicates the number of repetitions REPEAT of a series of processes in the five processing units 11 to 15. The sixth field 36 is a field indicating one microinstruction MINST.

FIG. 3 shows six control signals CONT in FIG.
The field configuration of 0 to CONT5 is shown. In FIG. 3, a first field 41 includes a processing start request bit S
TART, and the second field 42 has a mode bit MODE indicating mode A or mode B (M in mode A).
ODE = 0, MODE = 1 in mode B), and the third
Is a processing end request bit END.
The six microinstruction registers of each of the controllers 22, 23 and 24 form a first group 3 as described below.
Microinstruction registers (# 0 to # 2) and the other three microinstruction registers (# 3
To # 5). In mode A, three microinstruction registers (# 0 to # 2) are selected, and in mode B, the other three microinstruction registers (# 3 to # 5) are selected.

FIG. 4 shows a detailed configuration of the controller 21 at the first stage in FIG. The controller 21 includes an instruction supply unit 100, a control signal transfer unit 120, a microprogram counter 130, and a loop counter 140.

The instruction supply unit 100 includes an instruction memory 5
An instruction decoder 101 for decoding the instruction INST supplied from the controller 21 and a controller address register 102 for storing the address ADRS1 assigned to the controller 21. The instruction decoder 101 receives the address ADRS specified in the instruction INST and the address ADRS stored in the controller address register 102.
When 1 matches, the third to sixth fields 33 to 36 in the instruction INST are accepted. The instruction supply unit 100 includes a cycle number register 103 for storing the cycle number CYCLE1 obtained from the instruction decoder 101, a micro instruction register 104 for storing the microinstruction MINST1 obtained from the instruction decoder 101, and a NOP ( no operation) A NOP generator 110 for generating an instruction, and a NOP instruction generated by the NOP generator 110 or a microinstruction MINST1 stored in the microinstruction register 104 are stored in the data memory 1
A multiplexer 114 for selectively feeding to 1;
Pipeline pitch P obtained from instruction decoder 101
A pipeline pitch register 115 for storing ITCH, and the number of repetitions R obtained from the instruction decoder 101
It further includes a repetition number register 116 for storing EPEAT.

The control signal transfer unit 120 includes a control decoder 121, a code generator 122, and a delay circuit 1
23. The control decoder 121 decodes the control signal CONT0 supplied from the control unit 4 so as to detect the processing start request bit START. Mode bit MODE in control signal CONT0
From the control decoder 121 to the code generator 12
2. The code generator 122 receives the processing start request ST received from the microprogram counter 130.
ART / RESTART, the mode bit MODE received from the control decoder 121, and the loop counter 14
A new control signal code is generated based on the processing end request END received from 0. More specifically, the processing start request bit START is asserted each time a processing start request is received from the microprogram counter 130, and the processing end request bit END is asserted when a processing end request is received from the loop counter 140. The delay circuit 123 receives the clock signal CLK
, The control signal CONT1 obtained by delaying the control signal generated by the code generator 122 by the cycle number CYCLE1 stored in the cycle number register 103 is supplied to the controller 22.

The micro program counter 130 is a counter 1 for counting pulses of the clock signal CLK.
31, a comparator 132 for comparing the count value of the counter 131 with the cycle number CYCLE1 stored in the cycle number register 103, and the count value of the counter 131 and the pipeline pitch stored in the pipeline pitch register 115. It comprises a comparator 133 for comparing PITCH and one OR gate 134. The loop counter 140 is supplied with a pulse (a pulse of the processing start request START / RESTART) each time the count value of the counter 131 is reset to zero.
Counter 141 for counting the
And a comparator 142 for comparing the count value of with the number of repetitions REPEAT stored in the number-of-repetitions register 116. The counter 131 is the OR gate 13
4 is reset by the output. That is, the counter 1
31 indicates that the control decoder 121 has the processing start request bit ST
When the ART is detected, or when the comparator 133 detects the counter 1
31 count value and pipeline pitch register 115
Is reset when a match with the pipeline pitch PITCH stored in is detected. And the counter 13
Every time 1 is reset, the processing start request START / RESTAR is sent to the code generator 122 and the counter 141.
T is given. The selection of the microinstruction in the multiplexer 114 is controlled according to a signal SEL1 representing the result of the comparison by the comparator 132. The counter 141
It is reset when the control decoder 121 detects the processing start request bit START. When the comparator 142 detects a match between the count value of the counter 141 and the number of repetitions REPEAT stored in the repetition number register 116, a processing end request END is given to the code generator 122, and updating of the counter 131 is prohibited. Thus, the hold terminal of the counter 131 is activated.

FIG. 5 shows a detailed configuration of the second-stage controller 22 in FIG. The controller 22 includes an instruction supply unit 200, a control signal transfer unit 220, and a microprogram counter 230.

The instruction supply unit 200 includes the instruction memory 5
Decoder 201 for decoding the instruction INST supplied from the controller 22, a controller address register 202 for storing the address ADRS2 assigned to the controller 22, and a microinstruction obtained from the instruction decoder 201, respectively. And six microinstruction registers (# 0 to # 5) 204 to 209. When the address ADRS specified in the instruction INST and the address ADRS2 stored in the controller address register 202 match, the instruction decoder 201
Second, third and sixth fields 32,3 in NST
Accept 3,36. Also, the instruction decoder 201
It also has a function of storing the microinstruction obtained from the instruction INST in the microinstruction register specified by the index INDEX in the instruction INST among the six microinstruction registers (# 0 to # 5) 204 to 209.
Three microinstruction registers (# 0 to # 2) 204, 2
05 and 206 store the first group to be selected in mode A in the other three micro instruction registers (# 3 to # 5) 2
07, 208 and 209 are the second to be selected in mode B.
Configure each group. Instruction supply unit 200
Is the number of cycles CYC obtained from the instruction decoder 201
A cycle number register 203 for storing LE2;
A NOP generator 210 for generating a NOP instruction; and a micro instruction register (# 0) 20 belonging to a first group.
A multiplexer 211 for selecting the microinstruction stored in the microinstruction 4 or the microinstruction belonging to the microinstruction register (# 3) 207 belonging to the second group according to the mode bit MODE, Multiplexer 21 for selecting a microinstruction stored in (# 1) 205 or a microinstruction stored in microinstruction register (# 4) 208 belonging to the second group according to mode bit MODE
2 and micro instruction registers (#
2) a multiplexer 213 for selecting the microinstruction stored in 206 or the microinstruction stored in the microinstruction register (# 5) 209 belonging to the second group according to the mode bit MODE, and the NOP generator 21
NOP instruction generated by 0 or multiplexer 21
And a multiplexer 214 for selectively supplying one of the micro-instructions selected by each of the micro instructions 1, 2, 213 to the arithmetic unit 12.

The control signal transfer unit 220 includes a control decoder 221 and a delay circuit 223. The control decoder 221 outputs the processing start request bit STA
RT, mode bit MODE and processing end request bit E
The control signal CONT1 supplied from the controller 21 is decoded so as to detect ND. Delay circuit 223
Receives the control signal CONT1 supplied from the controller 21 based on the clock signal CLK.
The control signal CONT <b> 2 delayed by the cycle number CYCLE <b> 2 stored in 3 is supplied to the controller 23. The mode bit MOD detected by the control decoder 221
E is supplied to each of the multiplexers 211, 212, and 213.

The microprogram counter 230 is a counter 2 for counting pulses of the clock signal CLK.
31 and a comparator 232 for comparing the count value of the counter 231 with the cycle number CYCLE2 stored in the cycle number register 203. The counter 231 is reset each time the control decoder 221 detects the processing start request bit START. The selection of the microinstruction in the multiplexer 214 is controlled according to a signal SEL2 representing the result of the comparison by the comparator 232. The control decoder 221 sets the processing end request bit E
When ND is detected, the hold terminal of the counter 231 is activated so that updating of the counter 231 is prohibited.

FIG. 6 shows a detailed configuration of the controller 23 at the third stage in FIG. The controller 23 includes an instruction supply unit 300, a control signal transfer unit 320, and a microprogram counter 330.

The instruction supply unit 300 includes an instruction memory 5
Decoder 301 for decoding the instruction INST supplied from the controller 23, a controller address register 302 for storing the address ADRS3 assigned to the controller 23, and a microinstruction obtained from the instruction decoder 301, respectively. And six microinstruction registers (# 0 to # 5) 304 to 309. When the address ADRS specified in the instruction INST matches the address ADRS3 stored in the controller address register 302, the instruction decoder 301
Second, third and sixth fields 32,3 in NST
Accept 3,36. Also, the instruction decoder 301
It also has a function of storing the microinstruction obtained from the instruction INST in the microinstruction register specified by the index INDEX in the instruction INST among the six microinstruction registers (# 0 to # 5) 304 to 309.
Three microinstruction registers (# 0 to # 2) 304, 3
Reference numerals 05 and 306 denote the first group to be selected in mode A, and the other three micro instruction registers (# 3 to # 5) 3
07, 308, 309 are the second to be selected in mode B
Configure each group. Instruction supply unit 300
Is the number of cycles CYC obtained from the instruction decoder 301
A cycle number register 303 for storing LE3;
A NOP generator 310 for generating a NOP instruction; and a micro instruction register (# 0) 30 belonging to a first group.
A multiplexer 311 for selecting the microinstruction stored in the microinstruction register (# 3) 307 belonging to the second group or the microinstruction register (# 1) 30 belonging to the first group.
A multiplexer 312 for selecting the microinstruction stored in the microinstruction 5 or the microinstruction register (# 4) 308 belonging to the second group, and the microinstruction register (# 2) 30 belonging to the first group
A multiplexer 313 for selecting the microinstruction stored in the microinstruction (# 5) 309 belonging to the second group or the microinstruction belonging to the second group;
A multiplexer 314 for selectively supplying the NOP instruction generated by the OP generator 310 or one of the microinstructions selected by each of the multiplexers 311, 312, 313 to the arithmetic unit 13; The mode bit M in the supplied control signal CONT2
ODE and the flag signal FLAG supplied from the arithmetic unit 12
And an OR gate 317 for controlling the selection of the microinstruction in the multiplexers 311, 312, 313 in accordance with 2.

The control signal transfer unit 320 includes a control decoder 321 and a delay circuit 323. The control decoder 321 outputs the processing start request bit STA
RT, mode bit MODE and processing end request bit E
The control signal CONT2 supplied from the controller 22 is decoded so as to detect ND. Delay circuit 323
Changes the control signal CONT2 supplied from the controller 22 based on the clock signal CLK into the cycle number register 30.
The control signal CONT3 delayed by the number of cycles CYCLE3 stored in the control signal CONT3 is supplied to the controller 24. The mode bit MOD detected by the control decoder 321
E is supplied to the OR gate 317.

The microprogram counter 330 is a counter 3 for counting pulses of the clock signal CLK.
31 and a comparator 332 for comparing the count value of the counter 331 with the cycle number CYCLE3 stored in the cycle number register 303. The counter 331 is reset each time the control decoder 321 detects the processing start request bit START. The selection of the microinstruction in the multiplexer 314 is controlled according to a signal SEL3 representing the result of the comparison by the comparator 332. The control decoder 321 sets the processing end request bit E
When ND is detected, the hold terminal of the counter 331 is activated so that updating of the counter 331 is prohibited.

FIG. 7 shows a detailed configuration of the controller 24 at the fourth stage in FIG. The controller 24 includes an instruction supply unit 400, a control signal transfer unit 420, and a microprogram counter 430.

The instruction supply unit 400 includes an instruction memory 5
Decoder 401 for decoding the instruction INST supplied from the controller 24, a controller address register 402 for storing the address ADRS4 assigned to the controller 24, and a microinstruction obtained from the instruction decoder 401. And six microinstruction registers (# 0 to # 5) 404 to 409 for performing the operations. When the address ADRS specified in the instruction INST matches the address ADRS4 stored in the controller address register 402, the instruction decoder 401
Second, third and sixth fields 32,3 in NST
Accept 3,36. Also, the instruction decoder 401
It also has a function of storing the microinstruction obtained from the instruction INST in the microinstruction register specified by the index INDEX in the instruction INST among the six microinstruction registers (# 0 to # 5) 404 to 409.
Three microinstruction registers (# 0 to # 2) 404, 4
Reference numerals 05 and 406 denote the first group to be selected in mode A, and the other three micro instruction registers (# 3 to # 5) 4
07, 408 and 409 are the second to be selected in mode B.
Configure each group. Instruction supply unit 400
Is the number of cycles CYC obtained from the instruction decoder 401
A cycle number register 403 for storing LE4;
A NOP generator 410 for generating a NOP instruction; and a micro instruction register (# 0) 40 belonging to a first group.
A multiplexer 411 for selecting a microinstruction stored in the microinstruction register (# 3) 407 belonging to the second group or a microinstruction register (# 1) 40 belonging to the first group.
A multiplexer 412 for selecting the microinstruction stored in the microinstruction 5 or the microinstruction register (# 4) 408 belonging to the second group, and the microinstruction register (# 2) 40 belonging to the first group
A multiplexer 413 for selecting the microinstruction stored in the microinstruction (# 5) 409 belonging to the second group or the microinstruction stored in the microinstruction register (# 5) 409 belonging to the second group;
A multiplexer 414 for selectively supplying one of the NOP instruction generated by the OP generator 410 or the microinstruction selected by each of the multiplexers 411, 412, and 413 to the arithmetic unit 14; The mode bit M in the supplied control signal CONT3
ODE and the flag signal FLAG supplied from the arithmetic unit 13
And an OR gate 417 for controlling the selection of the microinstruction in the multiplexers 411, 412, and 413 in accordance with (3).

The control signal transfer unit 420 includes a control decoder 421 and a delay circuit 423. The control decoder 421 outputs the processing start request bit STA
RT, mode bit MODE and processing end request bit E
The control signal CONT3 supplied from the controller 23 is decoded so as to detect ND. Delay circuit 423
Transmits the control signal CONT3 supplied from the controller 23 based on the clock signal CLK to the cycle number register 40.
The control signal CONT4 delayed by the number of cycles CYCLE4 stored in 3 is supplied to the controller 25. The mode bit MOD detected by the control decoder 421
E is supplied to the OR gate 417.

The microprogram counter 430 is a counter 4 for counting pulses of the clock signal CLK.
31 and a comparator 432 for comparing the count value of the counter 431 with the cycle number CYCLE4 stored in the cycle number register 403. The counter 431 is reset each time the control decoder 421 detects the processing start request bit START. The selection of the microinstruction in the multiplexer 414 is controlled according to a signal SEL4 indicating the result of the comparison by the comparator 432. The control decoder 421 sets the processing end request bit E
When ND is detected, the hold terminal of the counter 431 is activated so that updating of the counter 431 is prohibited.

FIG. 8 shows the detailed configuration of the controller 25 at the fifth stage in FIG. The controller 25 includes an instruction supply unit 500, a control signal transfer unit 520, and a microprogram counter 530.

The instruction supply unit 500 includes an instruction memory 5
An instruction decoder 501 for decoding the instruction INST supplied from the controller 25 and a controller address register 502 for storing an address ADRS5 assigned to the controller 25. The instruction decoder 501 receives the address ADRS specified in the instruction INST and the address ADRS stored in the controller address register 502.
When 5 matches, the third and sixth fields 33 and 36 in the instruction INST are accepted. The instruction supply unit 500 includes a cycle number register 503 for storing the cycle number CYCLE5 obtained from the instruction decoder 501, a micro instruction register 504 for storing the microinstruction MINST5 obtained from the instruction decoder 501, and a NOP instruction. Generator 510 for generating the NOP, and NOP generated by NOP generator 510
A multiplexer 514 for selectively supplying the instruction or the microinstruction MINST5 stored in the microinstruction register 504 to the data memory 15;

The control signal transfer unit 520 includes a control decoder 521 and a delay circuit 523. The control decoder 521 outputs the processing start request bit STA
To detect the RT and the processing end request bit END,
The control signal CONT4 supplied from the controller 24 is decoded. The delay circuit 523 controls the control signal CONT supplied from the controller 24 based on the clock signal CLK.
4 is supplied to the control unit 4 by delaying the control signal CONT5 by the cycle number CYCLE5 stored in the cycle number register 503.

The microprogram counter 530 is a counter 5 for counting pulses of the clock signal CLK.
31 and a comparator 532 for comparing the count value of the counter 531 with the cycle number CYCLE5 stored in the cycle number register 503. The counter 531 is reset each time the control decoder 521 detects the processing start request bit START. The selection of the microinstruction in the multiplexer 514 is controlled according to a signal SEL5 representing the result of the comparison by the comparator 532. The control decoder 521 sets the processing end request bit E
When ND is detected, the hold terminal of the counter 531 is activated so that updating of the counter 531 is prohibited.

FIG. 9 shows an operation example of the data processing device of FIG. Here, the arithmetic units 12, 13 and 14 operate as an adder, a right shifter and a multiplier, respectively, a constant E is added to the data variable X read from the data memory 11, and the result Y of the addition is 2 bits. , And a data variable W representing the result of the multiplication of the shift result Z and the constant F is written to the data memory 15. In the example of FIG. 9, these series of processes are repeated twice. Data memory 11,
The number of cycles required for each processing of the arithmetic unit 12, the arithmetic unit 13, the arithmetic unit 14, and the data memory 15 is 1,
2, 1, 3, and 1. The maximum value of these cycle numbers, that is, the pipeline pitch, is 3. Note that T1 to T16 in FIG.
One machine cycle corresponding to the frequency of LK is shown.

Prior to the start of the data processing, the control unit 4 causes the instruction memory 5 to repeatedly supply the instruction INST to the five instruction supply units 100 and 20.
Initialization of registers 0, 300, 400, and 500 is performed. Instruction supply unit 1 for data memory 11
In 00, the cycle number register 103 stores a numerical value “1”,
The microinstruction register 104 stores a LOAD instruction, the pipeline pitch register 115 stores a numerical value “3”, and the repetition count register 116 stores a numerical value “2”. In the instruction supply unit 200 for the arithmetic unit 12, the cycle number register 203 stores the numerical value “2”, the micro instruction register (# 0) 204 stores the DATA word representing the constant E, and the micro instruction register (# 1) 205 stores the ADD. Stores each instruction. Instruction supply unit 3 for arithmetic unit 13
In 00, the cycle number register 303 stores a numerical value “1”,
The micro instruction register (# 0) 304 stores the SHIFT instruction. In the instruction supply unit 400 for the arithmetic unit 14, the cycle number register 403 stores a numerical value “3”, the microinstruction register (# 0) 404 stores a DATA word representing a constant F, and the microinstruction register (#
1) 405 stores a MUL1 (first half multiplication) instruction, and micro instruction register (# 2) 406 stores a MUL2 (second half multiplication) instruction. In the instruction supply unit 500 for the data memory 15, the cycle number register 503 stores a numerical value “1” and the micro instruction register 504 stores a STORE.
Stores each instruction.

After the initial setting of the registers as described above, the control unit 4 transfers the data from the external memory 2 to the data memory 11.
The DMA controller 3 is instructed to transfer the data variables X (1) and X (2), and the asserted processing start request bit START and the mode A are set in the cycle T1 as shown in FIG. The control signal CONT0 including the designated mode bit MODE and the negated processing end request bit END is supplied to the first-stage controller 21.

In the controller 21 of the first stage, in the cycle T1, the control decoder 121 detects the asserted processing start request bit START in the control signal CONT0, and as a result, the count values of the two counters 131 and 141 are reduced. Both are reset to “0”. At this time, the counter 131 sends a processing start request STAR to the code generator 122.
As a result of the supply of the T / RESTART pulse, the code generator 122 generates a new control signal having the same content as the control signal CONTO. The delay circuit 123 outputs the processing start request bit S asserted by the code generator 122.
The control signal CONT1 in which the control signal including TART is delayed by one cycle according to the value of the cycle number CYCLE1 "1" stored in the cycle number register 103 is supplied to the second-stage controller 22 in the cycle T2. On the other hand, the count value of the counter 131 is updated to “1” at the start of the cycle T2 and to “2” at the start of the cycle T3. The comparator 132 sets the count value of the counter 131 to “1” according to the value “1” of the cycle number CYCLE1 stored in the cycle number register 103.
, The multiplexer 114 selects a LOAD instruction, and if the count value of the counter 131 is a value other than “1”, the NOP instruction. Therefore, the microinstruction MI1 supplied to the data memory 11 from the controller 21 in the cycles T1, T2 and T3
Are a NOP instruction, a LOAD instruction, and a NOP instruction, respectively. However, the illustration of the NOP instruction is omitted in FIG. Data memory 11 that has been supplied with a LOAD instruction
Supplies the data variable X (1) to the computing unit 12.

When the count value of the counter 131 is updated to "3" at the start of the cycle T4, the comparator 133 outputs the count value of the counter 131 and the value "3" of the pipeline pitch PITCH stored in the pipeline pitch register 115. Is detected, the count value of the counter 131 is immediately reset to “0”. Therefore, in the cycle T4, the counter 131 sends the processing start request STA to the code generator 122 and the counter 141.
As a result of the RT / RESTART pulse being supplied, a new control signal is generated by the code generator 122 and the count value of the counter 141 is updated to “1”. The delay circuit 123 controls the control signal CONT1 by delaying the control signal including the processing start request bit START asserted by the code generator 122 by one cycle.
Is supplied to the second-stage controller 22 in the cycle T5. On the other hand, the count value of the counter 131 is equal to the cycle T
The value is updated to "1" at the start of cycle 5, and to "2" at the start of cycle T6. Therefore, the cycle T
The microinstructions MI1 supplied from the controller 21 to the data memory 11 in T4, T5 and T6 are NO
P instruction, LOAD instruction and NOP instruction. LOAD
The data memory 11 having received the instruction supplies the next data variable X (2) to the arithmetic unit 12.

When the count value of the counter 131 is updated to "3" at the start of the cycle T7, the count value is immediately reset to "0" by the output of the comparator 133. Therefore, in cycle T7, the counter 13
Processing start request START / RE from 1 to counter 141
As a result of the START pulse being supplied, the counter 141
Is updated to “2”. When the count value of the counter 141 is updated to “2” in this manner, the comparator 142 detects a match between the count value of the counter 141 and the value “2” of the repetition number REPEAT stored in the repetition number register 116. As a result, the processing end request END is immediately asserted. In cycle T7, the processing end request END is sent from the comparator 142 to the code generator 12
2 and the counter 131, a new control signal is generated by the code generator 122, and the count value of the counter 131 is held at "0".
The delay circuit 123 supplies the control signal CONT1 obtained by delaying the control signal including the processing end request bit END asserted by the code generator 122 by one cycle to the second-stage controller 22 in cycle T8.

As described above, in each of the cycles T2 and T5, the LOAD instruction is
1 is supplied. In the cycles T2 and T5, the asserted processing start request bit START is supplied from the first stage controller 21 to the second stage controller 22, and the asserted processing end request bit END is supplied in the cycle T8. .

In the controller 22 at the second stage, in the cycle T2, the control decoder 221 detects the asserted processing start request bit START in the control signal CONT1, and as a result, the count value of the counter 231 is reset to "0". Is done. The delay circuit 223 delays the control signal CONT1 including the processing start request bit START by two cycles according to the value “2” of the cycle number CYCLE2 stored in the cycle number register 203.
NT2 is supplied to the third-stage controller 23 in cycle T4. On the other hand, the multiplexers 211, 212, 21
3 receives the mode bit MODE specifying the mode A from the control decoder 221, so that the micro instruction registers (# 0 to # 2) 204 to 206 belonging to the first group
Is supplied to the multiplexer 214. The count value of the counter 231 is equal to the cycle T3.
Is updated to "1" at the start of the cycle, and to "2" at the start of the cycle T4. The comparator 232 outputs the cycle number CYCLE stored in the cycle number register 203.
When the count value of the counter 231 is “1” according to the value “2” of the micro instruction register (# 0) 2
04, a DATA word representing the constant E of the counter 231
When the count value of the counter 231 is “2”, the ADD instruction of the microinstruction register (# 1) 205 is given. When the count value of the counter 231 is a value other than “1” and “2”, the NOP instruction is given. The multiplexer 214 is selected. Therefore, the microinstruction M supplied from the controller 22 to the arithmetic unit 12 in the cycles T2, T3 and T4
I2 is the NOP instruction, DATA word and AD
This is a D instruction. The arithmetic unit 12 that has received the DATA word and the ADD instruction supplies the arithmetic unit 13 with the data variable Y (1) representing the result of the addition X (1) + E.

Immediately after the count value of the counter 231 is updated to “3” at the start of the cycle T5, the control decoder 221 detects the asserted processing start request bit START in the control signal CONT1, and as a result, the counter 2
The count value of 31 is reset to “0”. The delay circuit 223 delays the control signal CONT1 including the processing start request bit START by two cycles in accordance with the value “2” of the cycle number CYCLE2 stored in the cycle number register 203, and outputs the control signal CONT2 in the cycle T.
At 7, it is supplied to the controller 23 of the third stage. On the other hand, the count value of the counter 231 is updated to “1” at the start of the cycle T6 and to “2” at the start of the cycle T7. Therefore, the cycles T5, T6 and T7
, The microinstruction MI2 supplied from the controller 22 to the arithmetic unit 12 is a NOP instruction, a DATA word, and an ADD instruction, respectively. The arithmetic unit 12 having received the DATA word and the ADD instruction supplies the arithmetic unit 13 with the data variable Y (2) representing the result of the addition X (2) + E.

When the control decoder 221 detects the asserted processing end request bit END in the control signal CONT1 immediately after the count value of the counter 231 is updated to “3” at the start of the cycle T8, the counter 231 counts. The value is held at "3". Delay circuit 2
23 is a control signal CON obtained by delaying the control signal including the asserted processing end request bit END by two cycles.
T2 is supplied to the third-stage controller 23 in cycle T10.

As described above, the cycles T3, T4, T6
At T7 and T7, the required micro-instructions are
Is supplied to the computing unit 12 from the. The second stage controller 2
In the cycles T4 and T7, the asserted processing start request bits STAR
In the cycle T10, T is supplied with the asserted processing end request bit END.

In the controller 23 of the third stage, in cycle T4, the control decoder 321 detects the asserted processing start request bit START in the control signal CONT2, and as a result, the count value of the counter 331 is reset to "0". Is done. The delay circuit 323 delays the control signal CONT2 including the processing start request bit START by one cycle according to the value “1” of the cycle number CYCLE3 stored in the cycle number register 303.
NT3 is supplied to the fourth-stage controller 24 in cycle T5. On the other hand, multiplexers 311, 312, 31
3 receives the mode bit MODE specifying the mode A from the control decoder 321, so that the micro instruction registers (# 0 to # 2) 304 to 306 belonging to the first group
Is supplied to the multiplexer 314. The count value of the counter 331 is equal to the cycle T5.
Is updated to "1" at the start of the cycle, and to "2" at the start of the cycle T6. The comparator 332 outputs the cycle number CYCLE stored in the cycle number register 303.
If the count value of the counter 331 is “1” according to the value “1” of the micro instruction register (# 0) 3
When the count value of the counter 331 is a value other than "1", the multiplexer 314 selects the SHIFT instruction of No. 04 and the NOP instruction respectively. Therefore, in the cycles T4, T5 and T6, the microinstruction MI3 supplied from the controller 23 to the arithmetic unit 13 is NO
P instruction, SHIFT instruction and NOP instruction. SHI
The arithmetic unit 13 that has been supplied with the FT instruction sets the data variable Y
Data variable Z representing the result of 2-bit right shift in (1)
(1) is supplied to the arithmetic unit 14.

Immediately after the count value of the counter 331 is updated to "3" at the start of the cycle T7, the control decoder 321 detects the asserted processing start request bit START in the control signal CONT2.
The count value of 31 is reset to “0”. The delay circuit 323 delays the control signal CONT3 including the processing start request bit START by one cycle in accordance with the value “1” of the cycle number CYCLE3 stored in the cycle number register 303, and outputs the control signal CONT3 in the cycle T.
At 8, it is supplied to the controller 24 of the fourth stage. On the other hand, the count value of the counter 331 is updated to “1” at the start of the cycle T8 and to “2” at the start of the cycle T9. Therefore, the cycles T7, T8 and T9
, The microinstruction MI3 supplied from the controller 23 to the arithmetic unit 13 is a NOP instruction, a SHIFT instruction and a NOP instruction, respectively. The arithmetic unit 13 that has received the SHIFT instruction supplies the arithmetic unit 14 with the data variable Z (2) representing the result of the right shift of the data variable Y (2) by 2 bits.

At the start of cycle T10, the counter 331
When the control decoder 321 detects the asserted processing end request bit END in the control signal CONT2 immediately after the count value of the counter 331 is updated to “3”, the counter 331
Is held at "3". The delay circuit 323 delays the control signal including the asserted processing end request bit END by one cycle.
In the cycle T11, the controller 24 of the fourth stage
Supply to

As described above, the SHIFT instruction is supplied from the controller 23 to the arithmetic unit 13 in cycles T5 and T8. In addition, from the third stage controller 23 to the fourth stage controller 24, the process start request bits START asserted in the cycles T5 and T8, respectively,
At 11, the asserted processing end request bit END is supplied.

In the controller 24 at the fourth stage, in cycle T5, the control decoder 421 detects the asserted processing start request bit START in the control signal CONT3, and as a result, the count value of the counter 431 is reset to "0". Is done. The delay circuit 423 delays the control signal CONT3 including the processing start request bit START by three cycles according to the value “3” of the cycle number CYCLE4 stored in the cycle number register 403.
NT4 is supplied to the fifth-stage controller 25 in cycle T8. On the other hand, multiplexers 411, 412, 41
3 receives the mode bit MODE specifying the mode A from the control decoder 421, so that the micro instruction registers (# 0 to # 2) 404 to 406 belonging to the first group
Is supplied to the multiplexer 414. The count value of the counter 431 is equal to the cycle T6.
Is updated to "1" at the start of the cycle, and to "2" at the start of the cycle T7. The comparator 432 calculates the cycle number CYCLE stored in the cycle number register 403.
When the count value of the counter 431 is “1” according to the value “3” of the micro instruction register (# 0) 4
04, a DATA word representing a constant F of the counter 431.
Is "2", the MUL1 instruction of the microinstruction register (# 1) 405 is sent to the counter 431.
Is "3", the MUL2 instruction of the microinstruction register (# 2) 406 is sent to the counter 431.
Is not a value other than "1", "2" and "3", the NOP instruction is
To select. Therefore, the cycles T5, T6 and T
In FIG. 7, the microinstructions MI4 supplied from the controller 24 to the arithmetic unit 14 are a NOP instruction, a DATA word, and a MUL1 instruction, respectively. DATA word and MUL
Arithmetic unit 14 receiving one instruction supplies multiplication Z (1) × F
Perform the first half of When the count value of the counter 431 is updated to “3” at the start of the cycle T8, the MUL2 instruction is supplied from the controller 24 to the arithmetic unit 14. MU
The arithmetic unit 14 receiving the supply of the L2 instruction performs multiplication Z (1) ×
By executing the latter half of F, the data variable W (1) representing the result of the multiplication is supplied to the data memory 15.

In cycle T8, after the count value of the counter 431 is updated to "3", the control decoder 421 detects the asserted processing start request bit START in the control signal CONT3. Reset to "0". Delay circuit 42
3 is a control signal C including a processing start request bit START.
The control signal CONT4 obtained by delaying the ONT3 by three cycles in accordance with the value “3” of the cycle number CYCLE4 stored in the cycle number register 403 is supplied to the fifth controller 25 in the cycle T11. Meanwhile, counter 4
The count value of 31 is "1" at the start of cycle T9.
At the beginning of cycle T10, to "2"
At the start of 11, each is updated to "3". Therefore, the microinstruction MI4 supplied from the controller 24 to the arithmetic unit 14 in the cycles T9, T10 and T11.
Are the DATA word, MUL1 instruction and MUL, respectively.
Two instructions. DATA word, MUL1 instruction and MU
The arithmetic unit 14 receiving the supply of the L2 instruction performs multiplication Z (2) ×
A data variable W (2) representing the result of F is stored in the data memory 15
Supply to

At the start of cycle T11, the counter 431
Is updated to "3", the control decoder 4
When 21 detects the asserted processing end request bit END in the control signal CONT3, the count value of the counter 431 is held at "3". Delay circuit 42
3 is a control signal CONT obtained by delaying the control signal including the asserted processing end request bit END by three cycles.
4 is supplied to the fifth-stage controller 25 in the cycle T14.

As described above, a required microinstruction is supplied from the controller 24 to the arithmetic unit 14 in each of the cycles T6 to T11. In addition, the controller 24 in the fourth stage transmits the processing start request bit START asserted in each of the cycles T8 and T11 in the cycles T8 and T11 and the processing end request bit E asserted in the cycle T14.
ND is supplied.

In the controller 25 at the fifth stage, in cycle T8, the control decoder 521 detects the asserted processing start request bit START in the control signal CONT4, and as a result, the count value of the counter 531 is reset to "0". Is done. The count value of the counter 531 is updated to “1” at the start of the cycle T9 and to “2” at the start of the cycle T10. The comparator 532 is
Cycle number CY stored in cycle number register 503
According to the value “1” of CLE5, the STORE instruction is given to the multiplexer 514 when the count value of the counter 531 is “1”, and the NOP instruction is given to the multiplexer 514 when the count value of the counter 531 is a value other than “1”. Let me choose. Therefore, the microinstructions MI5 supplied from the controller 25 to the data memory 15 in the cycles T8, T9 and T10 are a NOP instruction, a STORE instruction and a NOP instruction, respectively. The data memory 15 receiving the STORE instruction stores the data variable W (1).

At the start of cycle T11, the counter 531
Is updated to "3", the control decoder 5
21 detects the asserted processing start request bit START in the control signal CONT4.
The count value of 1 is reset to “0”. The count value of the counter 531 is updated to “1” at the start of the cycle T12 and to “2” at the start of the cycle T13. Therefore, in the cycles T11, T12 and T13, the microinstruction MI5 supplied from the controller 25 to the data memory 15 includes the NOP instruction,
STORE instruction and NOP instruction. The data memory 15 receiving the STORE instruction stores the data variable W
(2) is stored.

At the start of cycle T14, counter 531
Is updated to "3", the control decoder 5
When 21 detects the asserted processing end request bit END in the control signal CONT4, the count value of the counter 531 is held at "3". Delay circuit 52
In a cycle T15, the control unit CONT5 delays the control signal CONT4 including the asserted processing end request bit END by one cycle in accordance with the value "1" of the cycle number CYCLE5 stored in the cycle number register 403. Supply to 4.

As described above, the STORE instruction is supplied from the controller 25 to the data memory 15 in the cycles T9 and T12, respectively. In the cycle T15, the asserted processing end request bit END is supplied from the fifth-stage controller 25 to the control unit 4.

As described above, according to the example of FIG. 9, the control unit 4 only needs to supply the control signal CONT0 including the processing start request bit START asserted in the cycle T1 to the first stage controller 21. , X (1) to W from cycle T2 to cycle T9
The first pipeline processing for obtaining (1) and the second pipeline processing for obtaining X (2) to W (2) from cycle T5 to cycle T12 are executed. The end of the second pipeline processing is determined by the asserted processing end request bit END.
Is transmitted from the fifth-stage controller 25 to the control unit 4 by the control signal CONT5 containing Therefore, the control unit 4 supplies the control signal CONT0 to the first-stage controller 21 and then sends the control signal CONT0 from the fifth-stage controller 25 to the control signal CONT0.
5 processing units 11 to 1
5, while performing data processing, other processing can be performed. In addition, since each of the controllers 21 to 25 has a function of generating a NOP instruction for preventing the corresponding processing units 11 to 15 from performing unnecessary operations, the capacity of the instruction memory 5 in FIG. 1 can be reduced.

In the example of FIG. 9, the first register group (# 0 to # 2) to be selected in mode A in each of the controllers 22 to 24 is used. Second register groups (# 3 to # 5) to be performed may be used. Mode bit MO in control signal CONT0
When the control unit 4 changes the DE, the arithmetic units 12 to 14
Is switched. For example, the addition in the arithmetic unit 12 can be switched between round addition and non-round addition. It is also possible to store a microinstruction in the second register group during execution of the microinstruction of the first register group, or to store a microinstruction in the first register group during execution of the microinstruction of the second register group. is there.

A micro-instruction for normal processing is stored in the first register group in the controller 23, and a micro-instruction for exception processing when an exception such as overflow occurs in the arithmetic unit 12 is sent to the controller 23. Are stored in the second register group in
Arithmetic unit 1 according to flag signal FLAG2 supplied from
3 is automatically switched. Other flag signal F
LAG3 can be used for a similar purpose.

[0063]

As described above, according to the present invention, a plurality of controllers are cascade-connected to each other similarly to a plurality of processing units, and a control signal requesting the start of a series of data processing is transmitted to the first stage. Each processing unit processes the given data signal in accordance with the micro-instruction and supplies a data signal representing the result of the processing to the next processing unit. When the processing start request bit in the control signal detected is detected, supply of the microinstruction to the corresponding processing unit is started, and the signal obtained by delaying the control signal by the number of cycles required for processing of the corresponding processing unit is replaced by the following signal. Since the data is supplied to the controller of the stage, a series of data processing by a plurality of processing units connected in cascade can be started at a predetermined timing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data processing device according to the present invention.

FIG. 2 is a diagram showing a field configuration of an instruction supplied from an instruction memory in FIG. 1;

FIG. 3 is a diagram showing a field configuration of six control signals in FIG. 1;

FIG. 4 is a block diagram showing a detailed configuration of a first-stage controller in FIG. 1;

FIG. 5 is a block diagram showing a detailed configuration of a second-stage controller in FIG. 1;

FIG. 6 is a block diagram showing a detailed configuration of a third-stage controller in FIG. 1;

FIG. 7 is a block diagram showing a detailed configuration of a controller at a fourth stage in FIG. 1;

FIG. 8 is a block diagram showing a detailed configuration of a controller at a fifth stage in FIG. 1;

FIG. 9 is a time chart illustrating an operation example of the data processing device of FIG. 1;

[Explanation of symbols]

Reference Signs List 1 data bus 2 external memory 3 DMA controller 4 control unit 5 instruction memory 6 instruction bus 11, 15 data memory (processing unit) 12 to 14 computing unit (processing unit) 21 to 25 controller 100, 200, 300, 400, 500 Instruction supply unit 120, 220, 320, 420, 520 Control signal transfer unit 130, 230, 330, 430, 530 Micro program counter 140 Loop counter

Claims (8)

[Claims] 1. A data processing apparatus comprising a plurality of processing elements cascaded with each other to form a first path and a second path, wherein each of the plurality of processing elements is located on the first path. A processing unit for processing a data signal supplied via the first input according to a microinstruction, and supplying a data signal representing a result of the processing to the first path. And a second input disposed on the second path; and supplying the microinstruction to the processing unit when detecting a processing start request bit in a control signal supplied via the second input. And a controller for supplying a signal obtained by delaying the control signal by the number of cycles required for processing of the processing unit to the second path. 2. The data processing apparatus according to claim 1, wherein the controller of each of the plurality of processing elements specifies a field indicating one microinstruction and one of the plurality of processing elements. Means for decoding an instruction having a field indicating an address, and accepting the microinstruction based on the instruction when the address specified in the instruction matches the address assigned to the controller. A data processing device comprising: 3. The data processing apparatus according to claim 1, wherein the controller of each of the plurality of processing elements includes a NOP (no opera) for designating a non-operation of the processing unit.
an instruction decoder for decoding an instruction having a NOP generator for generating an instruction, a field indicating one microinstruction, and a field indicating the number of cycles required for processing of the processing unit; A microinstruction register for storing a microinstruction obtained from the instruction decoder based on the instruction, a cycle number register for storing a cycle number obtained from the instruction decoder based on the instruction, and the NOP generator A multiplexer for selectively supplying a generated NOP instruction or a microinstruction stored in the microinstruction register to the processing unit; and a multiplexer supplied via the second input to detect the processing start request bit. A control decoder for decoding the control signal, and a second A delay circuit for delaying the supplied control signal by the number of cycles stored in the cycle number register; a counter for counting pulses of a clock signal; a count value of the counter and the cycle number register And a comparator for comparing the number of cycles stored in the control decoder, when the control decoder detects the processing start request bit, the counter is reset, and according to the result of the comparison by the comparator, A data processing device, wherein selection in a multiplexer is controlled. 4. The data processing device according to claim 1, wherein the controller of a processing element at the forefront stage of the plurality of processing elements includes a NOP (no opera) designating a non-operation of the processing unit.
An NOP generator for generating an instruction, a field indicating one microinstruction, a field indicating the number of cycles required for processing of the processing unit, and a field indicating the number of cycles required for processing of the processing unit. An instruction decoder for decoding an instruction having a field indicating a pipeline pitch representing a maximum value of the required number of cycles and a field indicating the number of repetitions of processing in the processing unit of each of the plurality of processing elements; A microinstruction register for storing a microinstruction obtained from the instruction decoder based on the instruction; a cycle number register for storing a cycle number obtained from the instruction decoder based on the instruction; To store the pipeline pitch obtained from the instruction decoder based on A pipeline pitch register; a repetition number register for storing the repetition number obtained from the instruction decoder based on the instruction; and a NOP instruction generated by the NOP generator or a micro stored in the micro instruction register. A multiplexer for selectively supplying an instruction to the processing unit; a control decoder for decoding the control signal supplied via the second input so as to detect the processing start request bit; The new control signal is generated so as to assert a processing start request bit of a new control signal each time a request is received, and to assert a processing end request bit of the new control signal when a processing end request is received. A code generator for controlling the control signal generated by the code generator. A delay circuit for delaying by the number of cycles stored in the register, a first counter for counting pulses of the clock signal, and a count value of the first counter and stored in the cycle number register. A first comparator for comparing a cycle number with a second comparator for comparing a count value of the first counter with a pipeline pitch stored in the pipeline pitch register; A second counter for counting pulses supplied each time the first counter is reset; and a second counter for comparing the count value of the second counter with the number of repetitions stored in the repetition number register. A third comparator, wherein the first counter is provided when the control decoder detects the processing start request bit or the second comparator The code generator is reset when the coincidence between the count value of the first counter and the pipeline pitch stored in the pipeline pitch register is detected, and the code generator performs the processing each time the first counter is reset. A start request is provided, selection in the multiplexer is controlled according to a result of the comparison by the first comparator, and the second counter is configured to detect when the control decoder detects the processing start request bit. Reset, the third
When the comparator detects that the count value of the second counter matches the number of repetitions stored in the repetition number register, the code generator is provided with the processing end request and the first counter is A data processing device wherein updating is prohibited. 5. The data processing device according to claim 4, wherein the controller of each of the processing elements other than the foremost processing element of the plurality of processing elements determines the inactivity of the processing unit. NOP (no opera
an instruction decoder for decoding an instruction having a NOP generator for generating an instruction, a field indicating one microinstruction, and a field indicating the number of cycles required for processing of the processing unit; A microinstruction register for storing a microinstruction obtained from the instruction decoder based on the instruction, a cycle number register for storing a cycle number obtained from the instruction decoder based on the instruction, and the NOP generator A multiplexer for selectively supplying a generated NOP instruction or a microinstruction stored in the microinstruction register to the processing unit; and a second processor for detecting the processing start request bit and the processing end request bit. Control data for decoding the control signal supplied via the input; A delay circuit for delaying the control signal supplied via the second input by the number of cycles stored in the cycle number register; and a counter for counting pulses of the clock signal. A comparator for comparing the count value of the counter with the number of cycles stored in the cycle number register, wherein the counter is reset each time the control decoder detects the processing start request bit, A data processing device for controlling selection of the multiplexer in accordance with a result of the comparison by the comparator and prohibiting updating of the counter when the control decoder detects the processing end request bit. 6. The data processing apparatus according to claim 1, wherein the controller of at least one specific processing element of the plurality of processing elements includes a NOP (no opera) designating a non-operation of the processing unit.
a NOP generator for generating instructions, a plurality of microinstruction registers for storing microinstructions, a field for indicating one microinstruction, and a field for indicating the number of cycles required for processing of the processing unit. Decoding an instruction having a field indicating an index that designates one of the plurality of microinstruction registers, and specifying the microinstruction based on the instruction by the index out of the plurality of microinstruction registers An instruction decoder for storing in a microinstruction register; a cycle number register for storing a cycle number obtained from the instruction decoder based on the instruction; and a NOP instruction generated by the NOP generator or the plurality of NOP instructions. Microphone stored in each of the micro instruction registers A multiplexer for selectively supplying one of the instructions to the processing unit; and a control for decoding the control signal supplied via the second input to detect the processing start request bit. A decoder, a delay circuit for delaying the control signal supplied via the second input by the number of cycles stored in the cycle number register, a counter for counting pulses of a clock signal, and the counter A comparator for comparing the count value of the cycle number with the number of cycles stored in the cycle number register, wherein the counter is reset when the control decoder detects the processing start request bit, and the comparator Wherein the selection in the multiplexer is controlled according to the result of the comparison by the data processor. 7. The data processing apparatus according to claim 6, wherein the plurality of micro instruction registers of the specific processing element form a first group and a second group, and are supplied via the second input. The control signal is the first
A mode bit for designating a group or the second group, wherein the controller of the specific processing element responds to the mode bit by storing a micro instruction stored in each of the micro instruction registers constituting the first group. A data processing apparatus, further comprising means for supplying an instruction or a microinstruction stored in each of the microinstruction registers constituting the second group to the multiplexer. 8. The data processing device according to claim 6, wherein the plurality of microinstruction registers of the specific processing element form a first group and a second group, and the processing is located before the specific processing element. The processing unit of the element further has a function of supplying a flag signal indicating the occurrence of an exception; and the controller of the specific processing element, the micro instruction register configuring the first group according to the flag signal. And a microinstruction stored in each of the microinstruction registers forming the second group or the microinstruction stored in each of the microinstruction registers constituting the second group.