JPH0799454A - Circuit shared error correction code processing circuit - Google Patents

Abstract

PURPOSE:To reduce circuitry by sharing an exclusive OR gate between coders generating plural different error correction codes, thereby eliminating redundant part of the circuit. CONSTITUTION:When the processing circuit is used for an extended Humming, coder, a switch S1 is thrown to the position of ground by a control signal SEN and a 0-level appears at an output. Information bit signals D2-D5 are received and check bits P11, P21, P31, P41 are generated by exclusive OR gates E5, E7, E9, E11. When the processing circuit is used for a BCH coder, the switch S1 is thrown to the position of an information bit signal D3 and the signal D3 appears at the output. Then a check bit signal P12 is generated by exclusive OR gates E1, E5, E13, E17 and a check bit signal 22 is generated by exclusive OR gates E2, E7, E13 and then one coder is used to use respective exclusive OR gates E1-E8 in common, from which check bit signals P11-P44 are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to time division multiple access (TD).
The present invention relates to a parallel processing type error correction code processing circuit in the case of performing communication according to (MA), and particularly to an error correction code processing circuit of a channel codec circuit that uses different error correction codes between channels.

Recent advances in semiconductor technology have made it possible to economically realize the encoding and decoding of information, and the error correction code has been widely applied. Wireless communication,
Especially in the field of mobile communication, it has come to be designed on the assumption that an error correction code is applied. In fact, when there are many errors in the transmission line such as mobile communication, just using the error detection code causes repeated retransmissions, resulting in poor efficiency and undetectable error, which causes data to be corrupted. There is. In this way, the adoption of error correction codes has become common, but different error correction codes are used between channels in time-division multiplex connection in which the transmission path is divided into time slots and shared by multiple channels. There is.

FIG. 3 is a block diagram showing an example of a channel codec circuit of a single error correction code adopted in a standard of a conventional digital car telephone system.
In the figure, four channels are time-division multiplexed, and a plurality of different single error correction codes are used for each channel. That is, the transmission data signals SI1, SI2, SI3, SI4 of the respective channels are expanded (8, 4) Hamming encoder C1, depending on the type of channel.
(15,11) BCH encoder C2, shortened (14,10)
BCH encoder C3, shortened (12,8) BCH encoder C4
The signal SO1 is output after being switched by the multiplexer M1 for each channel.

The extended (8,4) Hamming encoder C1 described above.
Is an extended (8,4) Hamming coding capable of single error correction / double error detection (SED / DED) with a code length of 8 and a number of information bits of 4. Also, (15,11) BC
The H encoder C2 is capable of single error correction / double error detection (SED / DED) with a code length of 15 and 11 information bits (1
5, 11) BCH encoding is performed.

Also, a shortened (14,10) BCH coder C
3 is a single error correction / double error detection with a code length of 14 and 10 information bits, which is obtained by placing 1 information bit as 0 from the above (15,11) BCH code and encoding and removing the 0. (SED / DED) possible encoding is performed. Similarly, the shortened (12,8) BCH coder C4 sets three information bits to 0 from the (15,11) BCH code.
Code length 1 obtained by removing the 0 by coding
2. Single error correction / double error detection with 8 information bits (S
ED / DED) capable encoding. (Reference: "Code theory" by Hideki Imai, published by The Institute of Electronics, Information and Communication Engineers)

FIG. 4 is a block diagram of a conventional encoder and decoder for error correcting code. The transmission data signal TSI is
A signal TSO to which a check bit is added is output through a certain error correction encoder C5. Also the received data signal RSI
A signal RSO error-corrected by the decoder D1 of the same type as that at the time of transmission is obtained.

[0007]

However, in the above-mentioned conventional channel codec circuit, when a plurality of different error correction codes are used between channels, an encoder is provided for each error correction code. Circuit scale increases, and the semiconductor chip area increases accordingly.
There were problems such as an increase in manufacturing costs and an increase in power consumption. In the conventional channel codec circuit,
Even for encoders / decoders that use the same error correction code, separate circuits are provided, so that the scale of the channel codec circuit becomes large, and there are the same problems as described above.

In view of the above problems, it is an object of the present invention to eliminate the redundant part of the circuit by sharing the circuit if a plurality of encoders or encoders / decoders of the same type are used. An object is to provide a circuit sharing type error correction code processing circuit with a reduced scale.

[0009]

In order to solve the above problems, the present invention has the following constitution. That is, the present invention provides an encoder of a channel codec circuit for applying a plurality of different error correction codes between a plurality of channels to which time slots of time division multiplex communication are allocated, the encoder generating the plurality of different error correction codes. This is a circuit sharing type error correction code processing circuit characterized in that an exclusive OR gate is shared between them.

Further, according to the present invention, in a decoder of a channel codec circuit for applying a plurality of different error correction codes among a plurality of channels to which time slots of time division multiplex communication are allocated, one of two values is set. A switch circuit is provided for selecting one of the values of the check bit signal and inputting it to the decoder. When the switch circuit selects the value of the check bit signal, the switch circuit operates as a decoder, and the switch is performed. It is a circuit common type error correction code processing circuit, which operates as an encoder when the circuit selects one of two values.

[0011]

According to the present invention, the same exclusive-OR gate is shared by a plurality of encoders that perform a plurality of types of encoding, and the scale of the channel codec circuit is reduced.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit configuration diagram of a first embodiment of a circuit sharing type error correction code processing circuit according to the present invention. The same example
This is an example of sharing an exclusive OR gate between encoders that generate a plurality of different error correction codes, and is expanded (8, 4).
Hamming code, (15,11) BCH code, shortened (1
The four codes of the 4,10) BCH code and the shortened (12,8) BCH code are encoded by using one encoder sharing the exclusive OR gate. All of the above four codes are codes that are applied to the standard as a single error correction code in the digital car telephone system.

In FIG. 1, D1 to D11 indicate information bit signals, and P11 to P44 indicate check bit signals. Further, E1 to E18 each represent an exclusive OR gate, and the switch S1 controlled by the control signal SEN is a switch for switching the operation mode of the encoder.

First, when used as an expanded (8,4) Hamming encoder, the control signal SEN causes the switch S1 to fall to the ground side, and a 0 level appears at the output of the switch S1. Then, 4-bit information bit signals D2 to D5
Is input, and the exclusive OR gate E5,
Check bit signals P11, P2 by E7, E9, E11
1, P31, P41 are generated.

Next, when used as a (15,11) BCH encoder, the control signal SEN causes the switch S1 to fall to the information bit signal D3 side, D3 appears at the output of the switch S1 and the 11-bit information bit. Signals D1 to D11
Is entered. Then, the check bit signal P12 is generated from the data of the information bit by the exclusive OR gates E1, E5, E13 and E17. Similarly, the exclusive OR gates E2, E7 and E14 are used to generate the check bit signal P2.
2. Check bit signal P32 by exclusive OR gates E3, E9, E15, exclusive OR gates E4, E11,
The check bit signal P42 is generated by E16 and E18.

Next, when used as a shortened (14,10) BCH encoder, the switch S is switched by the control signal SEN.
1 is pushed to the information bit signal D3 side, D3 appears at the output of the switch S1, and the 10-bit information bit signal D2-
D11 is input. Then, the exclusive OR gate E1
Check bit signal P1 by 3, E14, E15, E16
3, P23, P33, P43 are output. Then, when used as a shortened (12,8) BCH encoder, since 8-bit information bit signals D4 to D11 are input,
It has nothing to do with the state of switch S1. Then, the exclusive OR gates E6, E8, E10, E12 output the check bit signals P14, P24, P34, P44.

Next, FIG. 2 is a circuit configuration diagram of a second embodiment of the circuit common type error correction code processing circuit according to the present invention.
The embodiment is an example of a circuit common type error correction code processing circuit provided with a switching circuit that uses both an encoder and a decoder for an expanded (8,4) Hamming code. In the figure, DA1 to DA
4 is an information bit signal input, PA1 to PA4 are check bit signal inputs, DB1 to DB4 are information bit signal outputs, PB
Reference numerals 1 to PB4 denote check bit signal outputs, and E19 to E26 denote exclusive OR gates. The switch S2 having four circuits and two contacts, which is controlled by the control signal SWE, is a switching circuit that switches between the encoder and the decoder. A1 to A4 are 4-input AND gates, but one of the four inputs is a negative logic input (indicated by a circle).

First, when the error correction code processing circuit of FIG. 2 is used as an encoder, the switch S2 is turned to the ground side by the signal SWE. Then, 4-bit information bit signals DA1 to DA4 are input, and exclusive OR gates E19 to E22 generate check bit signals PB1 to PB4.

Next, when used as a decoder, the switch S2 is turned down to the signal line side by the signal SWE, and the information bit signals DA1 to DA4 and the check bit signals PA1 to PA4 which may include an error are input. Information bit signal DB1 in which a single error has been corrected via exclusive OR gates E19 to E22, AND gates A1 to A4 including negative logic inputs, and exclusive OR gates E23 to E26
~ DB4 is output.

Although the preferred embodiment has been described above, this is not a limitation of the present invention. For example, in the embodiment, the switching circuit is schematically described as a switch, but the switching is actually performed by the AND gate. Further, it is obvious that the present invention can be applied to codes other than the codes described in the embodiments.

[0021]

As described above, according to the present invention,
A shared circuit error correction code processing circuit with a reduced circuit scale is provided by sharing the exclusive OR gate between encoders that generate different error correction codes to eliminate the redundant part of the circuit. There is an effect that can be done.
In the case of encoders / decoders of the same type, the switching circuit serves as both the encoder and the decoder, thereby eliminating the redundant part of the circuit and reducing the circuit scale. Can be provided.
In particular, the circuit sharing type error correction code processing circuit of the present invention reduces the size of the circuit to reduce the size of the mobile phone or the portable terminal,
It is effective in reducing power consumption.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a circuit shared type error correction code processing circuit according to the present invention, showing a case where an exclusive OR gate is shared among four types of encoders.

FIG. 2 is a circuit configuration diagram of an embodiment of a circuit sharing type error correction code processing circuit according to the present invention, showing a case where an encoder and a decoder are shared.

FIG. 3 is a block diagram of an encoder portion of a conventional channel codec circuit that handles a plurality of codes.

FIG. 4 is a block diagram showing that a conventional encoder and decoder are composed of individual blocks.

[Explanation of symbols]

 E1 to E26 exclusive OR gate S1 switch S2 switch A1 to A4 AND gate (including negative logic input) C1 expansion (8,4) Hamming encoder C2 (15,11) BCH encoder C3 shortening (14,10) ) BCH encoder C4 shortened (12,8) BCH encoder M1 multiplexer C5 single error correction encoder (parallel processing type) D1 single error correction decoder (parallel processing type)

Claims (2)

[Claims] 1. An encoder of a channel codec circuit for applying a plurality of different error correction codes between a plurality of channels to which time slots of time division multiplex communication are allocated, wherein the encoder generates the plurality of different error correction codes. A circuit sharing type error correction code processing circuit characterized in that an exclusive OR gate is shared between them. 2. A decoder of a channel codec circuit for applying a plurality of different error correction codes among a plurality of channels to which time slots of time division multiplex communication are assigned, wherein either one of two values and a check bit signal are used. A switching circuit for selecting any one of the values of 1 and 2 and inputting it to the decoder. When the switching circuit selects the value of the check bit signal, it operates as a decoder, and the switching circuit is A circuit common type error correction code processing circuit, which operates as an encoder when any one of the values is selected.