JP2013198140A - Encoding and decoding system enabling error correction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an encoding/decoding system capable of coping with error correction up to three bit with a simple configuration.SOLUTION: A product code of eight rows and eight columns is generated by using a (8, 4)BCH code, error detection/correction of each row and each column of the product code is performed, and further, an intersection point of a row and a column where an error is detected is calculated and corrected. The product code is formed by combining a first BCH code formed in a code direction of data of a data matrix and a second BCH code generated by transposing a syndrome of a BCH code formed in a column direction of a data code of the data matrix to be regarded as an information bit.

Description

  The present invention relates to an encoding / combining method capable of error correction using a Hamming code and a product code, and more particularly to an information transmission for operating a power system, and a code error caused by noise generated on a transmission line. The present invention relates to an encoding / decoding system that can be corrected.

In general, an information transmission apparatus used for operating a power system is required to have reliability similar to that required for stable operation of the power system, and the transmission quality is 1 × in error rate. It is required to be about 10 ⁻⁷ or less.

  In addition, because there is a restriction on the time to transmit information to the system and prevent it from being shaken at the time of system failure, the transmitted information must be transmitted without error. In addition to suppressing the occurrence of transmission delay time due to re-transmission or delay of information that occurs, it is necessary to suppress transmission of erroneous data.

In order to cope with such conditions, so far we have adopted advanced error detection methods using higher transmission speeds and higher-stage generator polynomials, etc. A communication line with a low error rate is required.
However, assuming a distributed power supply system that is expected to expand in the future and a power supply system that utilizes natural energy, it is assumed that the location where the equipment is installed will be a rural area.

  In general, when configuring a communication line for operating a power system in such a rural area, a broadband transmission line is disadvantageous in terms of cost-effective capital investment, and the amount of information is always large. Since it is not required, it is required to construct a narrow-band transmission path that is inexpensive, so that it is often impossible to maintain good transmission quality.

  As a result, it is unavoidable to adopt a low-speed and simple error correction method and an error detection method as the encoding method to be transmitted, but power system operation is also applied to such a simple encoding method. Is required to have high quality and reliability. As an example of this simple coding method, for example, when a well-known (7, 4) Hamming code is used, 1-bit error correction is possible because the Hamming distance is 3 bits. It will not be able to deal with continuous noise such as burst noise because it will erroneously correct missing data. For this reason, there arises a problem that a necessary transmission quality and a delay due to retransmission or delay occur, and an allowable transmission delay time cannot be secured.

In particular, noise at electrical stations is mainly burst noise due to switching surges such as circuit breakers, and in addition to this continuous burst noise, it also generates burst noise due to lightning discharge. Even a simple coding method that can correct a bit error is required to have a high error correction capability.
For this reason, a method of correcting 2-bit error (Patent Document 1) to improve this characteristic and a method of using a product code as a hamming code to deal with a burst error have been studied, and the error detection performance and characteristics are improved. It is improving.

  However, although Patent Document 1 described above can correct a 2-bit error with these methods, the 3-bit error changes to a different code pattern, and thus cannot be detected as an error. Further, in the (8, 4) expanded Hamming (BCH) code shown in FIG. 1 in which parity bits are added to the (7, 4) Hamming code, 2-bit error detection is possible but correction is impossible. A 3-bit error is erroneously corrected to a different code, so that there is a problem that erroneous information is transmitted.

  The ready-robinson decoding method described in Non-Patent Document 1 allows error correction of many bits. However, since correction requires many iterative processes and requires a considerable amount of calculation, In the case of burst noise in which data is erroneous, error correction requires a lot of processing time, and the probability of error correction may increase. Therefore, in such a coding system, there is a concern that it may lead to transmission of erroneous information in power system operation or delay in information transmission, and is suitable as a transmission code system for operating the power system. There is a problem of not.

Japanese Patent Laid-Open No. 2001-251197

"Code theory", IEICE, pp.233-235

  The present invention has been made in view of the above circumstances, and applies a product code system to (8, 4) extended Hamming code, and can be applied to a narrowband transmission path. Error detection and error correction / correction is possible even if the number of iterations is small. For example, for random bit errors due to thermal noise and continuous bit errors due to burst noise due to electrical noise or lightning noise. The present invention also provides a high-speed and simple error correction method that enables error correction and an encoding / combination method that enables error detection.

  The first technical means generates a first (8, 4) expanded Hamming code based on a 4-by-4 data matrix for every 4 blocks of 4-bit digital data generated based on input data, A second (8,4) expanded Hamming code is generated based on the transposed matrix of the syndrome part of the (8,4) expanded Hamming code generated based on the transposed matrix of the data matrix, and the generated first ( (8,4) The expanded Hamming code and the second (8,4) expanded Hamming code are combined to generate a product code of 8 rows and 8 columns, and a code of a row or a column of the generated product code is sequentially read out as a transmission code Characterized by an encoding method characterized by

  The second technical means sequentially arranges blocks of the (8, 4) expanded Hamming code encoded and transmitted by the encoding method of the first technical means in a matrix table of 8 rows and 8 columns, and a product code matrix As a procedure 1, first error test was performed on four code strings including data codes in the column direction of the four data code strings of the data matrix in the product code, and a 1-bit error or 2-bit error was detected. An error detection flag to that effect is set in the code string, and error test is performed on eight code strings in the code string direction of the data corresponding to the data matrix as procedure 2, and a 2-bit error is detected in the code string in which the 2-bit error is detected. When a flag is set, a 1-bit error is detected, and the detected error code belongs to a code string for which an error flag is set in the test of step 1, the error is corrected and an error correction flag is added to the code string. If the error detection flag is not set in step 1, the 3-bit error flag is set in the code string without correction, and the error test in step 2 is reflected as step 3 in step 1. The second error test is performed on the code string, and if a 1-bit error is detected in the same way as in step 2, the error part is corrected and an error correction flag is set, or a 3-bit error flag is set and a 2-bit error is detected. If detected, an error 2-bit error flag is set, and a code string of rows and columns in which a 2-bit or 3-bit error flag is set for the 8-by-8 product code matrix reflecting the error test of procedure 3 as procedure 4 If the intersection is not error-corrected, the intersection point is corrected, and as the procedure 5, the correction of the procedure 4 is reflected and the code sequence verified in the procedure 1 is subjected to the third error test. But If issued, repeat steps 1 through Step 4, characterized by error correction method code to terminate the process if no error is detected.

  In the error correction method of the second technical means, the third technical means determines the intersection with the code string in which the error correction flag is set when there is no intersection between the row and the column in which the error flag is set in step 4. It is characterized by seeking.

  According to a fourth technical means, in the error correction method described in the second technical means, if no error is detected in the error test of the procedure 1 and the procedure 2, the subsequent procedure is omitted and the process is terminated. Characterize

  According to a fifth technical means, in the error correction method described in the second technical means, only the correction of 1-bit error is detected in the procedure 3, and the total number of correction bits is detected in the first procedure. If the number is less than the total number of error bits, or if the number is the same as the number of 1-bit errors detected, the following procedure is omitted and the process is terminated.

The sixth technical means is characterized by a decoding method for extracting and outputting data from the code corrected by any one of the error correction methods of the second to fifth technical means.

  A seventh technical means expands transmission data in which 4-bit data is input in units of 4 blocks into a data matrix table of 4 rows and 4 columns, and outputs the data matrix and its transposed matrix; and the data A first (8, 4) expanded Hamming code is generated based on the matrix, a (8, 4) expanded Hamming code is generated based on the transposed matrix, and a syndrome matrix extracted from the generated expanded Hamming code (8, 4) an expanded Hamming code generation unit for generating a second (8, 4) expanded Hamming code based on the transposed matrix of the first and second (8, 4) expanded Hamming codes generated An encoding apparatus includes: a product code generation unit that generates a product code matrix of 8 rows and 8 columns by combining; and an output unit that sequentially reads out the code strings of the product code matrix and uses them as transmission codes.

  The eighth technical means comprises: a receiving unit that expands the received code encoded by the encoding method according to claim 1 into a matrix table of 8 rows and 8 columns; An error detection flag is set in the detected code string, and an error correction unit that corrects the code in which the error is detected, and an output unit that extracts the error-corrected data, the error correction unit includes an error test A flag setting unit, a correction unit, a correction table generation unit, and a determination unit. The error test unit performs error tests in steps 1 to 3 and 5 for the product code expanded in the table, and sets a flag. The setting unit sets an error flag in the code string detected in the test, sets an error correction flag in the code string in which the error is corrected, and the correction unit detects 1 bit detected in steps 2, 3, and 5. Correct the error and go to step 4. The determination unit corrects the sign of the intersection of the row and column, and the determination unit performs the error correction end determination in steps 2, 3, and 5, and the output unit receives the data based on the end determination of the determination unit. It is characterized by a decoding device that extracts and outputs.

  The ninth technical means is a program for causing a computer to execute any one of the first to sixth technical means.

  According to the present invention, it is possible to construct an encoding / combining system capable of correcting an error of 3 bits as well as 2 bits with a simple system configuration.

It is a figure explaining the (8,4) expansion hamming (BCH) code | symbol used by this invention. It is a figure which shows the example of an (8,4) expansion hamming (BCH) code | symbol. It is a figure explaining the product code | symbol in this invention. It is a figure which shows the outline | summary of the communication system to which this invention is applied. It is a figure which shows the structure of the encoding apparatus of this invention. It is a flowchart explaining the encoding method of this invention. It is a figure explaining the error correction in the decoding process of this invention. It is a flowchart of the error correction process in this invention. It is a flowchart of the error correction process in this invention. It is a flowchart of the error correction process in this invention. It is a figure which shows the structure of the decoding apparatus of this invention.

The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a well-known (8, 4) expanded Hamming code (BCH code) used in the present invention.
X1 to X4 are data parts (information bits), C1 to C4 are syndrome parts (check bits), and C1 to C3 shift X1 to X4 by 3 bits to generate a generator polynomial G1 (X) = X ³ + X A remainder divided by +1, C4 is a remainder P obtained by shifting the data part and the syndrome part X1 to C3 by 1 bit and dividing by a generator polynomial G2 (X) = X + 1, as illustrated in the table of FIG. 16 codes are formed. Note that P is a so-called even parity.

If these codes are transmitted and there is no error in the transmission process, the received codes X1 to C3 are divisible by the generator polynomial G1 (X) = X ³ + X + 1. X1 to C4 are also divisible by the generator polynomial G2 (X) = X + 1.
When an error occurs in one bit, X1 to C3 are not divisible by the generator polynomial G1 (X) = X ³ + X + 1. However, the bit in which an error has occurred can be identified from the remainder. X1 to C4 are not divisible by the generator polynomial G2 (X) = X + 1 except when C4 is in error.
When an error occurs in 2 bits, X1 to C3 are not divisible by the generator polynomial G1 (X) = X ³ + X + 1, but X1 to C4 are divisible by the generator polynomial G2 (X) = X + 1.

Further, these 16 codes are different in at least four places when compared with the respective codes. That is, the minimum hamming distance of this code is 4, 1-bit error correction in a transmission process or the like is possible, and 2-bit errors can be detected.
If a transmission code in the table of FIG. 2 has an error in one or two bits during the transmission process, the received code becomes a code that does not correspond to any of the table in FIG. 2, and an error has occurred. Can be detected.
Therefore, by comparing the received code with each of the codes in the table of FIG. 2, in the case of a 1-bit error, the received code is detected only at one location from the transmitted code. If corrected, the error can be corrected.
However, if an error occurs in 2 bits, the code where the difference between the received code and the two locations is detected by comparison with the code in the table of FIG. Cannot be identified and errors can be detected, but errors cannot be corrected.

When an error occurs in 3 bits, a difference in one place is detected between the received code and a code other than the transmitted code, and the code is corrected and erroneously corrected. The present invention detects such a 3-bit error and enables error correction.
If an error occurs in 4 bits, the received code will match other codes other than the transmitted code, and neither error nor detection can be made. However, the probability that an error of 4 bits will occur is extremely low. Take corrective action.

FIG. 3 shows the configuration of the product code used in the present invention. Four blocks (8, 4) expanded Hamming codes including data parts 1 to 4, 5 to 8, 9 to 12, and 13 to 16 are arranged in 1 to 4 rows, respectively. A matrix of 1 row 1 column to 4 rows 4 columns is a data portion, and a matrix of 1 row 4 columns to 4 rows 8 columns is a first syndrome portion for the data portion.
Next, with respect to the column direction 1 to 4 columns corresponding to the transposed matrix of the data part, the remainders d1 to d3 obtained by dividing the generator polynomial G1 (X) with respect to the information bits of 1, 5, 9, and 13 in the first column, A remainder P obtained by dividing 5, 9, 13, d1 to d3 by the generating polynomial G2 (X) is obtained to generate an (8, 4) expanded Hamming code. In this way, an extended Hamming code is generated for information bits in the first to fourth columns in the column direction of the data portion, and the syndrome is arranged as a second syndrome unit in a matrix of 5 rows and 1 column to 8 rows and 4 columns.

Further, the check bits of the second syndrome part are regarded as information bits, an (8, 4) expanded Hamming code is generated, and arranged as a third syndrome part in the matrix of the syndrome 5 rows 5 columns to 8 rows 8 columns. To do.
The product code configured on the transmission side in this way is sequentially transmitted in the row direction from the information bit of the data portion of 1 row and 1 column, for example.

  FIG. 4 is an outline of a communication system to which the present invention is applied. Data output from a terminal device at a transmission end is encoded into a product code shown in FIG. 3 by an encoding unit of an encoding / decoding unit, and a modem. Are sequentially output to the transmission line. The receiving end decodes the received signal received through the modem by the decoding unit of the encoding / decoding unit, corrects the error, and outputs it to the terminal. In the figure, the modem is described as a hard-decision modem, but is not limited to a hard-decision modem.

The encoding process on the transmission end side will be described with reference to FIGS. FIG. 5 shows an encoding apparatus, and FIG. 6 is a flowchart showing its operation.
The input transmission data is converted into a 4-bit digital data string at the input unit of the encoding device, expanded into a data matrix table in units of the four blocks, and expanded Hamming (BCH) code generation based on the data matrix Part generates a first (8,4) BCH code. Similarly, the (8, 4) BCH code is generated by the BCH code generation unit based on the transposed matrix of the data matrix, the 4 × 4 syndrome matrix is extracted, and the transposed matrix is generated. This coincides with the second syndrome part.
The second syndrome part bit (check bit) is regarded as an information bit, and the (8, 4) BCH code is similarly generated. This is the second (8,4) BCH code, and the syndrome becomes the third syndrome part.
The first and second (8,4) BCH codes are combined to form a product code according to the present invention. The output unit sequentially reads and outputs the code string of the product code matrix.

The error correction in the decoding process at the receiving end by the product code will be described based on FIGS. 7 (A) to (G) and FIGS. 8 (A) to (C). At the receiving end, the received signal in units of 4 blocks is expanded into a matrix table of 8 rows and 8 columns, and a product code similar to that at the transmitting end is formed. 7A to 7G, the matrix is constituted by the same reference numerals as those in FIG. 3, but the reference numerals are omitted except for (A) in the figure.
Here, for example, as shown in FIG. 7 (A), it is assumed that an error has occurred in the code at the location marked with a cross.

As a procedure (1) of decoding (error test / correction), error test is performed on the code strings of 1 to 4 columns in the illustrated column direction. This code string corresponds to the (8,4) BCH code generated based on the code string in the column direction of the 4-block data matrix.
As shown in FIG. 7B, a 1-bit error is set in the first column where an error is detected, and a 1-bit error flag is set in the third column. In the third column, an error has actually occurred in 3 bits, but as described above, a 1-bit error flag is set because the (8, 4) BCH code is detected as a 1-bit error.

As procedure 2, an error test is performed for the 1 to 8 rows shown in the figure, that is, the 8 code columns in the direction of the code string of the data matrix, to correct a 1-bit error that can identify the error location, and to perform error detection / correction. Do.
In the illustrated case, a 2-bit error is detected in the first, third, and seventh lines, and a 2-bit error flag is set. Although an error has occurred in 3 bits in the second row, it is detected as a 1-bit error in the second row and the fourth column, and the corresponding portion is corrected.
Here, if an error has occurred in the second row and the fourth column, the error should be detected by the error test in the column direction in the procedure 1 described above. However, the error flag is not set in the fourth column in step 1 as shown in FIG. That is, it is detected that the second line in the procedure 2 is not a 1-bit error but a 3-bit error, and a 3-bit error flag is set.

In the procedure 3, the error test in the column direction of the procedure 1 is performed again for the 1st to 4th columns with respect to the result of the procedure 2 shown in FIG. 7C. If a 1-bit error is detected, the error correction is performed.
As shown in the figure, 1-bit error in 1 column where 1-bit error is detected is corrected, and an error correction flag is set in the 1st column.
Since 3 bit error is erroneously detected as 1 bit error in 3 columns, erroneously detected 3 column 6 row is erroneously corrected. Since the error flag is not set, it is detected that the third column is not a 1-bit error but a 3-bit error, and a 3-bit error flag is set. The result is as shown in FIG. In the figure, the error-corrected portion is indicated by a circle.

When the results corrected in steps 2 and 3 are arranged, the result is as shown in FIG.
In step 4, for the result corrected in step 2 and step 3 shown in FIG. 7E, the intersection of the row and column in which the 2-bit and 3-bit error flags are set in the row and column is obtained. Correct the bit.
At this time, if there is no intersection of the row or column for which the error flag is set, the intersection with the row or column for which the error correction is set is obtained. This is because the corrected row / column is the row / column in which the error was detected. Further, when the intersection point is an error correction point in the procedures 2 and 3, no correction is made. This is because it is correct correction based on 1-bit error detection. In the illustrated example, these conditions are not met.
As a result, the error in the third column, first row, third column, third row, and third column, seventh row at the intersection is corrected. However, the intersection of the second row and the third column in which no error has occurred is also corrected, and is erroneously corrected as indicated by a Δ mark in FIG.

In step 5, the error correction in the column direction of steps 1 to 4 in step 3 is performed again on the result corrected in step 4 shown in FIG. 7F to correct a portion where a 1-bit error is detected. In the example shown in the figure, in the third column test, the erroneously corrected 1-bit error in the third column and the second row of the Δ mark position erroneously corrected in the procedure 4 is detected and corrected correctly. If a 2-bit error is detected, repeat steps 2-4. The number of repetitions is arbitrarily determined, but if the error is not resolved, the process is terminated as a correction failure, and a different method is used.
In the example shown in the figure, since a 2-bit error is not detected as shown in FIG. 7 (G), error correction is completed without repeated verification.

In the above processing process, if no error is detected in any column or row in both the procedure 1 and procedure 2, it is obvious that the error can be determined in the received signal data and the process can be terminated. It is.
Further, in the verification of the procedure 3, when the error detection in the column direction is only 1-bit error and the total number is smaller than the number of error bits detected in the procedure 1, or the same number as the same 1-bit error detection number. If there is, the processing is terminated assuming that the error has been corrected.
This is because the location (code) where an error is detected in the procedure 1 is also detected in the procedure 2, and if it corresponds to a 1-bit error in the row direction, it is corrected in the procedure 2. That is, no error is detected in procedure 3 for the corresponding sequence of codes in which a 1-bit error is detected in procedure 1 and procedure 2. Further, if the code at one position of the column where the 2-bit error is detected in the procedure 1 is corrected if the 1-bit error detection position in the row direction is detected in the procedure 2, the 1-bit error is detected in the corresponding column in the procedure 3. Therefore, if a 2-bit or 3-bit string is not detected, it can be determined that the correction has been completed.
FIGS. 8A to 8C are charts describing the above error correction processing flow.

FIG. 9 is a diagram illustrating an example of a composite device in the encoding / decoding unit in FIG.
FIG. 9 is a diagram illustrating an example of a decoding device. The receiving unit 5 expands the 8 × 8-bit BCH code extracted from the received signal into an 8 × 8 product code matrix table, and generates a product code as exemplified in FIG. 3, for example.
The error correction unit 6 detects and corrects an error in the code string developed in the product code matrix table. The error correction unit 6 includes a code error verification unit 61, a flag setting unit 62, a correction unit 63, a correction table generation unit 64, and a determination unit 65.

The error test section 61 performs error tests on the code strings of the expanded product codes in the procedures 1 to 3 and procedure 5. The flag setting unit 62 sets a flag of the detected error in the detected code string when the error verification unit 61 detects an error, and sets an error correction flag when the error is corrected by the correction unit.
The correction unit 63 corrects the detected 1-bit error and corrects the sign of the intersection of the procedure 4.

The correction table generation unit 64 develops a result corrected in the error detection / correction process in steps 2 to 4 in a table. It is obvious that the correction result can be developed using the table of the receiving unit 1 as well.
The determination unit 65 determines the end of the error correction process as described above in the procedure 2, the procedure 3, and the procedure 5. The output unit 7 extracts and outputs data based on the process end determination of the determination unit.

As described above, the present invention achieves not only 2-bit error correction but also 3-bit error correction with a simple system configuration. Also in this process, the BCH code generation process and the error test process can be performed easily / at high speed by referring to, for example, the (8, 4) BCH code table shown in the table of FIG.
INDUSTRIAL APPLICABILITY The present invention is suitable for transmission of power system operation information corresponding to, for example, a rural area where a relatively small amount of data is required on a transmission line in which an error may occur but high transmission quality is required. is there.

DESCRIPTION OF SYMBOLS 1 ... Input part, 2 (8, 4) ... Extended hamming code generation part, 3 ... Product code generation part, 4 ... Output part, 5, Reception part, 6 ... Error correction part, 61 ... Error test part, 62 ... Flag Setting unit 63... Correction unit 64. Correction table generation unit 65 65 determination unit 7 output unit

The present invention relates to an encoding / decoding system capable of error correction using a Hamming code and a product code, and particularly applied to information transmission for operating a power system, and a code error caused by noise generated on a transmission line. The present invention relates to an encoding / decoding method that can be corrected.

The present invention has been made in view of the above circumstances, and applies a product code system to (8, 4) extended Hamming code, and can be applied to a narrowband transmission path. Error detection and error correction / correction is possible even if the number of iterations is small. For example, for random bit errors due to thermal noise and continuous bit errors due to burst noise due to electrical noise or lightning noise. The present invention also provides a high-speed and simple error correction method that enables error correction and an encoding / decoding method that enables error detection.

The first technical means is an error correction method for performing error correction on a transmission code encoded and transmitted in a predetermined procedure. In the predetermined procedure, a 4-bit data generated based on input data is transmitted. A first (8,4) expanded Hamming code is generated based on a 4 × 4 data matrix for every 4 blocks of digital data, and a (8,4) expanded is generated based on the transposed matrix of the data matrix Based on the transposed matrix of the syndrome part of the Hamming code, a second (8,4) expanded Hamming code is generated, and the generated first (8,4) expanded Hamming code and the second (8,4) are generated. ) Combining extended Hamming codes to generate a product code of 8 rows and 8 columns, sequentially reading out the codes of the generated rows or columns of the product codes as the transmission codes, and the error correction method uses the predetermined procedure reduction, transmitted the transmission codes sequentially Generating a product code matrix disposed in eight rows and eight columns of a matrix table, as step 1, performs first error test per column for four columns code string containing the data symbols in the product code matrix, one-bit error set 1 bit error flag code string of the detected column, 2 to set the 2 bit error flag bit error in the code string of the detected column, the step 2, reference numeral 8 rows corresponding to the product code matrix performs error test for each row the columns, 2 sets of 2-bit error flag bit error in the code column in the row detected in the case of detecting, detects the 1-bit error, the test of the detected error code Step 1 in setting the error correction flag to correct the error in the code sequence of the row if it belongs to a code string sequence being set error flag, the detected error code is set an error detection flag in step 1 in the case and not those Set 3 bit error flag in the code string of the line without correcting the error, as step 3, to reflect the result of the error test procedure 2 for the code string of four columns were subject to error test procedure 1 The second error test is performed for each column , and if 1-bit error is detected, the error location is corrected and an error correction flag is set, or a 3-bit error flag is set and 2-bit If an error is detected to set the 2 bit error flag, a step 4, reflecting the result of the error test procedure 3 for the product code matrix, either 2-bit error flag or 3 bit error flag is set The intersection of the row and column code strings is obtained, and when the intersection is not error-corrected, the intersection point is corrected. As a procedure 5 , the procedure 4 is performed for the four sequences of code sequences subjected to the error test in the procedure 1. Reflects the result of correction To perform third time error test for each column, if an error is detected, repeat steps 1 through Step 4, characterized by the Turkey to end the process if no error is detected.

A second technical means is Oite the first technique hand stage, in step 4, if the intersection of two-bit error flag or 3 bit error rows and columns of code sequence either is set flags no error It is characterized in that an intersection point with a code string in which a correction flag is set is obtained.

A third technical means is Oite the first technique hand stage, if the error in the error test procedure 1 and procedure 2 is not detected, characterized in that the process ends by omitting the subsequent steps .

A fourth technical means is Oite the first technique hand stage, in Step 3, only correct one bit error is detected, and the total number of error bits total number of correction bits is detected in step 1 good Ri decreases and that the field Gomata If Ru as many der 1-bit errors detected in Step 1, characterized in that the process ends by omitting the subsequent steps.

A fifth technical means, Ru decoding method der for extracting and outputting data from the corrected code by any one of the error correction method of the technical means of the first to fourth.

A sixth technical means is a decoding device that receives a transmission code encoded and transmitted in a predetermined procedure, performs error correction, and outputs data, wherein the predetermined procedure is generated based on input data A first (8,4) expanded Hamming code is generated based on a 4-by-4 data matrix for every 4 blocks of the 4-bit digital data, and is generated based on the transpose matrix of the data matrix ( The second (8,4) expanded Hamming code is generated based on the transposed matrix of the syndrome part of the 8,4) expanded Hamming code, and the generated first (8,4) expanded Hamming code and the second The (8, 4) extended Hamming codes of the above are combined to generate a product code of 8 rows and 8 columns, and the code of the generated row or column of the product codes is sequentially read out as the transmission code, and the decoding device Encoded and transmitted in the procedure of A receiving unit for generating a product code matrix arranged in a matrix table of sequential 8 rows and 8 columns receives the signal codes, errors that Rio erroneous correction for the product code matrix of the matrix table according to a predetermined error correction procedure A correction unit; and an output unit that extracts and outputs data corrected by the error correction unit. In the predetermined error correction procedure, as procedure 1, four columns including the data code in the product code matrix are provided. The first error test is performed for each code string, and a 1-bit error flag is set for the code string of the string where the 1-bit error is detected, and a 2-bit error flag is set for the code string of the string where the 2-bit error is detected As a procedure 2, an error test is performed for each of the 8 code strings corresponding to the product code matrix, and when a 2-bit error is detected, a 2-bit error flag is set in the detected code string. Bit error If the detected error code belongs to the code string of the column for which the error flag is set in the test of the procedure 1, the error is corrected and the error correction flag is set in the code string of the row and detected. If the error detection flag is not set in step 1 and the error detection flag is not set, a 3-bit error flag is set in the code string of the row without correcting the error. The second error test is performed for each column to reflect the result of the error test in step 2 for the four code strings, and if a 1-bit error is detected as in step 2, the error part is corrected. An error correction flag is set, or a 3-bit error flag is set. If a 2-bit error is detected, a 2-bit error flag is set. As step 4, the result of the error test in step 3 is obtained for the product code matrix. Reflected, 2-bit error file Find the intersection of the code string of the row and column in which either the lag or the 3-bit error flag is set, and correct the intersection if the intersection is not error-corrected. The third error test is performed for each column reflecting the correction result of step 4 for the four code strings subject to the above, and if an error is detected, steps 1 to 4 are repeated to detect the error. If not, the process is terminated .

The seventh technical means is a program for causing a computer to execute any one of the first to fifth technical means.

According to the present invention, an encoding / decoding system capable of correcting an error of 3 bits as well as 2 bits can be constructed with a simple system configuration.

FIG. 3 shows the configuration of the product code used in the present invention. Four blocks (8, 4) expanded Hamming codes including data parts 1 to 4, 5 to 8, 9 to 12, and 13 to 16 are arranged in 1 to 4 rows, respectively. A matrix of 1 row 1 column to 4 rows 4 columns is a data portion, and a matrix of 1 row 5 columns to 4 rows 8 columns is a first syndrome portion for the data portion.
Next, with respect to the column directions 1 to 4 corresponding to the transposed matrix of the data part, the remainders d1 to d3 obtained by dividing the information bits of the first column 1, 5, 9, 13 by the generator polynomial G1 (X) , 1 A remainder P obtained by dividing 5, 9, 13, d1 to d3 by the generating polynomial G2 (X) is obtained, and an (8, 4) expanded Hamming code is generated. In this way, an extended Hamming code is generated for information bits in the first to fourth columns in the column direction of the data portion, and the syndrome is arranged as a second syndrome unit in a matrix of 5 rows and 1 column to 8 rows and 4 columns.

As Step 2, the row direction of the 1-8 line shown, that is, the 8 marks No. column direction code string data of the data matrix performs error test, error detection / correction and correcting single bit errors can be specified error location To do.
In the illustrated case, a 2-bit error is detected in the first, third, and seventh lines, and a 2-bit error flag is set. Although an error has occurred in 3 bits in the second row, it is detected as a 1-bit error in the second row and the fourth column, and the corresponding portion is corrected.
Here, if an error has occurred in the second row and the fourth column, the error should be detected by the error test in the column direction in the procedure 1 described above. However, the error flag is not set in the fourth column in step 1 as shown in FIG. That is, it is detected that the second line in the procedure 2 is not a 1-bit error but a 3-bit error, and a 3-bit error flag is set.

Figure 9 is a diagram showing an example of a decrypt unit that put the coding / decoding unit in FIG. The receiving unit 5 expands the 8 × 8-bit BCH code extracted from the received signal into an 8 × 8 product code matrix table, and generates a product code as exemplified in FIG. 3, for example.
The error correction unit 6 detects and corrects an error in the code string developed in the product code matrix table. The error correction unit 6 includes a code error verification unit 61, a flag setting unit 62, a correction unit 63, a correction table generation unit 64, and a determination unit 65.

Claims (9)

Generating a first (8,4) expanded Hamming code based on a 4-by-4 data matrix for every 4 blocks of 4-bit digital data generated based on the input data;
Generating a second (8,4) expanded Hamming code based on the transposed matrix of the syndrome part of the (8,4) expanded Hamming code generated based on the transposed matrix of the data matrix;
The generated first (8,4) expanded Hamming code and the second (8,4) expanded Hamming code are combined to generate a product code of 8 rows and 8 columns, and a row or column code of the generated product code Are sequentially read out as transmission codes. (8, 4) expanded Hamming code blocks encoded and transmitted by the encoding method according to claim 1 are sequentially arranged in a matrix table of 8 rows and 8 columns to generate a product code matrix;
As a procedure 1, the first error test is performed on four code strings including data codes in the column direction of the four data code strings of the data matrix in the product code, and the code string in which the 1-bit error or 2-bit error is detected Set the error detection flag
As procedure 2, error test is performed on 8 code strings in the code string direction of the data corresponding to the data matrix, a 2-bit error flag is set in the code string in which 2-bit error is detected, and 1-bit error is detected and detected. If the error code belongs to a code string for which an error flag is set in the test of the procedure 1, the error is corrected and an error correction flag is set in the code string. The error detection flag is set in the procedure 1 If not, set the 3-bit error flag in the code string without correction,
Reflecting the error test of procedure 2 as procedure 3, the second error test is performed on the code string verified in procedure 1, and if a 1-bit error is detected as in procedure 2, the error part is corrected and the error correction flag is set. Set or set a 3-bit error flag and if a 2-bit error is detected, set an error 2-bit error flag,
For the product code matrix of 8 rows and 8 columns reflecting the error test of procedure 3 as procedure 4, the intersection of the code string of the row and column in which the 2-bit or 3-bit error flag is set is obtained, and the intersection is not error-corrected In that case, correct the intersection
As the procedure 5, the third error test is performed on the code string verified in the procedure 1 reflecting the correction of the procedure 4, and if an error is detected, the procedure 1 to the procedure 4 are repeated, and if no error is detected, the process is performed. A method for correcting an error of a code, comprising: ending the process.   3. The error correction method according to claim 2, wherein, in step 4, when there is no intersection between a row and a column in which an error flag is set, an error with respect to a code string in which the error correction flag is set is obtained. Correction method.   3. The error correction method according to claim 2, wherein if no error is detected by the error test of the procedure 1 and the procedure 2, the subsequent procedure is omitted and the process is terminated.   3. The error correction method according to claim 2, wherein only one-bit error correction is detected in step 3, and the total number of correction bits is less than the total number of error bits detected in the first procedure. Or an error correction method characterized in that if the number is the same as the number of detected 1-bit errors, the subsequent procedure is omitted and the process is terminated.   6. A decoding method, wherein data is extracted from the code corrected by the error correction method according to claim 2 and output. An input unit that expands transmission data in which 4-bit data is input in units of 4 blocks into a data matrix table of 4 rows and 4 columns, and outputs the data matrix and its transposed matrix;
A first (8, 4) expanded Hamming code is generated based on the data matrix, and further, an (8, 4) expanded Hamming code is generated based on the transposed matrix, and extracted from the generated expanded Hamming code A second (8, 4) expanded Hamming code that generates a second (8, 4) expanded Hamming code based on the transposed matrix of the syndrome matrix;
A product code generator for combining the generated first and second (8,4) expanded Hamming codes to generate a product code matrix of 8 rows and 8 columns;
An encoding device comprising: an output unit that sequentially reads out a code string of the product code matrix and uses it as a transmission code. A receiving unit that expands the code encoded by the encoding method of claim 1 into a matrix table of 8 rows and 8 columns, and an error test is performed on the code string of the matrix table, and a code string in which an error is detected is detected. An error correction unit that sets an error detection flag and corrects a code in which an error is detected, and an output unit that extracts error-corrected data,
The error correction unit includes an error verification unit, a flag setting unit, a correction unit, a correction table generation unit, a determination unit,
The error verification unit performs the error test of steps 1 to 3 and 5 for the product code expanded in the table, and the flag setting unit sets an error flag in the code string detected by the test and The error correction flag is set in the code string corrected in step S3, the correction unit corrects the 1-bit error detected in steps 2, 3, and 5, and the sign of the intersection of the row and column that has been subjected to the error test in step 4 is set. The decoding apparatus corrects, the determination unit performs the error correction end determination in the procedures 2, 3, and 5, and the output unit extracts and outputs data based on the end determination of the determination unit. .   The program for making a computer perform the method in any one of Claims 1-6.

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