JPH0799445A - Phase locked loop circuit, one-shot pulse generating circuit and signal processor - Google Patents

Abstract

PURPOSE:To provide a phase locked loop circuit from which can obtain a signal of a desired oscillating frequency without being affected by dispersion in manufacture or the like, the one-shot circuit from which can obtain a one-shot pulse of a desired with over a wide range and to provide a signal processing unit including them. CONSTITUTION:The 1st (2nd) phase locked loop circuit 100(120) is provided with a variable frequency oscillation circuit 104(110) of the same configuration and an operating point conversion circuit 105 makes the conversion of an operating point, its output Vg is fed to an adder circuit 109, and an oscillating frequency from the variable frequency oscillation circuit 110 is controlled by an output Vf2 of the adder circuit 109. Furthermore, the output Vf2 is inputted to an IN terminal of a variable frequency oscillation circuit 155 of the one-shot circuit 150, and the pulse width of the one-shot pulse is decided by the Vf2 and the count (m) of an edge detection circuit 161. The one-shot pulse OS is inputted to a 3rd phase locked loop circuit 160, from which a SYCLK and a SYDT are obtained via a data normalization circuit 170.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit, a one-shot pulse generation circuit, and a signal processing device including these phase synchronization circuit and one-shot pulse generation circuit.

[0002]

2. Description of the Related Art Conventionally, in zone bit recording for an information storage medium such as a hard disk and a magneto-optical disk, the frequency of a data write clock changes for each zone including a plurality of tracks. For example,
In zone bit recording of 4 zones, f1
= 8 MHz, f2 = 10 MHz, f3 = 12 MHz, f
The frequency of the data write clock changes as 4 = 14 MHz. In zone bit recording, by changing the frequency of the write clock in this way, the data storage densities in the outermost zone and the innermost zone can be made approximately the same, and the storage capacity of the information storage medium can be increased. It is possible to increase. When data is read from the information storage medium on which the writing process has been performed by such zone bit recording, the data transfer rate of the read data also corresponds to the write clock frequency of each zone. It becomes a rate. Therefore, for an apparatus that records on or reproduces from such an information storage medium, it is necessary to generate a clock corresponding to the frequency of each zone and read at a transfer rate corresponding to the frequency of each zone. It is required to reproduce the data that is recorded.

For example, in the phase locked loop circuit shown in FIG.
A signal obtained by multiplying the reference frequency fm from the reference frequency source 301 by 1 / M and a signal obtained by multiplying the write clock frequency fw by 1 / N are input to the phase comparator 307, and the phases are compared (M and N are: Natural number). Then, a DC voltage corresponding to the phase comparison difference is output from the filter circuit 308 to the variable frequency oscillation circuit 309, and the oscillation frequency is controlled. With this configuration, it is possible to generate a clock having a frequency of fw = fm × (N / M), and it is possible to generate a clock corresponding to each zone.

Further, for example, Japanese Patent Laid-Open No. 59-28209 discloses a two-stage phase locked loop circuit. In this conventional technique, a first phase-locked circuit and a second phase-locked circuit including a voltage-controlled variable frequency oscillation circuit having the same voltage / frequency conversion coefficient are prepared. Then, the first phase locked loop is synchronized with the reference frequency, and the control voltage of the oscillation circuit within the first phase locked loop is directly added to the control input of the oscillation circuit within the second phase locked loop. This allows the second
The free-running frequency of the phase-locked loop circuit becomes equal to the oscillation frequency of the oscillator circuit in the first phase-locked loop circuit. According to this conventional technique, if the reference frequency is stable, the free-running oscillation frequency of the second phase locked loop is not affected by manufacturing variations, power supply voltage fluctuations, ambient temperature changes, and the like. Therefore, it is possible to realize a highly accurate and stable phase locked loop without adjustment. The conventional phase-locked loop circuit has been widely used because it is very effective in equalizing the oscillation frequencies of the oscillation circuits in the plurality of phase-locked loop circuits.

Further, when reading the data stored in the information storage medium, the pulse width of the read data is not constant. Therefore, a circuit called a one-shot pulse generation circuit is required to generate a pulse having a constant width from the read data (hereinafter, simply referred to as a one-shot circuit).

FIG. 23 shows an example of a conventional one-shot circuit. In this one-shot circuit, first, the input detection circuit 351 detects the rising edge of the input signal input to the input terminal 353. The output of the input detection circuit 351 is delayed by the delay circuit 355 for a certain period of time, and the output 352 of the delay circuit 355 is input to the reset terminal of the input detection circuit 351. This allows
A one-shot pulse will be generated at the output terminal 354 of the input detection circuit 351.

The one-shot circuit shown in FIG. 23 is further provided with a phase synchronization circuit 359. A variable frequency oscillation circuit (ring oscillator) 360 having the same structure as that of the delay circuit 355 except that it is ring-connected is provided in the phase locked loop circuit 359. In addition, the delay circuit 355
A common oscillation control signal is input to the delay control terminal and the oscillation control terminal of the variable frequency oscillation circuit 360. Thereby, the delay time of the delay circuit 355 can be determined based on the reference frequency.

In this one-shot circuit, the variable frequency oscillating circuit 360 has the same structure as the delay circuit 355 except that it is connected in a ring. Therefore, even if there are manufacturing variations, power supply voltage fluctuations, and ambient temperature changes, delays will occur. Circuit 3
The delay time of 55 is always error-corrected by the common oscillation control signal. This makes it possible to obtain a highly stable and highly accurate one-shot pulse.

This is a very effective technique when the desired one-shot pulse width and the oscillation cycle time of the variable frequency oscillation circuit 360 are relatively close and the reference frequency is fixed. It has been used in one-shot circuits and the like.

Incidentally, the conventional one-shot circuit is a monostable one-shot multivibrator circuit as disclosed in Japanese Patent Laid-Open No. Sho 61-61.
-87416 and described in detail.

[0011]

However, first, referring to FIG.
The phase locked loop circuit having the configuration shown in (1) has the following problems. For example, the variable range of the clock frequency is 10MHz
Consider the case of -40 MHz. In this case, the voltage range in which the output Vf of the filter circuit 308 swings is finite,
In the case of a single 5V power source, the voltage is, for example, 1V to 4V. Then, the variable frequency oscillation circuit 309 is required to have a performance capable of changing the oscillation frequency by at least 10 MHz with respect to a change in Vf of 1V. Furthermore, when manufacturing variations, power supply voltage fluctuations, ambient temperature changes, etc. are taken into consideration, performance that is 2 to 3 times this, that is, performance that the oscillation frequency can be changed by 20 MHz to 30 MHz with respect to a change of 1 V of Vf is required. Will be done. However, in this way, the oscillation frequency-to-oscillation frequency proportionality coefficient (or oscillation frequency-to-oscillation frequency proportionality coefficient) of the variable frequency oscillation circuit 309 is
If too large, then the variable frequency oscillator circuit 30
Due to the presence of noise or the like, the state in which the lock state of the phase synchronization is easily released, the state in which the lock state 9 is mislocked, or the jitter is increased occurs. Therefore, in the phase locked loop circuit shown in FIG. 22, there is a problem that the variable range of the write clock cannot be made too large due to the restriction that the proportional coefficient cannot be made too large and the voltage range in which the output of the filter circuit swings is finite. there were.

Further, the two-stage phase locked loop circuit disclosed in Japanese Patent Laid-Open No. 59-28209 has the following problems. That is, in this phase locked loop, the zone bit
If the oscillation frequency required for recording or the like is different from the oscillation frequency in the phase-locked loop that is synchronized with the reference frequency, even if you try to use this conventional phase-locked loop, it is impossible due to its operating principle. There was a problem. This is because oscillating circuits having different oscillating frequencies have different oscillating control voltages, so that the oscillating control terminals cannot be connected to each other.

In the conventional one-shot circuit shown in FIG. 23, the required one-shot pulse width is very long with respect to the oscillation cycle of the variable frequency oscillation circuit 360, or the reference frequency must be changed in a wide range. When it was necessary, there were the following problems.

That is, in the conventional one-shot circuit, the width of the desired one-shot pulse is set by the delay time of the inverter in the delay circuit 355. Therefore, in order to obtain a long one-shot pulse width, it is necessary to increase the number of delay inverter stages. This means that a large area is occupied in mounting by that amount, which causes problems such as an increase in chip area and an increase in cost. Further, the delay circuit 355 and the variable frequency oscillation circuit 360 in the phase locked loop circuit are similar in structure but essentially different in function and characteristic. Therefore, even if a common oscillation control signal is input to the delay control terminal of the delay circuit 355 and the oscillation control terminal of the variable frequency oscillation circuit 360, the delay time of the inverter in the variable frequency oscillation circuit 360 and the inverter in the delay circuit 355 Is not exactly equal to the delay time of. In particular, when it was attempted to control the delay time in a wide range by changing the reference frequency, it was impossible to make both delay times equal over the entire range.

When the relationship between the oscillation frequency of the variable frequency oscillation circuit 360 and the delay amount of the delay circuit is to be changed, the delay characteristic of the delay circuit must be changed because the oscillation control signal is commonly used. However, this causes a problem that the variable frequency oscillation circuit 360 and the delay circuit 355 lose their identity and the error becomes larger.

The present invention has been made in order to solve the above-mentioned problems, and its purpose is not to be affected by manufacturing variations, power supply voltage fluctuations, ambient temperature changes, etc. An object of the present invention is to provide a phase locked loop circuit capable of obtaining a signal having a desired oscillation frequency different from the frequency and a signal processing device including the phase locked loop circuit.

Another object of the present invention is to provide a one-shot circuit capable of obtaining a one-shot pulse having a desired width in a wide range while suppressing an increase in occupied area, and a signal processing device including the one-shot circuit. It is in.

[0018]

In order to solve the above-mentioned problems, the invention of claim 1 provides a first phase synchronizing means for synchronizing with a reference frequency signal and a second phase synchronizing means for synchronizing with an input signal. A first phase comparison means for performing a phase comparison for synchronizing the reference frequency signal with the first phase synchronization means, the first phase comparison means comprising: First filter means connected to the phase comparison means to generate a first oscillation control signal, and a first variable frequency oscillation whose oscillation frequency is controlled based on a current or a voltage set by the first oscillation control signal. Means, the operating point converting means includes a current or voltage n set by the first oscillation control signal based on the first oscillation control signal.
Second phase comparison means for generating an operating point conversion signal capable of setting a double current or voltage, and the second phase synchronization means for performing phase comparison for synchronizing with the input signal; and the second phase comparison means.
Second filter means connected to the phase comparison means, and the operating point conversion signal and the output of the second filter means are input to the first and second addition input terminals to be added by current addition or voltage addition. It is characterized by including an adding means for generating the second oscillation control signal and a second variable frequency oscillating means for controlling the oscillation frequency based on the current or the voltage set by the second oscillation control signal.

According to the first aspect of the invention, the first phase synchronization means is synchronized with the reference frequency, and the first oscillation control signal which is the output of the filter means at the time of this synchronization is output to the operating point conversion means. It Then, in the operating point conversion means, n times (n times the current or voltage set by the first oscillation control signal (n
Is a real number) and an operating point conversion signal capable of setting a current or voltage is generated. That is, this operating point conversion signal is a signal that can set the oscillation frequency of the variable frequency oscillation means to n times. Then, the operating point conversion signal and the output of the second filter means are input to the first and second addition input terminals of the addition means, and the second oscillation control signal is generated by current addition or voltage addition. Then, the oscillation of the second variable frequency oscillation means is controlled by the second oscillation control signal. As a result, the second phase synchronization means is operated, for example, at the reference frequency n.
It becomes possible to synchronize with an input signal having a frequency that is approximately double or n times the reference frequency.

The invention of claim 2 is characterized in that, in claim 1, the operating point converting means includes means capable of arbitrarily controlling the magnification n.

According to the second aspect of the present invention, the control means enables control in which the value of the magnification n in the operating point conversion means is arbitrary. That is, this control means makes it possible to control the current or voltage that can be set by the operating point conversion signal to be n times. As a result, it becomes possible to control the central oscillation frequency of the second variable frequency oscillation means to an arbitrary value.

According to a third aspect of the invention, input detecting means for detecting the presence or absence of an input signal, oscillation control means, first variable frequency oscillating means, edge detecting means, and the first variable frequency oscillating means. Means for synchronizing with the reference frequency signal and having a second variable frequency oscillating means having the same structure as the means, a one-shot pulse is output from the oscillation control means or the first variable frequency oscillating means. A one-shot pulse generating circuit which is generated at an output terminal, wherein the edge detecting means outputs a detection signal after counting a rising edge or a falling edge of the output signal of the first variable frequency oscillating means by a natural number m times. Then, the oscillation control means outputs an oscillation start signal to the first variable frequency oscillation means when the input signal is detected by the input detection means to detect the edge. When the detection signal is input from the stage, an oscillation stop signal is output to the first variable frequency oscillation means, and the first variable frequency oscillation means has an oscillation start / stop control terminal and an oscillation frequency control terminal, When the oscillation start signal is input to the oscillation start / stop control terminal, oscillation is started, and the frequency of the oscillation is controlled based on the oscillation control signal of the second variable frequency oscillating means input to the oscillation frequency control terminal. When the oscillation stop signal is input to the oscillation start / stop control terminal, the oscillation is stopped.

According to the invention of claim 3, when the input signal is detected by the input detecting means, the first variable frequency oscillating means starts oscillating under the control of the oscillation controlling means. Since the oscillation frequency is controlled based on the signal that controls the oscillation of the second variable frequency oscillation means, the oscillation frequency becomes equal to the reference frequency. Next, the falling edge or the rising edge of this oscillation output is counted by the edge detecting means, and the detection signal is output after counting the edge m times. Then, when the detection signal is output, the oscillation is stopped by the control of the oscillation control means. From the above,
It is possible to output a one-shot pulse having a width determined by the reference frequency and the count m. When the count m is 1, the function of the edge detecting means may also function as the input detecting means, or the output of the first variable frequency control means may be a one-shot pulse output.

The invention according to claim 4 is based on claim 3, wherein a current or a voltage which is k times the current or voltage set by the oscillation control signal based on the oscillation control signal of the second variable frequency oscillating means. The operating point conversion means for generating an operating point conversion signal that can be set and outputting it to the oscillation frequency control terminal of the first variable frequency oscillating means is included.

According to the invention of claim 4, the oscillation frequency of the first variable frequency oscillating means is k times the reference frequency or k.
It is possible to set the width of the one-shot pulse to k times the resolution when setting the width of the one-shot pulse.

The invention of claim 5 is characterized in that, in claim 4, the operating point converting means includes means for arbitrarily controlling the magnification k.

According to the fifth aspect of the present invention, the control means enables control in which the value of the magnification k in the operating point conversion means is arbitrary. This allows control to set the width of the one-shot pulse to any resolution.

The invention of claim 6 is the same as claims 3 to 5.
In any one of the above, the window center is adjusted by adjusting the width of the one-shot pulse by the count m or the count m and the magnification k.

According to the sixth aspect of the invention, the window center can be adjusted by adjusting the width of the one-shot pulse by the count m or the count m and the magnification k. That is, for example, by increasing the width of the one-shot pulse, the window margin on the + side can be increased,
It is possible to shift the center of the window to the + side. Further, for example, by shortening the width of the one-shot pulse, it is possible to increase the − side window margin,
It is possible to shift the center of the window to the-side.

The invention according to claim 7 is characterized in that the first phase synchronizing means is synchronized with the reference frequency signal, the second phase synchronizing means is synchronized with the clock signal set based on the reference frequency signal, and 1 operating point conversion means, one-shot pulse generation means having an input detection means and an oscillation control means for detecting the presence / absence of read data from an information medium, a fourth variable frequency oscillation means and an edge detection means, and a data separator A first phase comparison means for performing a phase comparison for synchronizing with the reference frequency signal, the first phase comparison means comprising: First filtering means connected to the phase comparing means for generating the first oscillation control signal, and the oscillation frequency is controlled based on the current or voltage set by the first oscillation control signal. And a first variable frequency oscillation means,
A first operating point at which the first operating point conversion means can set a current or voltage n times as large as the current or voltage set by the first oscillation control signal based on the first oscillation control signal. Second phase comparison means for generating a conversion signal, the second phase synchronization means performing phase comparison for synchronizing with the clock signal, and second phase comparison means connected to the second phase comparison means.
Filter means, the first operating point conversion signal, and the second operating point conversion signal.
The output of the filter means is input to the first and second addition input terminals to generate a second oscillation control signal by current addition or voltage addition, and a current set by the second oscillation control signal. Or a second variable frequency oscillating means whose oscillation frequency is controlled based on a voltage, wherein the edge detecting means included in the one-shot pulse generating means has a rising edge of an output signal of the fourth variable frequency oscillating means. Alternatively, a detection signal is output after counting the falling edges by a natural number m times, and the oscillation control means included in the one-shot pulse generation means outputs an oscillation start signal when the read data is detected by the input detection means. Fourth
Output to the variable frequency oscillating means, and when the detection signal is input from the edge detecting means, an oscillation stop signal is output to the fourth
Output to the variable frequency oscillating means, and the fourth variable frequency oscillating means included in the one-shot pulse generating means has an oscillation start / stop control terminal and an oscillation frequency control terminal,
The second oscillation control of the second variable frequency oscillation means, which starts oscillation when the oscillation start signal is input to the oscillation start / stop control terminal and the frequency of the oscillation is input to the oscillation frequency control terminal. Signal is controlled based on the signal, and the oscillation is stopped when the oscillation stop signal is input to the oscillation start / stop control terminal, and the third phase synchronization means for the data separator is a one-shot of the one-shot pulse generation means. Third phase comparison means for performing phase comparison for synchronizing with pulse output, third filter means connected to the third phase comparison means, the second oscillation control signal, and the third filter The output of the means is input to the first and second addition input terminals to generate a third oscillation control signal by current addition or voltage addition, and current or current set by the third oscillation control signal. A third variable frequency oscillation means whose oscillation frequency is controlled based on, characterized in that it comprises a data normalization means.

According to the invention of claim 7, the read data is detected by the one-shot pulse generating means, and the one-shot pulse generating means outputs the one-shot pulse having a width determined by the second oscillation control signal and the count m. Is output. In this case, the second oscillation control signal is obtained by operating point conversion of the first oscillation control signal of the first phase synchronization means by the operating point conversion means and performing current addition or voltage addition by the addition means. Therefore, the fourth variable frequency oscillating means oscillates at the same frequency as the second variable frequency oscillating means. The one-shot pulse output from the one-shot pulse generating means is input to the third phase synchronizing means which is a data separator, and the third phase synchronizing means is synchronized with this one-shot pulse. And
The center oscillation frequency of the oscillation in the third variable frequency oscillation means in this case is determined by the second oscillation control signal. The data normalization circuit outputs the read data and the read clock that are normalized based on the one-shot pulse output and the output of the third variable frequency oscillating means. As described above, according to the present invention, it is possible to reproduce the normalized read data and the read clock from the data read from the information storage medium.

The invention according to claim 8 is the invention according to claim 7, wherein the current or voltage set by the second oscillation control signal is set based on the second oscillation control signal of the second variable frequency oscillating means. Second that can set k times the current or voltage
Second operating point converting means for generating the operating point converting signal and outputting it to the oscillation frequency control terminal of the fourth variable frequency oscillating means in the one-shot pulse generating means.

According to the eighth aspect of the invention, the resolution when setting the width of the one-shot pulse can be increased by k times.

The invention of claim 9 is the same as claim 7 or 8
In any one of the above, the first and second operating point conversion means include means capable of arbitrarily controlling the magnifications n and k.

According to the ninth aspect of the invention, it is possible to control the width of the one-shot pulse to any resolution.

The invention according to claim 10 is the window center according to any one of claims 7 to 9, wherein the width of the one-shot pulse output is adjusted by the count m or the count m and the magnification k. It is characterized by performing the adjustment of.

According to the tenth aspect of the invention, the window center can be adjusted by adjusting the width of the one-shot pulse.

[0038]

【Example】

1. First Example A first example described below is an example relating to a phase locked loop circuit. FIG. 1 shows a block diagram of the first embodiment, and FIG. 2 shows a circuit diagram showing details of a circuit forming each block. As shown in FIG. 1, the phase synchronization circuit according to the first embodiment includes first and second phase synchronization circuits 99 and 119 and an operating point conversion circuit 5. The first phase synchronization circuit 99 receives the reference frequency signal 1 as an input, and includes the phase comparator 2, the filter circuit 3, and the variable frequency oscillation circuit 4. The second phase locked loop circuit 119 receives the input signal 6 and includes a phase comparator 7, a filter circuit 8, an adder circuit 9, and a variable frequency oscillator circuit 10. Here, the variable frequency oscillating circuit 4 and the variable frequency oscillating circuit 10 have the same configuration and therefore have the same characteristics. FIG. 2 shows an example in which the variable frequency oscillation circuits 4 and 10 are ring oscillators.

Now, it is assumed that the first phase synchronization circuit 99 is stable in synchronization with the reference frequency 1 by the phase frequency pulling operation. At this time, the oscillation control signal Vf1 input to the variable frequency oscillation circuit 4 is also input to the operating point conversion circuit 5. Then, the operating point conversion signal Vg which is the output of the operating point conversion circuit 5 is input to the input terminal IN2 of the adding circuit 9. FIG. 2 shows an example of the configuration of the operating point conversion circuit 5.

Next, the first embodiment will be described in detail with reference to FIG. As shown in FIG. 2, the operating point conversion circuit 5 includes transistors 13, 14, 15, and 16. The operating point conversion operation is performed by changing the current supply capacity ratio of these transistors 13, 14, 15, and 16. Is going. For example, here, the physical dimensions of the transistors 13 and 14 are set to be the same, and the current supply capacities are set equal to each other. The physical dimensions are set so that the current supply capacity of the transistor 16 is n times the current supply capacity of the transistor 15. Suppose you have set it.
Further, the transistor 13 and the variable frequency oscillation circuits 4 and 1
The current supply capacities of the transistors 11 and 30 in 0 are set to be equal to each other. Also, with the transistor 15,
Transistors 12 and 3 in variable frequency oscillators 4 and 10
The current supply capacities of 1 and 1 are set to be equal to each other. Then, since the oscillation control signal Vf1 which is the input of the variable frequency oscillation circuit 4 is input to the gate of the transistor 13, the current flowing in the transistor 15 becomes equal to the current flowing in the transistor 11 in the variable frequency oscillation circuit 4.
It is well known that the oscillation frequency of the variable frequency oscillation circuit (ring oscillator) as shown in FIG. 2 is proportional to the current flowing through the transistor 11. Then, the current flowing through the transistor 13 and the transistor 15
Since the currents flowing through the same are the same, a voltage determined by this current is generated at the gate terminal of the transistor 15. Since the gate terminal of the transistor 15 is connected to the gate terminal of the transistor 16, a current that is n times the current flowing through the transistor 15 will flow through the transistor 16 due to the current mirror operation. And the transistor 16
The current flowing in the transistor 14 and the current flowing in the transistor 14 are equal to each other. The signal Vg will be output. This operating point conversion signal V
In g, the current flowing through the transistor 30 of the variable frequency oscillation circuit 10 can be set to n times.

Here, if the proportional coefficient of the current i flowing through the transistors 11 and 30 of the variable frequency oscillation circuits 4 and 10 to the oscillation frequency f is a, then f is given by the following equation.

F = a × i (1) From the equation (1), the oscillation frequency of the variable frequency oscillation circuit 4 is f
0, if the current flowing through the transistor 11 in the variable frequency oscillation circuit 4 is i0, then f0 is expressed by the following equation.

F0 = a × i0 (2) Therefore, the operating point conversion circuit 5 outputs a voltage which gives n × i0, that is, a voltage which multiplies f0 by n times.

The operating point conversion circuit 5 having the above-mentioned configuration converts the operating point with a very simple circuit configuration as compared with an operating point conversion circuit using a voltage multiplier and a multiplication type D / A converter described later. be able to. Therefore, the operating point conversion circuit 5 having this configuration has a great advantage in that the device can be downsized.

Now, the adder circuit 9, as shown in FIG.
Voltage-current converter 29 and transistors 17, 18, 1
Includes 9 and 20. That is, the adder circuit 9 uses VDD /
A voltage-current converter 29 for converting the input voltage of IN1 into a positive / negative current with reference to 2 is provided. Then, the output current of the voltage-current converter 29 and the current flowing through the transistor 17 determined by the voltage of the operating point conversion signal Vg are added, and the current determined by this addition result is duplicated in the transistor 20 by the current mirror operation. Then, the gate voltage of the transistor 18, which is made up of the duplicated current, is output as the oscillation control signal Vf2.

FIG. 3 shows an example of the configuration of the voltage-current converter 29. This voltage-current converter 29 includes an operational amplifier 23.
, Resistor 28, and transistors 24, 25, 26, 27
Etc. are included. The transistors 24 and 26 have the same current supply capability, and the transistors 25 and 27 also have the same current supply capability. Where the resistor 28
Flows through transistor 24 or transistor 25 to VDD or ground. And
Since negative feedback is applied to the operational amplifier 23, it operates so that its inverting input terminal voltage and non-inverting input terminal voltage become equal. Therefore, the voltage at the right end of the resistor 28 is VR
Since it is equal to the terminal voltage (VDD / 2 in this case),
A current of both positive and negative polarities corresponding to the voltage of the input terminal I flows according to Ohm's law with reference to VDD / 2 through the resistor 28. This current is equal to the difference between the current flowing through the transistor 24 and the current flowing through the transistor 25. In the transistors 26 and 27, the corresponding gates of the transistors 24 and 25 are connected to each other. As a result, due to the current mirror operation of the transistors 24 and 25 and the transistors 26 and 27, a current whose absolute value is equal to but opposite in polarity to the current flowing through the resistor 28 from the O terminal which is the output of the voltage-current converter 29. Will be output. The voltage-current conversion coefficient at this time is given by -1 / R, where R is the resistance value of the resistor 28.

In the adder circuit 9 of FIG. 2, the transistors 17 and 18 have the same current supply capability as the transistors 11 and 30 in the variable frequency oscillator circuits 4 and 10, and the transistors 19 and 20 are also in the variable frequency oscillator circuit 4. 1
It is assumed that the transistors 12 and 31 in 0 have the same current supply capability. Here, the output current Io of the voltage-current converter 29 is given by the following equation since the voltage-current conversion coefficient is -R as described above, where Vi is the input voltage of the voltage-current converter 29.

Io = − {Vi− (VDD / 2)} / R (3) Now, assuming that the voltage of Vi is VDD / 2, the output current Io of the voltage-current converter 29 is calculated from the above equation (3). It becomes zero. Then, when the output current Io is zero, the current flowing through the transistor 19 becomes equal to the current flowing through the transistor 17. Since the operating point conversion signal Vg from the operating point conversion circuit 5 is input to the gate terminal of the transistor 17, a current that is n times the current that flows in the transistor 11 of the variable frequency oscillation circuit 4 flows in the transistor 17.
As a result, according to the equations (1) and (2), the oscillation control signal Vf2 which is the output of the adder circuit 9 makes the oscillation frequency of the variable frequency oscillation circuit 10 n times the oscillation frequency of the variable frequency oscillation circuit 4. The signal to be set to.

The second phase synchronization circuit 119 is constructed so as to be synchronized with the input signal 6, but by the above operation,
Even if the oscillation frequency of the variable frequency oscillation circuit 4 and the oscillation center frequency of the variable frequency oscillation circuit 10 are different, it is possible to easily set the oscillation center frequency of the variable frequency oscillation circuit 10 that constitutes the second phase locked loop circuit 119. it can. And
When the output voltage Vi of the filter circuit 8 changes based on VDD / 2, the output V of the operating point conversion circuit 5 is output by the adder circuit 9.
An addition process with g is performed. Then, the oscillation frequency of the variable frequency oscillation circuit 10 changes based on the oscillation center frequency,
Accordingly, the variable frequency oscillator circuit 10 operates as an oscillator of the second phase locked loop circuit 119, and the second phase locked loop circuit 1
19 will be synchronized with the input signal 6.

Since the variable frequency oscillating circuit 4 and the variable frequency oscillating circuit 10 have the same structure and the same characteristics, even if the manufacturing frequency, the power supply voltage fluctuation, the ambient temperature change, etc. are affected, the oscillation operating current pair The oscillation frequency characteristics remain the same. Even if the oscillation operating current-oscillation frequency proportional coefficient fluctuates under these influences, the relationship that one oscillation frequency is n times the oscillation center frequency of the other is not broken. Therefore, if a very accurate and stable frequency such as a crystal oscillator is input to the reference frequency signal 1,
Even when the desired oscillation frequency is different from the reference frequency, it is possible to realize a highly accurate and stable phase-locked circuit without adjustment, without being affected by manufacturing variations, power supply voltage fluctuations, ambient temperature changes, and the like.

Further, according to this embodiment, it is possible to realize a phase locked loop in which the locked state is not easily released due to noise or the like and the jitter is less likely to increase. FIG. 4 is a characteristic diagram showing an example of the relationship between the oscillation operating current and the oscillation frequency of the variable frequency oscillator circuit. As is clear from this characteristic diagram, in the phase locked loop circuit as shown in FIG.
In order to synchronize the second phase locked loop with the oscillation frequency of ˜40 MHz, the oscillation operation current must be changed within the range shown in A of FIG. However, since the output voltage swing range of the filter circuit and the adder circuit is finite, it is difficult to change the oscillation operation current within a wide range (I0 to I1) as shown in FIG. Therefore, in order to deal with such a wide variable frequency range in the conventional phase locked loop, it is necessary to increase the proportional coefficient of the oscillation operating current to the oscillation frequency (increase the slope of the I / F line in FIG. 4). There is. However, increasing the proportional coefficient of the oscillation operating current to the oscillation frequency in this way makes it easier for the variable frequency oscillator circuit to be unlocked due to noise, etc.
Jitter tends to be increased, and stable phase-locked operation cannot be guaranteed. On the other hand, in the present embodiment, since the operating point conversion circuit 5 adds the offset current to the oscillation operating current in advance,
The oscillation operating current may be changed in the range shown in B of FIG. 4 for the oscillation frequency of 10 MHz and in the range shown in C of FIG. 4 for the oscillation frequency of 40 MHz. Therefore, the fluctuation range of the output voltage of the filter circuit 8 and the adder circuit 9 is not severely restricted, and the variable frequency oscillation circuit 10 is not required to have such a large oscillation operation current-oscillation frequency proportional coefficient. As a result, it is possible to realize a phase locked loop in which the locked state is hard to be released due to noise, jitter, and the like.

Although the current supply capacities of the transistors 13 and 15 are equal to the current supply capacities of the transistors 11 and 12 in the present embodiment for the sake of simplicity of description, they have the same proportionality constant and a proportional relationship. If so, the operation of the operating point conversion circuit does not change. Similarly, the transistors 17 and 18 and the transistors 19 and 20 are also equal to the current supply capacities of the transistors 11 and 12, respectively, but if they have the same proportionality constant and a proportional relationship, the operation of the adding circuit does not change. .

Further, in the present embodiment, the gate terminal of the transistor 11 in the variable frequency oscillator circuit 4 and the IN terminal of the operating point conversion circuit 5 are connected, but the present invention is not limited to this. For example, the gate terminal of the transistor 12 in the variable frequency oscillation circuit 4 and the IN terminal of the operating point conversion circuit 5 may be connected. In this case,
The operating point conversion circuit has a configuration as shown in FIG. 5, for example.
In this case, the current supply capacities of the transistors 13 and 21 are made equal to each other, and the current supply capacities of the transistors 15 and 22 are made equal to each other, or the transistors are arranged to have a proportional relationship with equal proportional constants. At this time, is the current flowing through the transistor 22 equal to the current flowing through the transistor 12 or
Alternatively, it is duplicated in the transistor 22 with a certain proportional constant. Then, all the current flowing through the transistor 22 flows through the transistor 21, and a voltage determined by this current is generated at the gate terminal of the transistor 21. As a result, the gate voltage of the transistor 21 becomes equal to the gate terminal voltage of the transistor 11. The subsequent operation is the same as the operation of the operating point conversion circuit described above.

FIG. 6 shows an example of the configuration of the operating point conversion circuit 205 in the case where means for arbitrarily controlling the current / current conversion magnification n (n is a real number) is provided. As shown in FIG. 6, the operating point conversion circuit 205 includes a switch circuit 221.
˜230, transistors 231-239, and transistors 240, 242, 244. FIG. 7 shows an example of the configuration of the switch circuits 221 to 230. The switch circuit includes an inverter 245, a transmission gate including transistors 246 and 248, and a transistor 250. And IN
The oscillation control signal Vf1 from the filter circuit 3 is input to the terminal, and one of the 8-bit control signals is input to the SW terminal.
One is entered. For example, bit 0 of the control signal is now "
1 ". In this case, the SW terminal of the switch circuit 221 becomes H level, and the switch circuit 2
The transmission gate in 21 becomes conductive, and the signal of Vf1 is transmitted to the gate terminal of the transistor 231. On the other hand, when the bit 0 becomes "0", the SW terminal of the switch circuit 221 becomes L level, the transmission gate in the switch circuit 221 becomes non-conductive, and the Vf1 signal is not transmitted to the gate terminal of the transistor 231. It will be. Similarly, by setting bits 0 to 7 of the control signal to "1" or "0", it is possible to control whether or not Vf1 is transmitted to the gate terminals of the transistors 231 to 239. The current supply capability of the transistors 231 to 239 is, for example, 1: 2: 4 :.
The weight is 8: 16: 32: 64: 128. As a result, the current / current conversion magnification n is set to 25.
It can be changed in 6 steps.

As described above, in the present embodiment, the means for arbitrarily controlling the current-to-current conversion magnification n is provided to generate a clock having an arbitrary frequency corresponding to each zone in zone bit recording. You can This can enhance the versatility of the device. Further, for example, in the characteristic diagram of the oscillation operation current versus the oscillation frequency in FIG. 4, the I / F straight line passes through the origin, but in reality, there is an error, and the I / F straight line may deviate from the origin. In addition, the I / F straight line may have non-linearity. In such a case, an error occurs in the equation of f = ai in the above equation (1).
However, such an error can be corrected by adjusting the value of the magnification n. For example, the frequency of the reference frequency signal input to the first phase locked loop 99 is f
and the frequency of the input signal input to the second phase-locked loop 119 is c × fm. Then, consider a case where the I / F line of the variable frequency oscillator does not pass through the origin. In such a case, in the present embodiment, the value of n is set not to be equal to c but to be a different value.
As a result, even when the I / F straight line does not pass through the origin, it becomes possible to output a clock having an accurate frequency of c × m from the second phase synchronization circuit 119.

In FIG. 6, the transistor 23
1 to 239 are divided as shown in the same drawing, but the present invention is not limited to this.
The configuration may be such that 0, 242, and 244 are divided.

Further, in the present embodiment, the case where a so-called I / F type variable frequency oscillation circuit is used as the variable frequency oscillation circuit has been described as an example. However, the present invention is not limited to this, and as shown in FIGS. 8A and 8B, V / F type variable frequency oscillation circuits 33 and 34 in which the input voltage and the oscillation frequency are proportional may be used. . In this case, the operating point conversion circuit uses the voltage multiplier 36, the multiplication type D / A converter 38, and the like, and the addition circuit uses the voltage addition circuit 32 and the like.

FIG. 9A shows an example of the circuit configuration of the voltage multiplier 36. In this circuit, 8-bit D / A
An analog multiplier 254 multiplies VY obtained by the converter 252 and VX which is an input signal to obtain an output.

FIG. 9B shows an example of the circuit configuration of the multiplication type D / A converter 38. In this circuit, the 8-bit R-2R ladder D / A converter 256
D / A conversion is performed by the operational amplifier 258,
The output is obtained by buffering or amplifying at 260. In this case, since the R-2R ladder D / A converter 256 shunts the voltage with a resistor to obtain a current output, it is necessary to amplify the output with an inverting operational amplifier. Therefore, it is difficult to realize this circuit with a single 5V power supply. Therefore, when a circuit is configured with a single 5V power source, it is necessary to have a circuit configuration as shown in FIG. In this circuit, a reverse R-2 with the input of the R-2R ladder D / A converter as the output and the output as the input
The R ladder 262 is used (simply a series resistor having a tap and a switch may be used). Then, select a tap to which the non-inverting operational amplifier 264 is connected with 8-bit data,
Thereby, a desired output can be obtained.

FIG. 10A shows an example of the circuit configuration of the voltage adding circuit 32. This circuit is an operational amplifier 26
6, 268 are included, but the configuration is known, and thus the description thereof is omitted. In order to operate with a single 5V power supply, it is necessary to have a circuit configuration including a non-inverting operational amplifier 270 as shown in FIG.

2. Second Example The second example is an example relating to a one-shot circuit. FIG. 11 shows a block diagram of the second embodiment, and FIG. 12 shows a circuit diagram showing details of the circuits constituting each block. As shown in FIG. 11, the one-shot circuit according to the second embodiment includes an input detection circuit 51, a variable frequency oscillation circuit 55, an edge detection circuit 61, and a phase synchronization circuit 59. Here, the input detection circuit 51 also serves as an oscillation control circuit. Further, FIG. 12 shows an example in which the variable frequency oscillation circuit 55 is configured by a ring oscillator.
ST is an oscillation start / stop control terminal, and in the case of FIG. 12, the oscillation is stopped when the input voltage to the ST terminal is at L level, and the output Va of the variable frequency oscillation circuit 55 is fixed at H level. On the other hand, when the input voltage to the ST terminal becomes the H level, oscillation starts, and from this point the output voltage Va repeats the H level and the L level for each half cycle of the oscillation cycle and continues to oscillate. The oscillation frequency in this case is determined by the voltage of the oscillation frequency control terminal IN. This IN terminal is connected to the IN terminal of the variable frequency oscillation circuit 60 in the phase locked loop 59 and Vf2.
Connected in common by signals. As shown in FIG. 12, the variable frequency oscillation circuits 55 and 60 have the same configuration and oscillate at the same frequency with respect to the same frequency control signal Vf2. The output Va of the variable frequency oscillation circuit 55 is input to the clock terminal of the edge detection circuit 61 including the N-ary asynchronous preset down counter in the next stage.

Now, it is assumed that the phase locked loop 59 is stable in synchronization with the reference frequency signal 58. When the rising edge of the input signal 53 is detected, the output of the input detection circuit 51 becomes H
Get up to the level. Input detection circuit (oscillation control circuit) 5
Since the output of No. 1 is connected to the oscillation start / stop control terminal ST, the variable frequency oscillation circuit 55 receiving this starts oscillation. When the rising edge of the output Va is counted N times, the edge detection circuit 61 outputs Vb of L level and presets itself. The preset edge detection circuit 61 tries to restart the counting by returning the output Vb to the H level again. However, the edge detection circuit 61
Output Vb is also input to the reset terminal of the input detection circuit 51, the oscillation start / stop control terminal ST goes to L level, oscillation stops, and the edge detection circuit 61 also stops counting. As a result, the input detection circuit 51, the variable frequency oscillation circuit 55, and the edge detection circuit 61 all wait in the input waiting state until the rising edge of the input signal 53 is detected again.

Each time the rising edge of the input signal 53 is detected, the above series of operations are repeated to obtain the desired one-shot pulse output 54 at the output of the input detection circuit (oscillation control circuit) 51. If the desired one-shot pulse width is long, it can be easily dealt with by simply increasing the preset value m of the edge detection circuit 61. This means that only a logic circuit can cope with a desired pulse width, and it is possible to significantly reduce the occupied area as compared with the conventional technique.

FIG. 13 shows a timing chart when m = 5 and the rise detection of the output Va is detected. As shown in FIG. 13, the one-shot pulse output 54 becomes H level at the rising edge of the input signal 53 (see E in FIG. 13), and when the rising edge of the output Va of the variable frequency oscillation circuit 55 is counted five times, edge detection is performed. The output Vb of the circuit 61 becomes L level (see F), and the one-shot pulse output 54 also becomes L level (see G).

Note that m = 1 and the variable frequency oscillating circuit 55.
In the case of detecting the falling edge of the output Va, the edge detection circuit 61 is deleted and the output V of the variable frequency oscillation circuit 55 is deleted.
By directly inputting a to the reset terminal of the input detection circuit 51, the input detection circuit 51 can also function as an edge detection circuit. When m = 1 and the rising edge of the output Va of the variable frequency oscillation circuit 55 is detected, the output Va of the variable frequency oscillation circuit 55 outputs a negative pulse once every time the input detection circuit 51 detects an input signal. Then, the variable frequency oscillator circuit 55 stops the oscillation. Therefore, in this case, the output of the variable frequency oscillation circuit 55 can be a one shot pulse output.

Since the variable frequency oscillation circuit 55 and the variable frequency oscillation circuit 60 have the same structure, the oscillation frequency of the variable frequency oscillation circuit 55 is equal to the oscillation frequency of the variable frequency oscillation circuit 60. Further, the oscillation frequency of the variable frequency oscillation circuit 60 becomes equal to the frequency of the reference frequency signal 58 due to the synchronous operation. When the one-shot circuit of this embodiment is formed on an integrated circuit, the same oscillation characteristics can be easily obtained by arranging the physical patterns of the two variable frequency oscillation circuits in the same manner. Accordingly, if a very accurate and highly stable frequency such as a crystal oscillator is used as the reference frequency signal 58, the one-shot pulse width can be highly accurately and highly stabilized against manufacturing variations, power supply voltage fluctuations, and ambient temperature changes. You can

In the present embodiment, both the input detection circuit 51 and the edge detection circuit 61 detect rising edges, but falling edges can be detected by inserting an inverter circuit in series with each input.

FIG. 14 shows a block diagram in the case where the operating point conversion circuit 63 having the same structure as that of the first embodiment is inserted in the second embodiment. FIG. 11 above,
In the configuration shown in FIG. 12, the oscillation frequency control terminal IN of the variable frequency oscillation circuit 55 and the oscillation frequency control terminal IN of the variable frequency oscillation circuit 60 are connected to each other. On the other hand, in the configuration shown in FIG.
The difference is that an operating point conversion circuit 63 is inserted between the IN terminal and the IN terminal of the variable frequency oscillation circuit 55. Except for this point, the configuration is the same as that shown in FIGS.

When the operating point conversion circuit (current / current conversion coefficient k) 63 is inserted in this way, as is apparent from the description of the first embodiment, the variable frequency oscillation circuit 5 is inserted.
The oscillation frequency of 5 can be made approximately equal to, for example, k times (k is a real number) or k times the oscillation frequency of the variable frequency oscillation circuit 60. The reason is that the operating point conversion circuit 63 has the same configuration as the operating point conversion circuit 5 of the first embodiment described in FIG. 2, so that the oscillation operating current in the variable frequency oscillation circuit 55 is oscillated in the variable frequency oscillation circuit 60. This is because the operating current can be increased by, for example, k times.

In this way, if the oscillation frequency of the variable frequency oscillation circuit 55 can be multiplied by k, the one-shot pulse width setting resolution determined by the frequency of the reference frequency signal 58
The one-shot pulse width can be set with a resolution k times finer. This is particularly effective when the frequency of the reference frequency signal 58 is fixed and cannot be changed, or when it is desired to arbitrarily change the resolution of the one-shot pulse width. Further, even with respect to manufacturing variations, power supply voltage fluctuations, and ambient temperature changes, the configurations and characteristics of the variable frequency oscillating circuits 55 and 60 are the same, and the relationship between the oscillating operating current and the oscillating frequency is proportional. High accuracy and high stability can be achieved as in the second embodiment.

In the operating point conversion circuit 63 shown in FIG. 14 as well, as in the case shown in FIG.
It is possible to provide a means for controlling arbitrarily. By providing such control means, it is possible to accurately generate a one-shot pulse of an arbitrary width corresponding to the clock of each zone in zone bit recording, as in the first embodiment. Even when the I / F straight line does not pass through the origin or when the I / F straight line has non-linearity, it is possible to accurately obtain a one-shot pulse with a desired width by correcting and controlling with the magnification k. You can Further, the oscillation cycle of the variable frequency oscillation circuit in the one-shot circuit does not have an accurate value immediately after the start of oscillation and has an error, so that a one-shot pulse having a desired width may not be obtained. Even in such a case, a one-shot pulse having a desired width can be accurately obtained by correcting and controlling the magnification k. Furthermore, by correcting and controlling the magnification k, it is possible to provide an adjustment function called so-called window center adjustment.

The operating point conversion circuit 63 may have various configurations, for example, the configuration shown in FIG.

Further, in the present embodiment, the case where a so-called I / F type variable frequency oscillation circuit is used as the variable frequency oscillation circuit has been described as an example. However, the present invention is not limited to this, and as shown in FIGS. 15A and 15B, V / F type variable frequency oscillation circuits 73 and 74 in which the input voltage and the oscillation frequency are proportional may be used. . In this case, as the operating point conversion circuit, the voltage multiplier 76, the multiplication type D / A converter 78 and the like having the configurations shown in FIGS. 9A to 9C are used.

3. Third Embodiment A third embodiment is a phase locked loop circuit of the first embodiment,
9 is an embodiment relating to a signal processing device including the one-shot circuit of the second embodiment.

FIG. 16 shows a block diagram of a signal processing apparatus according to the third embodiment. As shown in FIG.
This signal processing device includes a reference frequency source 101, a first phase synchronization circuit 100, an operating point conversion circuit 105, a second phase synchronization circuit 120, a one-shot circuit 150, and a third phase synchronization circuit 160. Then, the read data RD reproduced from the information storage medium 144 using the head 146 and shaped by the shaper 148 is subjected to predetermined signal processing to generate normalized read data SYDT and read clock SYCLK. is there. It is also possible to use the output WCLK of the second phase locked loop 120 as a write clock for the information storage medium.

The first phase locked loop circuit 100 includes a phase comparator 102, a filter circuit 103, and a variable frequency oscillator circuit 10.
4 in the first embodiment shown in FIGS. 1 and 2
It has the same configuration as the phase-locked loop circuit. Further, the operating point conversion circuit 105 has the same configuration as the operating point conversion circuit shown in FIG. 6, in which the current / current conversion magnification n can be arbitrarily set by an 8-bit control signal. In addition, the second phase synchronization circuit 120 includes the phase comparator 107 and the filter circuit 10.
8, an adder circuit 109, and a variable frequency oscillator circuit 110. Further, the configuration is different from the second phase locked loop circuit in the first embodiment in that it further includes a 1 / M frequency divider 106 and a 1 / N frequency divider 111. The 1 / M frequency divider 106 and the 1 / N frequency divider 111 are provided in order to generate a clock having a frequency of (N / M) times the reference frequency. That is, in FIG. 16, since the frequencies of FIN0 and FIN1 which are inputs to the phase comparator 107 are the same, M
When the frequencies of CLK and WCLK are fm and fw, respectively, the following equation holds.

Fm × (1 / M) = fw × (1 / N) (4) From the above equation, fw = fm × (N / M), and a clock that is (N / M) times the reference frequency must be obtained. become. The operating point conversion circuit 105 sets n to be the same as (N / M) or substantially equal to it. As a result, the center oscillation frequency of the variable frequency oscillation circuit 110 can be adjusted to fw, and stable oscillation is possible.

The one-shot circuit 150 includes an input detection circuit (oscillation control circuit) 151, a variable frequency oscillation circuit 155,
It includes the edge detection circuit and has the same configuration as the one-shot circuit in the second embodiment. Then, based on the read data RD, the one-shot pulse output OS having a width determined by the oscillation control signal Vf2 and the count m is output. The oscillation frequency control terminal IN of the variable frequency oscillation circuit 155 is commonly connected to the IN terminal of the variable frequency oscillation circuit 110, and the oscillation control signal Vf2 is input. As a result, the oscillation frequency of the variable frequency oscillation circuit 155 becomes the same as the oscillation frequency of the variable frequency oscillation circuit 110. Therefore, the multiplication factor n in the operating point conversion circuit 105, the frequency division ratios (1 / M) of the frequency dividers 106 and 111, (1
/ N) changes the oscillating frequency synchronized by the second phase locked loop 120, the width of the one-shot pulse also changes accordingly. Therefore, the zone bit
When reading data from the information processing medium in which the data is stored by recording, the above n,
(1 / M) and (1 / N) will be adjusted. As a result, the width of the one-shot pulse can be adjusted according to the transfer rate of the data read from each zone, and the zone bit recorded data can be read properly.

The third phase locked loop circuit 160 for data separator includes a phase comparator 162, a filter circuit 164, an adder circuit 166, a variable frequency oscillator circuit 168, and a data normalization circuit 170. Then, the one-shot pulse output OS of the one-shot circuit 150 is input to the phase comparator 162, and the oscillation control signal Vf2 is input to the IN1 terminal of the adding circuit 166. As a result, the third phase synchronization circuit 160 is phase-synchronized with the one-shot pulse output OS with the oscillation frequency of the variable frequency oscillation circuits 110 and 155 as the central oscillation frequency.

FIG. 17 shows an example of the configuration of the data normalization circuit 170. This data normalization circuit 170
D-Flip-flops 172 and 174, inverter circuit 176, buffer circuits 178 and 179, AND circuit 1
Including 80. Then, based on the one-shot pulse output OS and the output I / F of the variable frequency oscillation circuit 168,
The normalized read data SYDT and the read clock SYCLK are generated. RS is a signal for resetting the data normalization circuit 170.

In FIG. 18, the read data RD, the one-shot output OS, and the output I / of the variable frequency oscillation circuit 168 are shown.
A timing chart showing the relationship between F (SYCLK), the output DFF1 of the D-lip flop 172, and the normalized read data SYDT is shown.

As shown in FIG. 18, the synchronizing operation by the third phase synchronizing circuit 160 causes the falling edges of the OS and the I / F to be phase-synchronized (see E in FIG. 18). Further, when RD rises, OS is set to H level by the detection of the input detection circuit 151, and thereby DFF1 is also set to H level (see F and G). Next, when the I / F falls, SYD which is the output of the D-phillip flop 174 is output.
T goes to H level, and at the same time, the D-Flip-flop 172 is reset and DFF1 goes to L level (see H and I). Then, SYDT becomes L level at the next fall of I / F (see J). In this way, according to this embodiment, it is possible to generate SYDT and SYCLK having a rising edge at the center position of the SYDT pulse (see K).

Now, in the present embodiment, as shown in FIG. 18, the width of the one-shot pulse output OS is a half cycle of the I / F, that is, a cycle of 50%. The width of the OS is set to 50% of the I / F cycle in this way in order to properly secure the margin for the peak shift occurring in the read data RD.

For example, the read data RD is as shown in FIG.
Consider a case where the peak is shifted to the right as shown by E in (A). When the RD peak shifts in this way, the OS
Becomes H level due to the rising edge of RD,
The rising edge of the OS also shifts to the right (FIG. 19).
(See F and G in (A)). Now, DFF1 becomes H level at the rising edge of OS, and becomes L level at the falling edge of I / F (see H and I). Therefore,
If the rising edge of the OS and the falling edge of the I / F match, the timing of the rising edge and the timing of the falling edge of the DFF1 will match, and erroneous SYDT will be output.
Here, the fall of the OS and the fall of the I / F are
Normally, the third phase synchronization circuit 160 synchronizes by the synchronization operation. However, the peak shift has a very high frequency component as compared with the frequency change due to the rotation fluctuation of the medium. Therefore, normally, the third phase-locked loop 160 is configured to have a low-speed response characteristic to the peak shift so as not to follow the peak shift. Therefore, as shown in FIG. 19 (A), even if a peak shift occurs, the I / F does not follow this and do not significantly shift to the right.

Here, assuming that the follow-up speed for the peak shift of the third phase-locked loop 160 is zero (cannot follow) for simplification of description, the width of the one-shot pulse output OS is the period of the I / F. If it was 50%,
The peak shift to the right can be allowed up to + 50% of the I / F cycle (see J in FIG. 19A).
However, in consideration of the delay value of the logic circuit such as the D-phillip flop, the peak shift margin is actually smaller than + 50%.

Contrary to the above, FIG. 19B shows the case where RD peak-shifts to the left. In this case, if the rising edge of DFF1 (rising edge of OS) and the falling edge of I / F match, erroneous SYDT will be output (H in FIG. 19B). I)). That is, when the width of the one-shot pulse output OS is 50% of the I / F cycle, -50% of the I / F cycle (see J in FIG. 19B).
Up to, the peak shift to the left will be allowed.

As is clear from the above, when the width of the one-shot pulse output OS is 50% of the I / F cycle, the influence of the delay value of the logic circuit and the follow-up degree to the peak shift should be ignored. Therefore, it is concluded that a peak shift of -50% to + 50% is acceptable. The peak shift may occur in both the right direction and the left direction depending on the characteristics of the information recording medium. Therefore, it is desirable for the signal processing device side to have an allowance margin (-50% to + 50%) equally for the peak shift in both the right direction and the left direction. In this sense, in the normal state, it is desirable that the width of the one-shot pulse output OS is exactly 50% of the I / F cycle. Further, according to the one-shot circuit 150 of the present embodiment, the one-shot pulse width can be adjusted more accurately than in the conventional one-shot circuit, so that the one-shot pulse width can be accurately adjusted to 50 times the I / F cycle.
It can be%. As a result, it is possible to realize a signal processing device that is less likely to malfunction due to the peak shift of read data.

As described above, in the normal state, the one-shot pulse width is exactly 50 I / F cycles.
% Is desirable. However, in some cases, it may be desired to adjust the window margin for peak shift, that is, to perform the window center adjustment.
In such a case, the method of inserting the operating point conversion circuit as described in FIG. 14 is particularly effective. That is, the operating point conversion circuit that receives the oscillation control signal Vf2 is inserted in the preceding stage of the variable frequency oscillation circuit 155. Then, the operating point conversion signal which is the output of the operating point conversion circuit (current / current conversion magnification k) is input to the IN terminal of the variable frequency oscillation circuit 155. Thereby, the oscillation frequency of the variable frequency oscillation circuit 155 can be made different from the oscillation frequency of the variable frequency oscillation circuit 110, and for example, the variable frequency oscillation circuit 110.
It is possible to oscillate at a frequency higher than the oscillation frequency of. And the adjustment that makes this oscillation frequency different is
This is done by adjusting the current / current conversion magnification k of the operating point conversion circuit. As a result, the width of the one-shot pulse can be adjusted with extremely high resolution, and the window center adjustment can be performed with extremely high accuracy.

20A and 20B, when the width of the one-shot pulse is increased to adjust the window center, specifically, the width of the one-shot pulse is set to 75% of the I / F cycle. An example in the case of doing is shown. In this case, considering a case where a rightward peak shift occurs as shown in FIG. 20A, the rising edge of the DFF 1 and the I / F
The correct SYDT is output until the falling edges of the two coincide with each other (see H and I in FIG. 20A).
Therefore, set the one-shot pulse width to 75% of the I / F cycle.
Then, the window margin on the + side increases by 25% to + 75% (see J in FIG. 20A). On the other hand, FIG.
As shown in 0 (B), considering a case where a peak shift occurs in the left direction, the window margin on the − side is reduced by 25% to −25% contrary to the above (FIG. 20 (B)). See J).

In this way, the width of the one-shot pulse is set to I
When it is set to 75% of the period of / F, the window margin becomes −25 to + 75%, and the window center is +
You can shift 25% to the side. That is, by increasing the width of the one-shot pulse, it becomes possible to adjust the window center to the + side.

In FIGS. 21A and 21B, the width of the one-shot pulse is I / F for adjusting the window center.
An example in which the period is set to 25% is shown. In this case, considering a case where a rightward peak shift occurs as shown in FIG. 21A, the window margin on the + side is 2
It decreases by 5% to + 25% (see J in FIG. 21 (A)). On the other hand, as shown in FIG. 21B, considering the case where a peak shift occurs in the left direction, the window margin on the − side increases by 25% to −75%, contrary to the above. (See J in (B)).

In this way, the width of the one-shot pulse is set to I
When it is set to 25% of the cycle of / F, the window margin becomes -75% to + 25%, and the window center can be shifted to the -side by 25%. That is, by shortening the width of the one-shot pulse, it is possible to adjust the window center to the − side.

As described above, according to this embodiment, it is understood that the window center can be adjusted by adjusting the width of the one-shot pulse. Then, by adjusting the window center in this manner, it becomes possible to test the window margin of the entire data reading system. Further, depending on the information storage medium, there is a medium in which the peak shift is likely to occur in the right direction or the left direction. In such a case, in this embodiment, the width of the one-shot pulse is changed according to the characteristics of the information storage medium to shift the window center to the + side or the-side, thereby effectively preventing erroneous reading of data. You can do it.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention.

For example, the configurations of the variable frequency oscillation means, operating point conversion means, addition means, input detection means (oscillation control means), edge detection means, and data normalization means are not limited to those described in this embodiment, All kinds of configurations can be considered as long as they have similar functions.

Further, the phase locked loop circuit, the one-shot circuit, and the signal processing device according to the present invention perform the read processing from the read-only information storage medium such as the CD-ROM and the writing in the information storage medium such as the hard disk and the magneto-optical disk. Of course, it can be applied to both read processing.

[0097]

According to the first aspect of the present invention, it becomes possible to synchronize the second phase synchronization means with an input signal having a frequency that is, for example, n times the reference frequency or substantially equal to n times the reference frequency. . As a result, even when the desired oscillation frequency is different from the reference frequency, a highly accurate and stable phase locked loop can be realized without adjustment, without being affected by manufacturing variations, power supply voltage fluctuations, ambient temperature changes, and the like. Further, in particular, in the case where the conversion in the operating point converting means is to convert the current n times, there is an advantage that the operating point converting means can be realized with a simple configuration.

According to the second aspect of the invention, the control means makes it possible to control the center oscillation frequency of the second variable frequency oscillation means to an arbitrary value. This allows
It is possible to realize an optimal phase synchronization circuit for zone bit recording, etc. Further, according to the present invention, even when the I / F straight line or the like does not pass through the origin or has the non-linearity, it is possible to effectively eliminate the error caused thereby.

According to the invention of claim 3, it is possible to output a one-shot pulse having a width determined by the reference frequency and the count m. As a result, even if the desired one-shot pulse width is large, it is possible to suppress an increase in occupied area and obtain a highly accurate and stable one-shot pulse output in a wide pulse width range.

Further, according to the invention of claim 4 or 8, the resolution when setting the width of the one-shot pulse can be increased by k times. This makes it possible to set the width of the one-shot pulse with finer resolution.

According to the invention of claim 5 or 9, it is possible to control the width of the one-shot pulse with an arbitrary resolution. As a result, it is possible to obtain a one-shot pulse having an arbitrary accurate width corresponding to, for example, zone bit recording. Further, even when the one-shot pulse having a desired width cannot be obtained because the oscillation cycle of the variable frequency oscillating means does not become accurate immediately after the start of oscillation, it is possible to accurately obtain the desired width by controlling the magnification k. One-shot pulse can be obtained.

According to the invention of claim 6 or 10,
The window center can be adjusted by adjusting the width of the one-shot pulse. This makes it possible to test the window margin of the entire data reading system. Also, if there is an information storage medium that is prone to peak shift in the right or left direction, the width of the one-shot pulse can be changed according to the characteristics of the information storage medium to adjust the window center, Erroneous reading can be effectively prevented.

According to the invention of claim 7, it is possible to reproduce the normalized read data and the read clock from the data read from the information storage medium. Further, it is possible to generate a data write clock to the information storage medium by using the output clock of the second phase locked loop.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to a first embodiment.

FIG. 2 is a diagram showing details of a circuit forming each block in FIG.

FIG. 3 is a diagram showing a configuration example of a voltage-current converter.

FIG. 4 is a characteristic diagram showing an example of a relationship between an oscillation operating current and an oscillation frequency of a variable frequency oscillator circuit.

FIG. 5 is a diagram showing another configuration example of an operating point conversion circuit.

FIG. 6 is a diagram showing an example of an operating point conversion circuit having means capable of arbitrarily controlling a magnification n.

FIG. 7 is a diagram showing an example of a configuration of a switch circuit.

FIGS. 8A and 8B are diagrams showing a configuration example of a phase locked loop circuit when a V / F type variable frequency oscillation circuit is used as the variable frequency oscillation circuit.

9 (A), (B), and (C) are diagrams showing an example of configurations of a voltage multiplier and a multiplication type D / A converter.

10A and 10B are diagrams showing an example of the configuration of a voltage adding circuit.

FIG. 11 is a block diagram of a one-shot circuit according to the second embodiment.

12 is a diagram showing details of a circuit forming each block in FIG.

FIG. 13 is a timing chart showing the operation of the one-shot circuit.

FIG. 14 is a diagram showing a configuration example of a one-shot circuit provided with an operating point conversion circuit.

15A and 15B are diagrams showing a configuration example of a one-shot circuit when a V / F type variable frequency oscillation circuit is used as the variable frequency oscillation circuit.

FIG. 16 is a block diagram of a signal processing device according to the third embodiment.

FIG. 17 is a diagram showing an example of a configuration of a data normalization circuit. The figure which shows the example of an operating point conversion circuit.

FIG. 18 is a timing chart showing the operation of the third embodiment.

19A and 19B are timing charts when the width of a one-shot pulse is 50% of the I / F cycle and peak shift occurs in the rightward and leftward directions.

20A and 20B are timing charts when the width of a one-shot pulse is 75% of the I / F cycle and peak shift occurs in the rightward and leftward directions.

21A and 21B are timing charts in the case where the width of a one-shot pulse is 25% of the I / F cycle and a peak shift occurs in the rightward and leftward directions.

FIG. 22 is a diagram showing a configuration of a conventional phase locked loop circuit.

FIG. 23 is a diagram showing a configuration of a conventional one-shot circuit.

[Explanation of symbols]

 1 Reference frequency signal 2 Phase comparator 3 Filter circuit 4 Variable frequency oscillation circuit 5 Operating point conversion circuit 6 Input signal 7 Phase comparator 8 Filter circuit 9 Adder circuit 10 Variable frequency oscillation circuit 51 Input detection circuit (oscillation control circuit) 53 Input Signal 54 One-shot pulse output 55 Variable frequency oscillation circuit 58 Reference frequency signal 59 Phase synchronization circuit 60 Variable frequency oscillation circuit 61 Edge detection circuit 63 Operating point conversion circuit 99, 100 First phase synchronization circuit 119, 120 Second phase synchronization Circuit 101 Reference frequency source 102 Phase comparator 103 Filter circuit 104 Variable frequency oscillation circuit 105 Operating point conversion circuit 106 1 / N frequency divider 107 Phase comparator 108 Filter circuit 109 Adder circuit 110 Variable frequency oscillation circuit 111 1 / N frequency division Vessel 144 information storage medium 146 f Dead 148 Shaper 150 One-shot circuit 151 Input detection circuit (oscillation control circuit) 155 Variable frequency oscillation circuit 160 Third phase synchronization circuit (data separator) 161 Edge detection circuit 162 Phase comparator 164 Filter circuit 166 Adder circuit 168 Variable Frequency oscillator 170 Data normalizer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 3/355 5/08 W 7402-5J 5/135 H03L 7/099

Claims (10)

[Claims] 1. A first phase synchronizing means for synchronizing with a reference frequency signal, and a second phase synchronizing means for synchronizing with an input signal,
A phase synchronization circuit including operating point conversion means, the first phase synchronization means performing phase comparison for synchronizing with the reference frequency signal, and the first phase comparison means. First filter means connected to the means to generate a first oscillation control signal, and first variable frequency oscillation means having an oscillation frequency controlled based on a current or a voltage set by the first oscillation control signal. The operating point converting means includes an operating point converting signal capable of setting a current or voltage n times as large as the current or voltage set by the first oscillation control signal based on the first oscillation control signal. Second phase comparing means for generating, the second phase synchronizing means performing phase comparison for synchronizing with the input signal, and second filter means connected to the second phase comparing means, The operating point conversion signal and the second flux Output and the first filter means,
An addition unit that is input to the second addition input terminal and generates a second oscillation control signal by current addition or voltage addition;
And a second variable frequency oscillating means whose oscillation frequency is controlled based on the current or voltage set by the oscillation control signal of 1. 2. The phase locked loop circuit according to claim 1, wherein the operating point conversion means includes means capable of arbitrarily controlling the magnification n. 3. An input detection means for detecting the presence or absence of an input signal, an oscillation control means, a first variable frequency oscillation means, an edge detection means, and a second configuration having the same configuration as the first variable frequency oscillation means. A one-shot pulse generated at the output terminal of the oscillation control means or the output terminal of the first variable frequency oscillation means. A pulse generating circuit, wherein the edge detecting means outputs a detection signal after counting rising edges or falling edges of the output signal of the first variable frequency oscillating means by a natural number m times, and the oscillation control means When the input signal is detected by the input detection means, an oscillation start signal is output to the first variable frequency oscillation means, and the edge detection means outputs the detection signal. And outputs an oscillation stop signal to the first variable frequency oscillation means, the first variable frequency oscillation means having an oscillation start / stop control terminal and an oscillation frequency control terminal, and the oscillation start / stop control terminal When the oscillation start signal is input to the oscillation start signal, the oscillation is started, the frequency of the oscillation is controlled based on the oscillation control signal of the second variable frequency oscillation means input to the oscillation frequency control terminal, and the oscillation start is stopped. A one-shot pulse generation circuit, which stops the oscillation when the oscillation stop signal is input to a control terminal. 4. The current or voltage k set by the oscillation control signal based on the oscillation control signal of the second variable frequency oscillating means according to claim 3.
A one-shot pulse generation circuit including operating point conversion means for generating an operating point conversion signal capable of setting a doubled current or voltage and outputting it to the oscillation frequency control terminal of the first variable frequency oscillation means. . 5. The one-shot pulse generating circuit according to claim 4, wherein the operating point converting means includes means capable of arbitrarily controlling the magnification k. 6. The window center is adjusted according to claim 3, wherein the width of the one-shot pulse is adjusted by the count m or the count m and the magnification k. One-shot pulse generator circuit. 7. A first phase synchronizing means for synchronizing with a reference frequency signal, a second phase synchronizing means for synchronizing with a clock signal set based on the reference frequency signal, and a first operating point converting means. A one-shot pulse generating means having an input detecting means for detecting the presence or absence of read data from the information medium, an oscillation controlling means, a fourth variable frequency oscillating means and an edge detecting means, and a third phase synchronizing means for a data separator. And a first phase synchronization means, wherein the first phase synchronization means is connected to the first phase comparison means for performing phase comparison for synchronizing with the reference frequency signal, and the first phase comparison means. First filter means for generating a first oscillation control signal, and a first variable frequency oscillator whose oscillation frequency is controlled based on a current or a voltage set by the first oscillation control signal. Wherein the first operating point conversion means is capable of setting a current or voltage n times the current or voltage set by the first oscillation control signal based on the first oscillation control signal. A second phase comparison means for generating a first operating point conversion signal, the second phase synchronization means performing phase comparison for synchronizing with the clock signal, and the second phase comparison means.
Second filter means connected to the phase comparison means, the first operating point conversion signal and the output of the second filter means are input to the first and second addition input terminals to add current or voltage. The adder means for generating a second oscillation control signal by addition; and the second variable frequency oscillating means for controlling the oscillation frequency based on the current or voltage set by the second oscillation control signal. The edge detecting means included in the shot pulse generating means is a natural number m of the rising edge or the falling edge of the output signal of the fourth variable frequency oscillating means.
A detection signal is output after counting the number of times, and the oscillation control means included in the one-shot pulse generation means outputs an oscillation start signal to the fourth variable frequency oscillation means when read data is detected by the input detection means. And outputs an oscillation stop signal to the fourth variable frequency oscillation means when the detection signal is input from the edge detection means, and the fourth variable frequency oscillation means included in the one-shot pulse generation means An oscillation start / stop control terminal and an oscillation frequency control terminal are provided, and when the oscillation start signal is input to the oscillation start / stop control terminal, oscillation is started, and the frequency of the oscillation is input to the oscillation frequency control terminal. The oscillation is controlled based on the second oscillation control signal of the second variable frequency oscillating means, and the oscillation is stopped when the oscillation stop signal is input to the oscillation start / stop control terminal. And a third phase comparison means for stopping the third phase synchronization means for the data separator and performing a phase comparison for synchronizing with the one-shot pulse output of the one-shot pulse generation means, and the third phase comparison means. A third filter means connected to the means, the second oscillation control signal and the output of the third filter means are input to the first and second addition input terminals to obtain a third value by current addition or voltage addition. Of the oscillation control signal, third variable frequency oscillation means whose oscillation frequency is controlled based on the current or voltage set by the third oscillation control signal, and data normalization means. A signal processing device characterized by: 8. The current or voltage of claim 7, which is k times the current or voltage set by the second oscillation control signal based on the second oscillation control signal of the second variable frequency oscillating means. A second operating point converting means for generating a settable second operating point converting signal and outputting it to the oscillation frequency control terminal of the fourth variable frequency oscillating means in the one-shot pulse generating means; A characteristic signal processing device. 9. The signal processing device according to claim 7, wherein the first and second operating point converting means include means capable of arbitrarily controlling the magnifications n and k. 10. The window center is adjusted by adjusting the width of the one-shot pulse output by the count m or the count m and the magnification k. Signal processing device.