JPH0799256A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an EEPROM, which can form a floating gate satisfying both the characteristics of the interface of a tunnel insulating film and the insulating film between the floating gate and a control gate and can improve the characteristics and the reliability of an element. CONSTITUTION:A floating gate is formed on a semiconductor substrate through a tunnel insulating film. A control gate is formed on the floating gate through a gate insulating film. Thus, an electrically rewritable memory cell is constituted. In the EEPROM, wherein a plurality of memory cells are integrated, the floating gate is formed of double-layered polycrystalline silicon films 40a and 40b. Arsenic is doped into the silicon film 40a at the lower layer as impurities. phosphorus is doped into the silicon film 40b at the upper layer as impurities.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device (EEPROM) using electrically rewritable memory cells in which a floating gate and a control gate are stacked. .

[0002]

2. Description of the Related Art Conventionally, an N-type memory cell having a plurality of memory cells connected in series has been proposed as a highly-integrated EEPROM.
An AND cell type EEPROM is known. One memory cell has a FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate via an insulating film, and a plurality of memory cells adjacent to each other are connected in series to share a source and a drain. Connected to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array.

The drains on one end side of the NAND cells arranged in the column direction of the cell array are commonly connected to the bit line through the select gates, and the other end side is also connected to the common source line which is also the source line through the select gates. Has been done. The gate electrodes of the control gates and select gates of the memory cells are commonly connected as control gate lines (word lines) and select gate lines in the row direction of the memory cell array.

The operation of this NAND cell type EEPROM is as follows. Data writing is sequentially performed from the memory cell farther from the bit line. To explain the case of the n-channel, a high voltage VPP (for example, 20V) is applied to the control gate of the selected memory cell, and the control gate and the select gate of the non-selected memory cell on the bit line side from this are applied. An intermediate potential VM (for example, 10V) is applied. 0V (for example, "1") or an intermediate potential VM (for example, "0") is applied to the bit line depending on the data. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the selection gate and the non-selected memory cell.

When there is data to be written (“1” data), a high electric field is applied between the gate and drain of the selected memory cell, and electrons are tunnel-injected from the substrate to the floating gate. As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to be written (“0” data), the threshold value does not change.

In data erasing, a high potential is applied to a p-type substrate (in the case of a well structure, an n-type substrate and a p-type well formed therein), and the control gate and select gate of the selected memory cell are set to 0V. Then, a high potential is applied to the control gate of the selected memory cell. As a result, electrons in the floating gate of the selected memory cell are emitted to the substrate, and the threshold value moves in the negative direction.

For data reading, a non-selected memory cell on the bit line side of the selected gate and the selected memory cell is turned on, and 0V is applied to the gate of the selected memory cell. At this time, by detecting the current flowing through the bit line,
A judgment of "0" or "1" is made.

Such a conventional NAND cell type EEPR
In the OM, in the data write mode, electrons tunnel from the substrate to the floating gate through the tunnel oxide film. Therefore, it is indispensable that the tunnel current flows stably without variation. This tunnel current largely depends on the grain size of the polycrystalline silicon forming the gate electrode. In order for the tunnel current to flow stably, the grain size at the oxide film interface should be small.

Generally, phosphorus-implanted polycrystalline silicon, which is currently used for the gate electrode of EEPROM, tends to have a larger grain size than arsenic-implanted polycrystalline silicon. Therefore, it is desirable to use arsenic-implanted silicon in order to stabilize the tunnel current characteristics.

On the other hand, considering the leak current between the floating gate and the control gate, the leak current decreases as the grain size at the interface of the polycrystalline silicon as the gate increases. Therefore, it is preferable to use phosphorus-implanted silicon.

Further, the processed shape at the edge of the floating gate is formed in an upwardly convex acute angle. Then, there is a problem that the withstand voltage between the floating gate and the control gate deteriorates due to the influence of this edge.

[0012]

As described above, the conventional EE
In PROM, polycrystalline silicon in which phosphorus is implanted as a floating gate has a large grain size and a small leak current between the floating gate and the control gate, but the tunnel current characteristic between the floating gate and the substrate becomes unstable. Further, in the case of arsenic-implanted polycrystalline silicon, the grain size is reduced and the tunnel current is stabilized, but the leak current is increased and the dielectric strength and the data retention characteristic of the memory cell are deteriorated. In other words, the characteristics of the tunnel insulating film and the floating gate
There is a problem that it is difficult to form the grain size of the gate electrode that optimizes both the characteristics of the inter-control gate insulating film.

The present invention has been made in view of the above circumstances, and an object of the present invention is to form a floating gate that satisfies both the tunnel insulating film interface and the floating gate / control gate insulating film characteristics. Another object of the present invention is to provide an EEPROM capable of improving the device characteristics and reliability.

[0014]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention forms a floating gate on a semiconductor substrate via a tunnel insulating film, and forms a control gate on the floating gate via a gate insulating film to form an electrically rewritable memory cell, In the nonvolatile semiconductor memory device in which a plurality of memory cells are integrated, (1) the floating gate is composed of a single-layer or multi-layer semiconductor film, and the semiconductor film is doped with a plurality of types of impurities.

(2) The floating gate is made of a single-layer polycrystalline silicon film, and the silicon film is doped with phosphorus and arsenic as impurities. (3) The floating gate is composed of a two-layer polycrystalline silicon film, the lower silicon film is doped with arsenic as an impurity, and the upper silicon film is doped with phosphorus as an impurity. It is characterized by that.

[0016]

According to the present invention, the floating gates are formed in the upper and lower two layers, and different impurities are doped into the floating gates.
At the upper interface of the floating gate, the grain size can be increased by phosphorus doping to reduce the leak current between the floating gate and the control gate. Further, at the lower interface of the floating gate, the grain size can be reduced by arsenic doping to stabilize the tunnel current. This makes it possible to satisfy both characteristics of the tunnel insulating film and the floating gate / control gate insulating film.

Also, by doping polycrystalline silicon as a floating gate with a plurality of types of impurities, good results that cannot be obtained by single doping can be obtained. In particular, when two kinds of phosphorus and arsenic are doped, the leak current between the floating gate and the control gate on the upper interface of the floating gate is suppressed to the same level as that of the p-doped floating gate, and the current variation in the tunnel oxide film on the lower interface is Leakage current after high electric field stress can also be suppressed. Therefore, it becomes possible to satisfy both the characteristics of the tunnel oxide film and the floating gate / control gate insulating film.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a NAND cell structure of an EEPROM according to an embodiment of the present invention, and FIG.
(B) is the AA ', BB' sectional drawing. Also,
3A and 3B are cross-sectional views of the first MOS transistor section (intermediate potential VM system) and the second MOS transistor section (high potential VPP system) of the peripheral circuit, and FIG. 4 is an equivalent of a NAND cell. Circuit.

In this embodiment, four memory cells M1 ...
M4s are connected in series in such a manner that the source and drain diffusion layers are shared by adjacent ones to form a NAND cell. Such NAND cells are arranged in a matrix to form a cell array. The drain at one end of the NAND cell is connected to the bit line BL via the selection gate S1, and the source line at the other end is also connected to the common source line (common source diffusion layer) via the selection gate S2. The control gates CG1 to CG4 of each memory cell are arranged in a direction intersecting the bit line BL to form a word line WL.

In this embodiment, one NAND cell is composed of four memory cells, but one NAND cell is composed of 2n (n = 1, 2, ...) Memory cells in one stage. Can also be configured.

M of concrete memory cell structure and peripheral circuit
The OS transistor structure is as shown in FIGS. In this embodiment, different p-type wells 2 and 21 which are the cell array region and the peripheral circuit region are formed on the n-type silicon substrate 1, and the cell array and the peripheral circuit are formed in these p-type wells 2 and 21. In this embodiment, four memory cells and two select gates are formed in a region surrounded by the element isolation insulating film 10 of the p-type well 2.

In each memory cell, the floating gate 4 is formed of the first-layer polycrystalline silicon film of 50 to 400 nm formed on the p-type well 2 through the tunnel insulating film 3 of the thermal oxide film of 5 to 20 nm. Has been done. The control gate 6 is composed of the second-layer polycrystalline silicon having a thickness of 100 to 400 nm formed on the floating gate 4 with the gate insulating film 5 made of a thermal oxide film having a thickness of 15 to 40 nm interposed therebetween.

Here, the floating gates of the memory cells formed of the first-layer polycrystalline silicon film have upper and lower two gates, as will be described later.
It is a stacked structure of steps and is formed by a polycrystalline silicon film into which ions of different types (phosphorus or arsenic) are implanted. Further, the gate insulating film 11 of the first MOS transistor of the peripheral circuit, the gate electrode 12a formed via the gate insulating film 13 of the second MOS transistor,
6a is the same as the control gate 6 of the memory cell.
This is due to the 0-nm second-layer polycrystalline silicon film.

The n-type diffusion layer 9 serving as the source / drain of each memory cell and MOS transistor is formed by ion implantation of arsenic or phosphorus after formation of each gate electrode.
N-type layer 9 serving as source / drain diffusion layer of memory cell
Are shared by adjacent ones, and four memory cells are connected in series. On the substrate on which elements are formed, C
The bit line 8 and the electrode wirings 23 in the peripheral circuit portion are formed of an Al film and covered with the VD insulating film 7.

In such a structure, the coupling capacitance C1 between the floating gate 4 of each memory cell and the substrate is
Is set to be smaller than the coupling capacitance C2 between the control gate 6 and the control gate 6. This relationship is as shown in FIG.
It is obtained by extending the floating gate 4 from the element region to the element isolation region.

The basic parameters will be described below.
According to the rule of pattern size of 1 μm, both floating gate 4 and control gate 6 have a width of 1 μm and a channel width of 1 μm.
And the floating gate 4 is 1 μm on both sides on the element isolation insulating film.
We are extending each. The tunnel insulating film 3 is, for example, a 10 nm thermal oxide film, and the gate insulating film 5 is 35 nm.
Is a thermal oxide film.

When the dielectric constant of the thermal oxide film is ε, C1 = ε / 0.02 C2 = 3ε / 0.035. Therefore, C1 <C2.

Next, a specific manufacturing process of the EEPROM of this embodiment will be described with reference to FIGS.
Note that these drawings mainly show the structure of the cell array portion.

According to a normal process, first, the p-type wells 2 and 21 are formed in the cell array region and the peripheral circuit region of the n-type silicon substrate 1 in separate steps with an optimum concentration for obtaining a required threshold voltage. . Next, as shown in FIG. 5A, the element isolation oxide film 10 is formed in the LOCOS process. Then, after forming a thermal oxide film as a tunnel insulating film, a first-layer first-stage polycrystalline silicon film 40a having a thickness of 100 nm, for example, is deposited and necessary impurities are doped. As a doping method, for example, 2 × 10 ²² cm ⁻³ arsenic is doped by ion implantation.

Next, as shown in FIG. 5B, a first layer first stage polycrystalline silicon film 4 is formed by photoresist processing.
0a is patterned to form the first-stage floating gate electrode 4 in the cell array portion by patterning. FIG. 5C shows FIG.
It is a top view of (b), and SDG is also shown simultaneously.

Next, as shown in FIG. 6A, a first-layer second-stage polycrystalline silicon film 40b is deposited to a thickness of 50 nm, for example, and an impurity species different from the first-stage doping is performed.
At this time, for example, phosphorus is doped by 1 × 10 ¹⁴ cm ⁻² ion implantation. This doping is not limited to phosphorus, and may be doping of arsenic, antimony, boron or the like, or doping of two or more kinds of dopants. Further, not only ion implantation but also diffusion may be used.

Next, as shown in FIG. 6B, for example, a photoresist process is performed so as to cover the first-layer first-stage polycrystalline silicon film 40a, and the first-layer second-stage polycrystalline film is subjected to CDE processing. The silicon film 40b is patterned to form slits in the first-layer second-stage polycrystalline silicon film 40b.
Thus, the first-layer second-stage floating gate electrode of the cell array portion is formed, and 40a and 40b are combined to form the floating gate 4 of the memory cell. FIG. 6C is a plan view of FIG. 6B, and SDG is also shown.

The first-layer polycrystalline silicon film can also be formed as follows. In the same manner as shown in FIG. 5A, the first layer first stage polycrystalline silicon film 40.
After a is deposited and doping is performed, for example, silicon nitride is deposited as shown in FIG. 7, and then patterning is performed. Thereafter, the first-layer second-stage polycrystalline silicon film 40b is deposited in the same manner as described above. The following is the same as the above process.

The film formed between the first stage and the second stage is, for example, a silicon oxide film or a silicon oxynitride film (Si
Any material that can serve as a diffusion barrier for impurities such as OxNx) may be used. Further, a natural oxide film having a film thickness of about 1 nm may be used.

Now, the process shown in FIG. 6B or the process shown in FIG.
After the step shown in, a thermal oxide film of, for example, 30 nm is formed as a gate insulating film on the first-layer polycrystalline silicon film. Then, the cell array is covered with photoresist.

Then, using this photoresist as a mask, the first-layer polycrystalline silicon in the peripheral portion is etched by CDE, and the gate insulating film in the peripheral region is etched by ammonium fluoride treatment. M
45 nm thermal oxide film for OS transistor,
A thermal oxide film of 25 nm, for example, is formed for the second MOS transistor. Then, a second layer polycrystalline silicon film is deposited. The second layer polycrystalline silicon film is doped with desired impurities. There are various methods for this doping as in the case of the first-layer polycrystalline silicon.

Next, a photoresist is patterned to cover the control gate region and the peripheral transistor region of the memory cell. Then, using this photoresist, the second
The layer polycrystalline silicon film and the first layer polycrystalline silicon film thereunder are selectively etched to simultaneously pattern the control gate and the floating gate in the cell array region.

Thereafter, a photoresist for gate patterning in the peripheral transistor region is patterned. Then, using this photoresist as a mask, the second-layer polycrystalline silicon film in the peripheral transistor region is selectively etched to form a gate pattern. Then, ion implantation of impurities is performed to form an n-type layer to be a source / drain diffusion layer. Then, the EEPROM is completed through a normal interlayer insulating film forming process.

Next, the NAND cell type EEP of this embodiment will be described.
The operation of the ROM will be described. First of all, data deletion is NAN
Batch erasing is performed on the memory cells forming the D cell. Therefore, in this embodiment, the control gates CG1 and CG4 of all the memory cells in the NAND cell are set to 0V,
The boosted high potential VPP (for example, 18V) is applied to the n-type substrate 1 and the p-type well 2. Further, the high potential VPP is applied to the gate electrodes SG1 and SG2 of the first and second selection gates S1 and S2 and the bit lines BL1 and BL2. As a result, the control gates of all memory cells and the p-type well 2
An electric field is applied between them, and electrons are emitted from the floating gate 4 to the p-type well 2 by a tunnel current. As a result, the threshold values of all the memory cells M1 to M4 are moved in the negative direction and become "0".

Next, data writing is sequentially performed from the memory cell on the source line side in the NAND cell, that is, the memory cell M4 farther from the bit line. Now, memory cell M
The case where the "1" data is selectively written in 4 will be described. The gate electrode S of the second select gate S2 on the source side will be described.
G2 is set to 0V, the high potential VPP is applied to the control gate CG4, and the remaining control gates CG1 to CG3 and the gate electrode SG1 of the drain side first selection gate S1 are between the power supply potential VCC and the high potential VPP. Intermediate potential VM (eg (1 /
2) VPP) is applied. Further, 0 V is applied as the "L" level potential to the selected bit line BL1 and the intermediate potential VM is applied to the non-selected bit line BL2. The p-type well is set to 0V and the n-type substrate is set to Vcc.

As a result, in the selected cell,
0V of the bit line BL1 is transmitted to the drain, a high electric field is applied between the bit line BL1 and the control gate, and electrons are injected into the floating gate. As a result, in the selected cell, the threshold value moves in the positive direction and "1" is written. The other memory cells M1 to M3 connected to the bit line BL1 are in the write mode, but the electric field thereof is small and the threshold value does not change. CG1 on the non-selected (or "0" write) bit line BL2 side
In the layer memory cell in CG3, the control gate has an intermediate potential V
M, channel potential is Vcc, and the potential difference is 3-4V
However, there is no threshold change. Bit line BL2
The memory cell along CG4 on the side is also in the write mode, but its electric field is also small and there is no threshold change.

When writing to the selected memory cell is completed in this manner, the memory cell immediately above in the NAND cell is similarly written to M3, and writing is sequentially performed to the memory cells M2 and M1. Be seen.

The data read operation will be described with reference to the memory cell M4.
V2 is applied to G2, Vcc is also applied to the control gates CG1 to CG3 of the unselected memory cells M1 to M3 as a potential for turning on the memory cells in the "1" state, and the control gate CG4 of the selected cell is set to 0V. It is said that Then, a read potential of 1 to 5V is applied to the bit line BL1 connected to the selected cell, and the other non-selected bit line BL2 is set to 0V. As a result, data "0" or "1" is discriminated depending on whether or not a current flows through the bit line BL1.

According to this embodiment, the portion of polycrystalline silicon in contact with tunnel insulating film 3 is arsenic-doped silicon having a relatively small grain, and the portion of polycrystalline silicon in contact with gate insulating film 5 has a relatively large grain. It is possible to realize the floating gate 4 which is phosphorus-doped polycrystalline silicon. Therefore, the leakage current between the floating gate 4 and the control gate 6 can be reduced, and the tunnel current characteristic can be stabilized, so that the reliability E which has not been obtained in the past can be obtained.
EPROM is obtained. In addition, by forming the floating gate 4 with two layers of polycrystalline silicon, the processed shape at the edge of the floating gate 4 can be rounded, which causes a problem such as deterioration of withstand voltage between the floating gate 4 and the control gate 6 due to the edge. It can be prevented in advance. (Embodiment 2) In this embodiment, the floating gate is not formed of a two-layer poly, but is formed of a single-layer poly, and two kinds of phosphorus and arsenic are used as impurities to be doped.

First, similarly to the first embodiment, a polycrystalline silicon film 40 was deposited as shown in FIG. 8 (a). Then, phosphorus was doped at 3 × 10 ¹⁵ cm ⁻² and arsenic was doped at 3 × 10 ¹⁵ cm ⁻² . As a doping method, for example, diffusion at 850 ° C. or ion implantation may be used.

Next, as shown in FIG. 8B, the first-layer polycrystalline silicon film 40 is patterned by photoresist processing to pattern the floating gate electrodes 4 in the cell array portion. FIG. 8C is a plan view of FIG. 8B, and SDG is also shown.

The respective characteristics of the case of using the two-type doped floating gate as in this embodiment and the case of using the conventional single-doped floating gate were examined. As a result, the following facts were revealed.

As shown in FIG. 9, the leakage characteristic of the tunnel insulating film after the high stress application is much better in the arsenic single-doped layer than in the phosphorus single-doped layer. When phosphorus and arsenic were doped at a ratio of 1: 1, a value close to that obtained by arsenic alone was obtained. That is, doping the floating gate with arsenic has the effect of reducing the leak current. In FIG. 9, ΔVG on the vertical axis is the difference between the initial voltage and the voltage after stress application, and here is 1 × 10 5.
^-11 is the difference between the voltages at which the current flows.

On the other hand, the leakage current between the floating gate and the control gate is smaller in the phosphorus single doping than in the arsenic single doping.
When doped with 1, the value obtained was closer to that of phosphorus alone than that between the phosphorus alone and arsenic alone.

Further, as shown in FIG. 10, the sheet resistance is smaller in the phosphorus single doping than in the arsenic single doping, but the phosphorus and arsenic are doped 1: 1 as in the present embodiment. In that case, it was closer to that of phosphorus-doped alone than the intermediate between phosphorus-only doped and arsenic-only doped.

As described above, according to the present embodiment, by doping both phosphorus and arsenic as impurities for doping the polycrystalline silicon film as the floating gate, for example, by doping at 1: 1, the tunnel current can be increased more than the phosphorus doping alone. The stability of the tunnel current was significantly improved, and the tunnel current stability similar to that of arsenic-doped alone was obtained. Furthermore, the leakage current was much smaller than that of arsenic-doped alone, and the floating gate-control gate leakage current characteristics similar to those of phosphorus-doped were obtained. (Reference Example) Here, the results of measuring the relationship between the impurity doping amount, the gate voltage, the leakage current with respect to the annealing time, the charge amount causing dielectric breakdown, the read disturb time, etc. will be described.

FIG. 11 is a characteristic diagram showing the relationship between the dose of ion implantation into the gate poly-Si and the stress leak current (when an electric field of 5 MV / cm is applied). The thickness of the gate oxide film is 8 nm, and the stress electric field is constant current ± 100 mA / cm.
^{It was set to 2.5} seconds. A is the one in which the gate side is negative, stress is applied, and the gate side is positive, and the IV characteristics are measured,
B shows the IV characteristic measured with the gate side positive and stress applied and the gate side negative, and C shows the IV characteristic measured with the gate side positive and stress applied. The measured value, D, is obtained by applying stress with the gate side being negative and applying the stress with the gate side being negative.

As can be seen from this figure, in the case of A, the leak current decreases as the ion implantation dose amount decreases. 5 × 10 ^{15 for} both P (phosphorus) and As (arsenic)
A dose amount of cm ⁻² or less, that is, an impurity concentration of 3.3 × 10 ²⁰ cm ⁻³ or less is desirable.

FIG. 12 is a characteristic diagram showing the relationship between the dose amount of P as an impurity ion-implanted into the gate poly-Si and the stress leak current (when an electric field of 5 MV / cm is applied). The thickness of the gate oxide film and the stress electric field were the same as in the case of FIG. A is the one in which the gate side is negative, stress is applied, and the gate side is positive, and the IV characteristics are measured, B
Shows the IV characteristic measured with the gate side being positive and the stress being applied and the gate side being negative.

As can be seen from this figure, in the case of A, the stress leak depends on the P concentration. It is preferable to lower the P concentration as much as possible and supplement the impurities with As. Furthermore, As
It is better to dope only.

FIG. 13 shows the relationship between the impurity dose amount and the charge amount causing dielectric breakdown, that is, TDDB (Time-Depende).
FIG. 6 is a characteristic diagram showing the dependence of nt Dielectric Breakdown) characteristics on the ion implantation dose amount. The thickness of the gate oxide film and the applied stress were the same as in the case of FIG. A indicates that the gate side is positive and stress is applied, and B indicates that the gate side is negative and stress is applied. As can be seen from this figure, like the stress leak, the lower the impurity concentration, the longer the life with positive stress on the gate side and the shorter the life with negative stress on the gate side. That is, if the stress leak is large, the TDDB life becomes short, and if the stress leak is small, T
The DDB life is extended.

FIG. 14 is a characteristic diagram showing the relationship between the voltage applied to the gate and the read disturb time. As can be seen from this figure, as the gate voltage decreases, the read disturb time increases, and when the W / E cycle is small (10 ² ), As and P have almost the same characteristics. However, when the number of W / E cycles is large (10 ⁶ ), As-doped is superior to P-doped.

FIG. 15 is a characteristic diagram showing the relationship between the annealing time (annealing temperature is 950 ° C.) and the leak current.
Gate oxide film thickness is 8nm, stress is constant current ± 10
0 mA / cm ² , 3 sec, and the dose amount is 3 × 1
0 ¹⁵ cm ^-2 , and the annealing temperature was 1000 ° C. Also,
That has been previously annealed at 1000 ° C. for 20 minutes,
Two types, which were not annealed, were measured.

A is a characteristic in which the gate side is negative and stress is applied and the gate side is positive and the IV characteristic is measured. B is the gate side is positive and stress is applied and the gate side is negative and I-. This is a measurement of V characteristics. As can be seen from this figure, with respect to the sample which was not annealed at 1000 ° C., the leakage current decreased as the thermal process was lowered (the annealing time was shortened). (Embodiment 3) In the NAND type EEPROM, the voltage VPP applied to the control gate at the time of writing needs to be as high as about 20V. Generally, VFG = {C1 / (C1 + C2)} VPP C1: capacitance between floating gate and control gate C2: capacitance between floating gate and substrate VFG: potential of floating gate In order to lower C1, it is necessary to increase C1 / (C1 + C2), that is, C1. Therefore, in this embodiment, the space of the floating gate in the word line direction is made smaller than the minimum processing size.

First, as shown in FIG. 16A, the substrate 6
After the element isolation oxide film 62 and the tunnel insulating film 63 are formed on the first surface, the first layer first stage polycrystalline silicon film 64 is deposited on them. Then, after doping desired impurities, patterning is performed by photoresist processing to pattern the first-stage floating gate of the cell array portion.

Next, as shown in FIG. 16B, after removing the photoresist 66, a second stage polycrystalline silicon film 65 is deposited and desired impurities are doped. Subsequently, a photoresist 66 is applied and formed, and is shifted from the pattern of the first-stage polycrystalline silicon 64 to process the photoresist.

Next, as shown in FIG. 16C, the first layer second stage polycrystalline silicon film 65 is formed by, eg, RIE processing.
Is patterned to form slits in the first-layer polycrystalline silicon film. Thus, the first-layer second-stage floating gate electrode of the cell array portion is formed, and 64 and 65 are combined to form the floating gate of the memory cell. After this, FIG.
As shown in (d), the thermal oxide film 6 as a gate insulating film
A control gate made of the second-layer polycrystalline silicon film 68 is formed via 7.

As described above, in this embodiment, since the pattern removal portions of the first and second steps of the first-layer polycrystalline silicon film are shifted, the space portion of the floating gate is made smaller than the minimum pattern size. Can be made smaller. As a result, the capacitance between the floating gate and the substrate can be sufficiently increased, and the voltage applied to the control gate during writing can be lowered.

Although the above-mentioned embodiment uses the LOCOS for element isolation, a memory cell using trench isolation as shown in FIG. 17 can be manufactured in the same manner. In FIG. 17, 69 indicates an interlayer insulating film and 70 indicates a bit line. (Embodiment 4) In this embodiment, the capacitance between the floating gate and the substrate is increased by leaving the side wall.

As shown in FIG. 18A, a polycrystalline silicon film 84 as a floating gate is formed to a thickness of, for example, 200 nm on a substrate 81 having a TEOS 83 buried in an element isolation trench, with a tunnel oxide film 82 interposed therebetween. Subsequently, a SiN film 85 as a mask is formed to have a thickness of 200 nm, for example, and this is selectively etched by photoresist processing to form a slit. Further, a SiN film 86 is deposited to a thickness of 100 nm, for example.

Then, as shown in FIG.
By performing RIE on the N film 86, the SiN film 86 is left on the sidewall of the SiN film 85. As a result, the SiN mask has slits smaller than the minimum pattern size.

Then, as shown in FIG.
The polycrystalline silicon film 84 is selectively etched using the N films 85 and 86 as a mask to form a floating gate. Then, as shown in FIG. 18D, the SiN films 85 and 86 are peeled off. After that, a control gate is formed by depositing a polycrystalline silicon film via an insulating film and further patterning the polycrystalline silicon film.

As described above, in this embodiment, even if the floating gate is a single layer, the technique of leaving the side wall is used,
A slit smaller than the minimum dimension of lithography can be formed, the capacitance between the floating gate and the substrate can be increased, and the voltage applied to the control gate at the time of writing can be lowered.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be carried out without departing from the scope of the invention. In the embodiment, a polycrystalline silicon film is used as the semiconductor film forming the floating gate, but other semiconductor materials can be used. Further, the impurity species to be doped in the polycrystalline silicon film is not limited to phosphorus and arsenic, and can be changed appropriately according to the specifications.

[0070]

As described above in detail, according to the present invention, by selecting a plurality of impurity species to be doped into the semiconductor film as the floating gate, the tunnel insulating film interface and the floating gate / control gate insulating film are formed. A floating gate satisfying both characteristics can be formed, and an EEPROM capable of improving the element characteristics and reliability can be realized.

[Brief description of drawings]

FIG. 1 is a NAND of an EEPROM according to a first embodiment.
The top view which shows a cell structure.

FIG. 2 is a view showing a cross section taken along the line AA ′ and BB ′ of FIG.

FIG. 3 is a cross-sectional view showing a configuration of a transistor portion of a peripheral circuit.

FIG. 4 is an equivalent circuit diagram of the NAND cell according to the first embodiment.

FIG. 5 is a diagram showing a manufacturing process of the NAND cell of the first embodiment.

FIG. 6 is a diagram showing a manufacturing process of the NAND cell of the first embodiment.

FIG. 7 is a diagram showing a modification of the first embodiment.

FIG. 8 is a view showing a manufacturing process of the NAND cell of the second embodiment.

FIG. 9 is a diagram showing a relationship between an impurity doping amount and tunnel current characteristics.

FIG. 10 is a diagram showing a relationship between an impurity doping amount and a sheet resistance.

FIG. 11 is a diagram showing a relationship between an impurity doping amount and a leak current.

FIG. 12 is a diagram showing a relationship between a doping amount of phosphorus as an impurity and a leak current.

FIG. 13 is a diagram showing a relationship between an impurity doping amount and a charge amount causing dielectric breakdown.

FIG. 14 is a diagram showing a relationship between a gate voltage and a read disturb time.

FIG. 15 is a diagram showing a relationship between annealing time and leak current.

FIG. 16 is a diagram showing a manufacturing process of the NAND cell according to the third embodiment.

FIG. 17 is a diagram showing a modification of the third embodiment.

FIG. 18 is a view showing a manufacturing process of the NAND cell of the fourth embodiment.

[Explanation of Codes] 1 ... N-type silicon substrate 2, 21 ... P-well 3 ... Tunnel insulating film 4 ... Floating gate 5 ... Gate insulating film 6 ... Control gate 7 ... CVD insulating film 8 ... Bit line 10 ... Element isolation insulation Film 11 ... Gate insulating film 6a, 12a ... Gate electrode 23 ... Electrode wiring 40a ... 1st layer 1st stage polycrystalline silicon film 40b ... 1st layer 2nd stage polycrystalline silicon film 41 ... SiN film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Riichiro Shirata 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (3)

[Claims] 1. A floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed on the floating gate via a gate insulating film to form an electrically rewritable memory cell. In the nonvolatile semiconductor memory device in which a plurality of memory cells are integrated, the floating gate is formed by doping a semiconductor film with a plurality of impurity species. 2. A floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed on the floating gate via a gate insulating film to form an electrically rewritable memory cell. In the nonvolatile semiconductor memory device in which a plurality of the memory cells are integrated, the floating gate is made of a single-layer polycrystalline silicon film, and the silicon film is doped with phosphorus and arsenic as impurities, respectively. Nonvolatile semiconductor memory device. 3. A floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed on the floating gate via a gate insulating film to form an electrically rewritable memory cell. In the nonvolatile semiconductor memory device in which a plurality of memory cells are integrated, the floating gate is composed of a two-layer polycrystalline silicon film, the lower silicon film is doped with arsenic as an impurity, and the upper silicon film is doped with an impurity. A non-volatile semiconductor memory device, characterized in that it is doped with phosphorus.