JPH0798675A - Error processing system for bus extension controller - Google Patents

Abstract

PURPOSE:To shorten a delay time at the time of receiving an access request to an extended bus from a central processing unit, and activating an extended bus cycle by a bus extension controller. CONSTITUTION:When the abnormality of the request address of a common bus address line 11 is not detected, a bus timing converting part 40 operates an address signal interface 10 and a control signal interface 30 without waiting the error check of write data, and activates the extended bus cycle. When the error of write data is detected by an error detecting part 50, a write designation from the bus timing converting part 40 is converted into a read designation by a read/write converting part 60, and outputted to an extended bus read/write control line 32, while a data signal interface 20 is interrupted. Thus, an access which is originally write can be converted into read, and the writing of the error data can be prevented. When the error is not detected, the write cycle is started as it is, and a delay until the extended bus cycle is started is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error processing system for a bus expansion controller, and more particularly to an error generated when an access request from a central processing unit to an input / output device or a storage device connected to an expansion bus is relayed. The present invention relates to an error processing method for a bus expansion controller.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a general structure of an information processing apparatus using an expansion bus. The central processing unit 1, the main storage device 2 and the bus expansion control device 3 are connected to the common bus 5, and access to the input / output device or the storage device 4 connected to the expansion bus 6 is performed by the bus expansion control device 3
Done through.

The common bus 5 includes an address line and a data line,
Each of the control lines transmits a bus cycle start designation, a read / write designation, and a bus cycle end designation (referred to as a bus control signal), and corresponds to a write cycle and a read cycle, respectively, in synchronization with a single-phase clock. It is a synchronous bus that operates as shown in.

When data is read (read) or written (write), from the central processing unit 1, the request address is an address line and "0" indicating the start of the bus cycle is the bus cycle start control line at the timing T1. Then, at timing T2, "1" or "0" is output to the read / write control line in response to the designation of read or write. Each control line can be in three states of “0”, “1” and high impedance, but the read / write control line is set to the state of “1” corresponding to the read designation when the start of the bus cycle is instructed. Is set. When the bus cycle start processing is completed, the bus cycle start control line and the bus cycle end control line are set to T
At both timings, the state becomes "1" indicating that the bus cycle is in progress.

At the T3 timing, when "0" indicating the end of the bus cycle is issued to the bus cycle end control line, the bus cycle ends at the T4 timing. During this period, in the case of a write cycle, from T2 timing to T4
The write data is output to the data line until the timing, and in the case of the read cycle, the read data on the data line is read from the T3 timing to the T4 timing. The bus cycle is continued by outputting "1" to the bus cycle end control line (period represented by Tw).
be able to.

In the conventional error processing method of the bus expansion control device, when relaying an access request to an input / output device or a storage device connected to the expansion bus, necessary information such as address and data received from the central processing unit When an error is detected, the bus expansion control device performs an operation of suppressing an access request to be output to the expansion bus.

FIG. 6 is a block diagram showing the configuration of a conventional bus expansion control device. In FIG. 6, the address signal interface 10 operates to receive a request address from the common bus address line 11 and output it to the extension bus address line 12. The operation of the address signal interface 10 is controlled by the address output control line 13. The data signal interface 20 receives data from the common bus data line 21 and receives the data from the extension bus data line 22.
And the operation of receiving data from the expansion bus data line 22 and outputting it to the common bus data line 21. The data signal interface 20 is a bidirectional interface, and the data transfer direction and output control are performed by the data direction control line 24 and the data output control line 23, respectively. The control signal interface 30 is an interface that outputs a bus control signal from the bus timing conversion unit 40a to the extension bus, and the extension bus cycle start designation received via the start designation relay line 44 is output to the extension bus cycle start control line 31. , Read / write relay line 45
The extended bus read / write designation received via a is output to the extended bus read / write control line 32. The output control of the control signal interface 30 is performed by the control signal output control line 46.

The bus timing conversion unit 40a is a control unit that adjusts the transmission timing of the bus control signal and outputs the control signal to each interface, and the common bus cycle start control line 41 and the common bus read / write control line 42.
And the extended bus cycle end control line 33, which receives a common bus cycle start designation, a common bus read / write designation, and an extended bus cycle end designation, respectively, and an extended bus cycle start designation, an extended bus read / write designation, and a common bus cycle end designation. Convert to and start designated trunk line 4
4, output to the read / write relay line 45a and the common bus cycle end control line 43. At the same time, “0” is output to the address output control line 13, the data output control line 23, and the control signal output control line 46 when the signals are transferred, and “1” is output when the signals are not transferred. , "0" and "1" are output to the data direction control line 24 corresponding to read / write.

The error detector 50 is a detector for checking the correctness of the address and data received from the common bus address line 11 and the common bus data line 21, and when an error is detected, the error detection signal line 51 is connected to the error detection signal line 51. "0" (normally "1") is output to output the bus timing conversion unit 40a.
To notify.

Next, the operation of the conventional bus expansion controller shown in FIG. 6 will be described. First, an error processing operation when the bus expansion control device detects an error in the write data in response to a write request from the central processing unit will be described.

FIG. 7 is a waveform diagram of the error processing operation of the bus expansion controller in this case. At t1 timing, the request address is input to the common bus address line 11, “0” is input to the common bus cycle start control line 41 to start the bus cycle, and at t2 timing, the write data is shared to the common bus data line 21. A write designation “0” is input to the bus read / write control line 42. The error detection unit 50 determines that the common bus address line 1
The error check of the request address received from 1 is performed, and the error check of the write data received from the common bus data line 21 is performed by the timing t3. When the error detection unit 50 detects an error in the write data,
At timing t3, "0" is output to the error detection signal line 51 to notify the bus timing conversion unit 40a. Upon receiving this, the bus timing conversion unit 40a
The operation of continuously outputting "1" to the address output control line 13, the data output control line 23, and the control signal output control line 46 is performed. As a result, the bus cycle is not started for the expansion bus, and the write request from the central processing unit is suppressed. Subsequently, at the timing t4, the common bus cycle end control line 4 is designated as the common bus cycle end designation.
"0" is output to 3, and the write cycle of the common bus is completed. During this time, there is no change in the data direction control line 24 and the previous state is maintained. The solid line in the figure shows the case where the previous state is write, and the broken line shows the case where the previous state is read.

Next, the operation when there are continuous write requests from the central processing unit and each write cycle operates normally will be described with reference to the waveform diagram of FIG.

At the u1 timing, the common bus address line 1
The request address is input to 1 and "0" is input to the common bus cycle start control line 41, and then at the u2 timing,
Write data is input to the common bus data line 21 and “0” for writing is input to the common bus read / write control line 42. As described above, the error detection unit 50 performs the error check of the request address by u2 timing.
Error check of write data is performed up to 3 timings.

When no error is detected, the error detector 50 continues to output "1" to the error detection signal line 51. In this case, the bus timing conversion unit 40a operates after checking the error detection signal output at the u3 timing, and therefore the address output control line 13 at the u4 timing.
Also, "0" is output to the control signal output control line 46, a request address is issued to the extension bus address line 12, and an extension bus cycle start instruction is issued to the extension bus cycle start control line 31 via the start designation relay line 44. Drive. At this time, "1" corresponding to the read designation is output to the extension bus read / write control line 32 via the read / write relay line 45a. Subsequently, at the u5 timing, "1" is output to the data direction control line 24, "0" is output to the data output control line 23, write data is output to the extension bus data line 22, and extension bus read / write control line 32 is output. The write designation “0” is output to, and the write processing on the expansion bus becomes possible. At this time, the extension bus cycle end control line 33 is held in the state of "1" indicating that the bus cycle is in progress.

Writing to the expansion bus is completed, and u7
At the timing, when the bus timing conversion unit 40a receives "0" indicating the extension bus cycle end designation from the extension bus cycle end control line 33, at the u8 timing, the address output control line 13, the data output control line 23, and the control signal output control "1" is output to the line 46, and the extension bus address line 12, the extension bus data line 22, the extension bus cycle start control line 31, and the extension bus read / write control line 3 are output.
The driving of the extension bus signal for 2 is stopped, and "0" which is the common bus cycle end designation is output to the common bus cycle end control line 43 to end the write cycle of the common bus.

Subsequently, when a write cycle for the common bus is started from the uA timing, a write cycle is generated for the expansion bus at the above timing.

The above is a description of the operation of the conventional expansion bus control device when the write cycle operates normally. As described above, the conventional error processing system is a system that does not generate a bus cycle in the expansion bus when an error is detected. Therefore, the expansion bus cycle is started after checking the necessary information, and a delay of 3 clock cycles is required from the start of the common bus cycle to the start of the expansion bus cycle.

[0018]

As described above, the conventional error processing method of the bus expansion control device relays the access request so that a bus cycle is not generated in the expansion bus even when an error in the write data is detected. Since this method suppresses the common bus cycle when an error is detected, the delay time is long and the processing speed is slow because the processing waits for the arrival of each required information during normal operation. there were. The method of simply increasing the operating clock frequency to increase the processing speed is as follows:
There is a problem that a high-speed hardware element is required and the cost becomes high.

An object of the present invention is to provide an error processing system for a bus expansion control device which can reduce the time required from the start of a common bus cycle to the start of an expansion bus cycle during a normal operation of a write request to the expansion bus. is there.

[0020]

The error processing method of the bus expansion controller of the present invention is a synchronous bus for relaying an access request from a central processing unit to an input / output device or a storage device connected to the expansion bus. In the error processing method of the extended control unit, if no error is detected in the address received from the central processing unit, the address is transferred to the extension bus to start an extension bus cycle, and the central processing unit continues from the address. When an error is detected in the received write data, the write designation received with the write data is converted into a read designation and output while the transfer of the write data to the expansion bus is suppressed,
The extension bus cycle is configured to end as a read cycle.

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a bus expansion controller using the present invention.

The bus expansion controller shown in FIG. 1 has an address signal interface 10 and a data signal interface 20 as in the conventional bus expansion controller shown in FIG.
And a control signal interface 30, a bus timing conversion unit 40, and an error detection unit 50. When the error detection unit 50 detects an error between the bus timing conversion unit 40 and the control signal interface 30. Is configured to include a read / write conversion unit 60 that converts a write designation from the bus timing conversion unit 40 into a read designation. Address signal interface 1 having the same reference numeral as in FIG.
0, the data signal interface 20, the control signal interface 30, and the error detection unit 50 have the same configuration and the same operation as the conventional device, but the bus timing conversion unit 40 is different from the bus timing conversion unit 40a of the conventional device in that If the address error check is normal,
The control signal is output to the address signal interface 10 and the control signal interface 30 without waiting for the error check of the write data to start the expansion bus cycle. The output of the error detection unit 50 is supplied to the bus timing conversion unit 40 and the read / write conversion unit 60 via the error detection signal line 51.
When "0" indicating the error detection is received from the error detection signal line 51, "0" indicating the write designation received from the bus timing conversion unit 40 via the read / write relay line 45 is changed to "1" indicating the read designation. The data is converted and output to the read / write conversion output line 61. The read / write conversion unit 60 is composed of, for example, an inverter and an OR gate, or an AND gate and an inverter, and when the error detection signal line 51 is normally “1”, the state of the read / write relay line 45 is directly changed to the read / write conversion output line. Output to 61.

Next, the operation of the bus expansion controller of FIG. 1 will be described. First, the error processing operation when an error is detected in the write data in the write request from the central processing unit will be described with reference to the waveform diagram of FIG.

At the v1 timing, the common bus address line 1
1 receives the request address and the common bus cycle start control line 41 receives "0" for starting the bus cycle,
At two timings, the write data is received from the common bus data line 21 and the write designation “0” is received from the common bus read / write control line 42. The error detection unit 50 checks the request address for errors by the timing v2.
The error check of the write data is performed by the v3 timing. If no error is detected in the request address, "1" is output to the error detection signal line 51 until timing v3, so the bus timing conversion unit 4
0 outputs “0” to the address output control line 13 and the control signal output control line 46 at the timing v3, and instructs the extension bus address line 12 to request the request address and the extension bus cycle start control line 31 to start the extension bus cycle. Output "0". At this time, a read designation "1" is output to the extension bus read / write control line 32.

When the error detection unit 50 detects an error in the write data, the error detection signal line 51 is issued at timing v3.
And outputs "0" to the bus timing conversion unit 40 and the read / write conversion unit 60. The bus timing conversion unit 40 follows the v3 timing and then the v4 timing.
"1" is output to the data direction control line 24 and "0" for writing is output to the read / write relay line 45. However, since the error detection signal line 51 is "0", the data output control line 2
Continuing to output "1" to 3, the drive of write data to the extension bus data line 22 is suppressed. Further, after the v3 timing, the read / write conversion unit 60 receives "0" of the error detection signal line 51, and even if the read / write relay line 45 becomes "0", it is converted into "1" and read / write converted. Output to the output line 61. Therefore, even if the read / write relay line 45 becomes "0" at the v4 timing, the extension bus read / write control line 32 remains in the state of "1", and it is as if a read cycle was started to the extension bus. appear.

At v6 timing, when read data is output from the specified address to the extension bus data line 22 and "0" is output to the extension bus cycle end control line 33 as an extension bus cycle end designation, the bus timing conversion unit 40 detects this, and outputs "1" to the address output control line 13 and the control signal output control line 46 at timing v7 to output the expansion bus address line 12, expansion bus cycle start control line 31 and expansion bus read of the expansion bus. / Light control line 3
The driving of the extension bus signal for 2 is stopped, and "0" is output to the common bus cycle end control line 43 to end the write cycle of the common bus.

The above is the error processing operation for the write data error of the bus expansion control device of the present embodiment. Instead of stopping the activation of the bus cycle for the expansion bus, it is changed to the read cycle when an error is detected. As a result, the write cycle of the write data is prevented from being performed and the bus cycle is ended. When an error is detected in the request address, the common bus cycle is terminated without starting the extended bus cycle.

Next, the operation when there are continuous write requests from the central processing unit and each write cycle operates normally will be described with reference to the waveform diagram of FIG.

The common bus signal from the w1 timing to the w8 timing is the same as in the case of FIG. 2 described above. If the error of the request address is not detected, the error detection unit 50 continues to output “1” to the error detection signal line 51, so that the bus timing conversion unit 40 outputs the address output control line 13 and the control signal output at the w3 timing. Control line 4
"0" is output to 6, and the extension bus signal shown in FIG. 3 is driven to the extension bus address line 12, the extension bus cycle start control line 31, and the extension bus read / write control line 32. If there is no error in the write data, error detection signal line 5
Since 1 continues the state of “1”, at the timing of w4, the bus timing conversion unit 40 causes the data direction control line 2
4, "1" is output to the data output control line 23, "0" is output to the read / write relay line 45, and write data "0" is output to the extension / bus relay line 45 to drive the write data to the extension bus data line 22. The respective control lines (31, 32, 33) are in the write cycle operating state. When the writing is completed and the "0" designating the end of the bus cycle is received from the extended bus cycle end control line 33 at the timing of w6, the bus timing conversion unit 40 sets the address output control line 13, at the timing of w7.
"1" is output to the data output control line 23 and the control signal output control line 46 to stop all extension bus signals, and "0" is output to the common bus cycle end control line 43 to write the common bus write cycle. To end.

When write access to the common bus is started again at timing w9, a write cycle is generated on the expansion bus at the timing described above. In this way, the time from the access request to the common bus to the generation of the write cycle on the expansion bus is shortened as compared with the conventional method.

[0032]

As described above, according to the error processing system of the bus expansion controller of the present invention, the expansion bus cycle can be started without waiting for the result of the error check of the write data. This has the effect of speeding up normal access.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a bus expansion control device using the present invention.

FIG. 2 is a waveform diagram for explaining an error processing operation of the present embodiment.

FIG. 3 is a waveform diagram for explaining a normal operation in response to a write request according to this embodiment.

FIG. 4 is a block diagram showing a general configuration of an information processing device using an expansion bus.

FIG. 5 is a waveform diagram for explaining a general operation of a synchronous bus.

FIG. 6 is a block diagram showing a configuration of a conventional bus expansion control device.

FIG. 7 is a waveform diagram for explaining an error processing operation of the conventional bus expansion control device.

FIG. 8 is a waveform diagram for explaining a normal write operation of the conventional bus expansion control device.

[Explanation of symbols]

 1 Central Processing Unit 2 Main Storage Device 3 Bus Expansion Control Device 4 Input / Output Device or Storage Device 5 Common Bus 6 Expansion Bus 10 Address Signal Interface 20 Data Signal Interface 30 Control Signal Interface 40, 40a Bus Timing Conversion Unit 50 Error Detection Unit 60 Read / write converter

Claims (1)

[Claims] 1. An address received from a central processing unit in an error processing method of a synchronous bus expansion control unit for relaying an access request from a central processing unit to an input / output device or a storage device connected to an expansion bus. If no error is detected, the address is transferred to the expansion bus, an expansion bus cycle is started, and if an error is detected in the write data received from the central processing unit following the address, the write data An error processing method for a bus expansion control device, characterized in that the write specification received together with the write data is converted into a read specification and output while the transfer to the expansion bus is suppressed, and the expansion bus cycle is ended as a read cycle. .