JPH0797907B2 - PWM inverter current controller - Google Patents

Description

The present invention relates to a current control device for a PWM inverter, and particularly to a current control device for a PWM inverter that is suitable for use in constructing an inexpensive and small PWM inverter. Regarding

[Conventional technology]

In a device such as a PWM inverter that obtains a desired output current by switching a DC voltage, current pulsation occurs due to the switching operation. Conventionally, as a method of obtaining a current detection value in which this pulsation component is reduced, for example, as described in JP-A-58-198165, current detection is performed in synchronization with a specific timing of a PWM signal serving as a reference for switching operation. It is known how to do it. In this method, by detecting the current in synchronization with the vicinity of the maximum positive and negative values of the carrier signal for generating the PWM signal,
It is based on the fact that the current value at the timing of approximately the midpoint of the flow or non-flow section of each switching element that constantly constitutes the inverter is obtained. Since the current value detected at this timing does not include the influence of current pulsation, it is not only effective when performing current control simply by a discrete calculation such as with a microprocessor, but also a smoothing filter for current pulsation in an analog current control system. Is also effective.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, as a means for detecting the phase current of each phase of the PWM inverter, an insulated type such as a current detector using a Hall effect element is used, whereby the actual phase current flowing in each phase Is being detected.

However, such an insulated current detector is more expensive than a shunt resistor generally used for current detection, and has a larger shape than a simple resistor. Become. Therefore, the PWM including the current detector
There is a problem that the configuration of the inverter cannot be downsized.

The present invention uses an inexpensive means using a shunt resistor as a PWM inverter current detector to obtain a stable detected current value with less current pulsation, and based on this detected current value.
An object of the present invention is to provide a more inexpensive and smaller current control device for a PWM inverter, which can control the output current of the PWM inverter so as to follow the current command value without a response delay.

[Means for solving problems]

The above-mentioned object is to connect a shunt resistor between a switching element on one side of an arm that constitutes a PWM inverter and the DC power supply, and to synchronize with a specific timing of a current flowing period of the switching element, the shunt resistor. The current detection means for detecting the phase current of the corresponding phase by sampling and holding the voltage across both ends, and the time-series data of the detected current value taken in synchronization with the specific timing of the conduction period of the switching element. Based on the above, by interpolating the current value between the detection timings, interpolation means for predicting the current in the conduction period of the switching element on the side opposite to the side where the shunt resistor is provided, and for each predetermined cycle, A current control for controlling the switching element of the inverter so that the detected current value from the current detection means or the interpolation means follows the current command value. It is achieved by providing a means. This timing is obtained when the switching element on the side provided with the shunt resistor is in the flow state in the vicinity of the maximum positive or negative value of the carrier signal used for generating the PWM signal.

[Operation] The switching operation of the PWM inverter is realized by alternately switching the two switching elements between the flowing state and the non-flowing state in the arm consisting of the upper and lower two switching elements provided for each phase. To be done. Therefore, when the arm of the PWM inverter on the side where the shunt resistor is provided is in the flow state, the current flowing therethrough is equal to the phase current, and the voltage drop across the shunt resistor corresponds to the phase current. However, in the non-flowing state, the phase current flows through the switching element of the arm on the opposite side, so that the voltage drop becomes zero and does not correspond to the phase current. According to the method of the present invention, a timing signal representing almost the midpoint of the flow section of the switching element on the side where the shunt resistor is provided is easily obtained, and this signal is used to sample the voltage drop of the shunt resistor.
By holding, the detected value that constantly represents the phase current is obtained. Moreover, this detected value is a value from which the influence of current pulsation is removed.

The present invention eliminates the influence of such current pulsation, and
Since the output current of the PWM inverter can be controlled based on the detected current value that is equivalently detected at a high sampling cycle by interpolation, the output current can be controlled without a response delay to the current command value.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention, in which 1 is a DC power source, 2 is an inverter main circuit, 3 is an AC motor, and 4 to 6
Is a shunt resistor, 7 to 9 are sample holders, 10 is a carrier signal generation circuit, 11 is a comparator, 12 to 14 are current control circuits, 18 is a pulse distribution circuit, and 19 is a pulse amplifier.

In the figure, the PWM inverter is composed of a DC power supply 1 and an inverter main circuit 2, and supplies its three-phase output current to the AC motor 3. Inverter main circuit 2 is U phase, V phase, W
It consists of three-phase and three-phase arms, and each arm is composed of switching elements that operate vertically and in pairs. Each switching element is a power transistor in the U-phase upper arm.
It consists of a parallel connection of Qup and flywheel diode Dup, and the latter is used to feed back the reverse current to the power transistor. The switching element is a power MOSFET (Metal Qxide Semiconductor type).
Field Effect Transistor) and GTO (Gate Turn Off Thy
ristor) can also be used. The U-phase lower arm and the V-phase and W-phase arms are similarly configured by using these switching elements.

With respect to the basic configuration of the inverter main circuit 2 as described above, shunt resistors 4, 5 and 6 are connected between the switching element of the lower arm and the negative side of the DC power source 1 for each phase,
The voltage drop due to the current flowing there is detected. This voltage is detected as a potential with respect to the negative side of the DC power supply 1 in the U phase, V phase, and W phase. The voltage V of the shunt resistors 4, 5 and 6 for each phase
_RU, V _RV, the sample holder 7, 8, 9 and V _RW in each phase, and held at a specific timing, is used as a detection signal representative of the phase of the phase current.

The hold signal for the sample holder is a carrier signal C of amplitude V _m generated by the carrier signal generation circuit 10.
_R is compared with an appropriate voltage level V _S (V _S <V _m ) by the comparator 11 and obtained. The voltage V _S is set near V _m , and the carrier signal C _R is sample holder 7,8,9 in the section where C _R > V _S.
Is set to the sample mode, and the value is held in the remaining section. A sample holder like this is a FET (F
It can be easily configured with the field effect transistor) and a capacitor, and in order to reduce the influence of the discharge of the capacitor, see, for example, Ohno, "Electronic circuit design that operates reliably" (CQ 57, CQ It goes without saying that you can also use op amp sample holders such as those found in publishers.

A current control circuit (ACR) for each phase using the current detection values i _du , i _dv , i _dw sampled and held at the timing described above
Current control is executed by 12, 13 and 14, and each output M _U , M _V , M _W
By comparing the carrier wave signal C _R with the carrier wave signal C _R , the PWM signals S _U , S _V , S _{W of} each phase are obtained. The pulse distribution circuit 18 generates an ON / OFF signal for each power transistor based on this PWM signal, and power-amplifies this ON / OFF signal with a pulse amplifier 19 to obtain an actual gate signal g _UP , g _UN , ..., g _WN . . By this signal, the switching operation of the power transistors Q _UP , Q _UN , ..., Q _WN forming the inverter main circuit is executed.

Next, the operation waveform of this embodiment will be described for the U phase.

FIG. 2 is an operation waveform diagram of the first embodiment of the present invention.

In the figure, the timing signal H _g obtained by comparing the carrier signal C _R with the amplitude V _m at the voltage level V _S has a period of T _c , and an interval of T _S near the positive maximum value of the carrier signal C _R. The pulse signal is only "1". Where T _c is the carrier period,
The voltage level V _S is set near V _m . On the other hand, U-phase PWM
The signal S _U is generated by comparing the carrier signal C _R with the U-phase ACR output M _U (which corresponds to the U-phase voltage command value). Based on this signal, the gate signals g _UP , g for turning on / off the power transistors Q _UP , Q _UN of the U-phase arm
_UN is obtained. Here, the section of "0" of this signal represents the OFF area and the section of "1" represents the ON area. By the switching operation of these power transistors Q _UP and Q _UN , the phase current i _{U of} U phase flows including a pulsating component.

In the region where the phase current i _U is positive, the gate signal g _UP is “1”.
At this time, the power transistor Q _{UP of the} upper arm is turned on, and a positive current is supplied from the positive side of the DC power supply 1. next,
When g _UP changes to “0”, Q _UP turns off, and g _UN becomes “1” accordingly. At this time, depending on the collector potential of the power transistor Q _UN , there are cases where Q _UN is turned on and cases where it is not turned on. In the former case, the U-phase potential is conducted to the negative side of the DC power supply, and the phase current flows through the DC power supply. In the latter, on the other hand, the phase current is the flywheel diode D _UN.
Flowing through. However, in both cases, the phase current in this region (where g _UN is “1”) corresponds to the current flowing through either Q _UN or D _UN . This relationship is
The same holds when the phase current i _U is negative. Therefore, when the shunt resistor is connected to the lower arm as in this embodiment, the voltage drop V _RU of the shunt resistor in the section where g _UN is “1” _always corresponds to the phase current i _U of the U phase. To do. Further, in the section where g _UN is “0”, the phase current flows through the power transistor Q _UP or the flywheel diode D _UP of the upper arm, and the voltage drop V _RU of the shunt resistor becomes zero. Now, the timing signal H generated by the above-mentioned means
_As described in the above publication (Japanese Patent Laid-Open No. 58-198165), g is almost at the midpoint of the “1” section of g _UN , and the period T _c of which the time T _S becomes “1” It is a pulse signal. Therefore,
By sampling the voltage of the shunt resistor in the “1” section of this signal and holding the value in the remaining section ( _Hg is “0” section), the voltage is kept constant regardless of the current flow state of the lower arm. The current detection value i _du obtained by removing the pulsating component is obtained. At this time, the time T when H _g becomes “1”
_S can be adjusted by changing the voltage level V _S and is set to be greater than the time it takes the sample holder to sample the voltage.

As described above in detail, according to the present embodiment, the current that generated the timing signal for sampling the voltage of the shunt resistor can be detected with a relatively simple circuit. The current control device used can be constructed at low cost.

Next, a second embodiment according to the present invention will be described with reference to FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.
Is a microprocessor, 21 is a PWM signal generator, 22 is a multiplexer, and 23 is an A / D converter. In the following embodiments, the same symbols as in FIG. 1 indicate the same parts.

In the first embodiment, the current detection circuit suitable for forming the analog current control circuit has been described, but in the following embodiments, the current control system is executed by using discrete arithmetic elements such as a microprocessor. A suitable circuit will be described. Microprocessor 20 interrupt processing is started by the rise of the timing signal S _H generated from the PWM signal generator 21, the phase of the shunt resistor 4, 5 and 6 of this when the voltage (the DC power source 1 at this time The negative side is used as a reference potential) is converted into a digital amount and is taken in. Therefore, the microprocessor 20 sequentially selects the voltages V _RU , V _RV , and V _RW of the shunt resistors by the multiplexer 22, and the A / D (Analog to Digit) is selected.
tal) converter 23 converts the corresponding analog voltage into digital data. The microprocessor 20 executes the control calculation from the detection value thus obtained and the separately set current command value, and sets the data thus obtained in the PWM signal generator 21. Each phase of the PWM signal based on the PWM signal generator 21 in the latest configuration data S _U, S _V, since continuously generate S _W, can achieve the desired current control process.

FIG. 4 is a detailed configuration diagram of the PWM signal generator in FIG. 3, where 20 is a microprocessor, 21 is a PWM signal generator, and 2
Reference numeral 4 is a clock pulse generator, 25 is an up / down counter, 26 and 27 are maximum and minimum value discriminating circuits, 28 is an OR circuit, 29 is a flip-flop, 30 is a register, and 31 is a comparator.

FIG. 4 shows the configuration of the PWM signal generator 21 for one phase (U phase). Therefore, by counting the clock pulse CLK generated from the clock pulse generator 24 by the up / down counter 25, the PWM signal is generated. To generate carrier data. At this time, the discrimination circuits 26 and 27, the OR circuit 2
8. The flip-flop 29 is used to switch the counting direction (up count / down count) of the up / down counter 25. The carrier wave data D _c thus obtained and the U-phase modulated wave data (data obtained as a result of the current control calculation) D _MU set in the register 30 by the microprocessor 20 are compared by the digital comparator 31. As a result, the U-phase PWM signal S _U is generated. Here, only the U phase is shown, but the same carrier data D _c is used for the other two phases as well. In this case, the signal S _H when switching from up-counting to down-counting is used as a timing signal of the current detection.

Next, the operation of this circuit will be described with reference to FIG.

FIG. 5 is an operation waveform diagram of the configuration of FIG.

In FIGS. 4 and 5, the count value D _c of the up / down counter 25 is compared with the data of the positive maximum value determination circuit D _H 26 and the data of the minimum value determination circuit D _L 27, that is, the negative maximum value data, A signal indicating the counting direction by switching the "0" and "1" levels of the flip-flop 29 with the OR signal (generated by the OR circuit 28) of the carry signal S _H and the borrow signal S _L for these two data setting values. S _F is obtained. Now, the desired carrier wave data D _c can be obtained by setting the count down in the region where the signal _SF is “0” and the count up in the region where the signal S _F is “1”. At this time, the carry signal S _H coincides with the timing of the positive maximum value of the carrier wave. Therefore, by detecting the voltage V _RU of the shunt resistor at this timing, current detection that corresponds to the layer current i _u constantly and is not affected by the current pulsation can be performed by the same principle as in the first embodiment. It will be possible.

In this embodiment, the voltage of the shunt resistor is captured at the time of the positive maximum value of the carrier signal for generating the PWM signal. It goes without saying that the detection value corresponding to the phase current can be obtained even if the values are shifted back and forth.

As described above in detail, in the second embodiment, a current control device for obtaining a detected current value by a current detection device using a shunt resistor and performing the discrete calculation of the detected current value by a microprocessor or the like. Is used, and it is possible to obtain the same effect as that of the first embodiment described above.

FIG. 6 is a block diagram of a PWM signal generator showing a third embodiment of the present invention, in which 20 is a microprocessor, 21 is a PWM signal generator, 24 is a clock pulse generator, 25 is an up / down counter, 26 , 27 is a discrimination circuit, 28 is an OR circuit, 29 is a flip-flop, 30 is a register, and 31 is a comparator. In the second embodiment described above, the circuit for detecting the phase current of the PWM inverter by taking in the voltage of the shunt resistor for each positive maximum value of the carrier signal has been described. In FIG. 6, the current value between the above detection timings is interpolated based on the values detected so far, and this is used as the current detection value at this point.

FIG. 6 has the same configuration as FIG. 5, and differs from FIG. 5 in that the borrow signal S _L is used as an interrupt signal for the microprocessor 20 in addition to the carry signal S _H. This operation will be described with reference to FIG.

FIG. 7 is an operation waveform diagram of FIG. 6, in which the microprocessor 20 synchronizes with the carry signal S _H and digitally outputs the voltage V _RU of the shunt resistor at a period T _c (T _C is a carrier period). D
Convert to _iU and _import . The data at this time are shown by white circles in the figure. Next, the microprocessor is interrupted at the timing of the borrow signal S _L which is out of phase with this carry signal by T _c / 2. Since this Taimungu not obtained the correct current detection values from the shunt resistors may be stored past detection data synchronized with S _H, by extrapolation from these data, the current detection at the timing of S _L Predict the value. This is indicated by a black circle. Now, as shown in FIG. 7, the detection timing is represented as k-1, k, k + 1, k + 2, k + 3, and the equation for extrapolation interpolation at the timing of k + 3 is shown in the following (Equation).

Here, a linear interpolation formula was used as the extrapolation. This is based on the fact that in normal operation, the carrier wave signal of the PWM signal is set sufficiently higher than the frequency of the current command value, so that it can be assumed that the current value between each detection timing changes linearly. In order to improve the accuracy of interpolation,
It goes without saying that quadratic interpolation and higher-order interpolation equations can be used by using the detection data obtained earlier.

As described in detail above, according to the present embodiment, the sampling cycle for current detection can be equivalently increased, and therefore, there is an advantage that the response of the current control system can be improved.

〔The invention's effect〕

As described above, according to the present invention, the output current of the PWM inverter can be detected by using the shunt resistor, and moreover, the detected value is a value obtained by removing the current pulsation component peculiar to the PWM inverter. Since an equivalently high sampling period can be obtained, an inexpensive and small current control device can be obtained. Then, by using such a current control device, the output slow current of the PWM inverter can be controlled with excellent relative positiveness with respect to the current command.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. FIG. 5 is a detailed configuration diagram of the figure, FIG. 5 is an operation explanatory diagram of the configuration of FIG. 4, FIG. 6 is a configuration diagram showing a third embodiment of the present invention, and FIG. 7 is an operation explanatory diagram of FIG. 1 ... DC power supply, 2 ... Inverter main circuit, 3 ... AC motor, 4-6 ... Shunt resistor, 7-9 ... Sample holder, 20 ... Microprocessor, 21 ... PWM
Signal generator, 23 ... A / D converter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiko Matsuda 4026 Kujicho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Hiroyuki Hanei 7-1-1 Higashi Narashino, Narashino City, Chiba Stocks Narashino Factory, Hitachi, Ltd. (56) References: Actual Development Showa 50-134617 (JP, U)

Claims (1)

[Claims] 1. A P inverter for controlling an AC output current of a PWM inverter in which an arm composed of two switching elements on an upper side and a lower side, which operate in pairs, is provided in parallel between DC power sources for three phases.
In a current control device for a WM inverter, a shunt resistor is connected between a switching element on one side of the arm and the DC power supply, and the shunt resistor is synchronized with a specific timing of a conduction period of the switching element. The current detection means for detecting the phase current of the corresponding phase by sampling and holding the voltage across both ends, and the time-series data of the detected current value taken in synchronization with the specific timing of the conduction period of the switching element. Based on the above, by interpolating the current value between the detection timings, interpolation means for predicting the current in the conduction period of the switching element on the side opposite to the side where the shunt resistor is provided, and for each predetermined cycle,
A current control device for a PWM inverter, comprising: current control means for controlling a switching element of the inverter so that a detected current value from the current detection means or the interpolation means follows a current command value.