JPH0795787B2 - Digital signal generator - Google Patents

Description

The present invention relates to a device for generating a digital signal corresponding to a desired analog signal, and more specifically, to a PBX (Private Branch Exchange), an electronic key telephone device, or the like. The present invention relates to a digital signal generator suitable for generating a digital signal corresponding to a dial tone, a ringback tone, a hold tone, a multi-frequency signal or the like required in a telephone device.

[Prior art and its problems] A telephone device such as a PBX or a key telephone device uses a dial tone signal that informs that the terminal telephone may be dialed, and the calling side indicates that the other party is calling. A circuit that generates a ringback tone signal to notify the telephone, a hold tone signal to notify the calling telephone of the hold, a multi-frequency signal for selecting the other party (hereinafter collectively referred to as a voice frequency signal). have. There are the following two typical representative generation methods of this audio frequency signal.

(1) Generating various audio frequency signals using an analog oscillator.

(2) For example, Japanese Patent Application Laid-Open No. 61-62245 (Japanese Patent Application No. 59-183)
As disclosed in 843), digital voice signals corresponding to various voice frequency signals are stored in a memory in advance, the digital voice signals are read from the memory according to a request, and D / A conversion is performed by a trunk or a terminal device. To do.

However, when the analog oscillator of (1) above is used, the configuration of the device becomes complicated. That is, a plurality of oscillators are required to generate various audio signals. In addition, PBX
When a telephone device such as a key telephone device or a key telephone device is configured by a digital PCM system, an A / D (analog / digital) converter must be provided after the analog oscillator.

When the memory of the above (2) is used, there is a problem that the capacity of the memory becomes large when many kinds of sounds or sounds having a long cycle are generated, which inevitably increases the cost.
In particular, in order to obtain the melody hold tone, the capacity of the memory must be considerably increased, so that it is practically difficult to obtain the melody hold tone by using the memory.

Therefore, the applicant has attempted to form a triangular wave or trapezoidal wave digital signal using an up-down counter. However, since it is a triangular wave or a trapezoidal wave and contains harmonic distortion components, it is necessary to provide a digital low-pass filter.

On the other hand, when the digital signal is transmitted to the output transmission line, it is desirable to start the transmission from the zero point (zero cross point) of the digital signal and to inhibit the transmission at the zero cross point. If the means for detecting the zero-cross of the output of the digital low-pass filter is provided, the above-mentioned zero-cross control becomes possible. However, providing the dedicated zero-cross detection circuit inevitably increases the cost of the device.

Therefore, it is an object of the present invention to provide a digital signal generator capable of easily performing zero-cross control.

[Means for Solving Problems] The present invention for solving the above problems and achieving the above object provides a clock signal generating circuit and an up-counting in response to a clock signal obtained from the clock signal generating circuit. An up-down counter for cyclically repeating an operation and a down-counting operation to generate a digital triangular wave signal, and a digital triangular wave signal obtained from the up-down counter or a harmonic distortion component of a signal whose amplitude is controlled. A digital low-pass filter, provided between the digital low-pass filter and the output transmission path,
A sample and hold circuit that samples the output of the digital low-pass filter at a predetermined frequency, holds and outputs only for a predetermined time, and a zero time point when the output digital signal of the digital low-pass filter has a periodicity of zero, A zero time point determination circuit determined by the output of the up / down counter, data transmission control signal supply means for giving a data transmission control signal indicating whether or not to transmit a digital signal from the sample and hold circuit, and the zero time point determination circuit. And a signal for controlling the sample-and-hold circuit so as to inhibit the transmission of data or release the inhibition of transmission by the data transmission control signal in synchronization with the zero time point. , The digital signal from the sample and hold circuit Those related to the digital signal generator consisting of a control circuit for controlling the delivery.

Incidentally, explaining the correspondence relationship with the later-described embodiment of the present invention, the clock signal generating circuit is a PLL circuit 35,
The up / down counter is an up / down counter 80 in the triangular wave generating circuit 34, the digital low-pass filter is a DLP filter 43, and the sample / hold circuit is an 8 kHz sample / sample at the output stage of the DLP filter 43.
A hold circuit 45, the zero point determination circuit is a zero delay pulse generation circuit 82 in the triangular wave generation circuit 34, the data transmission control signal supply means is the CPU 11, and the control circuit is an amplitude control signal generation circuit 38. And a signal transmission control circuit 91 in FIG.

[Operation] The zero point (zero cross) of the output of the up / down counter in the above invention does not coincide with the zero cross of the output of the digital low-pass filter. However, if the delay time of the digital low pass filter can be known in advance, the zero cross of the output of the digital low pass filter can be known from the output of the up / down counter. In the present invention, the zero cross of the output of the digital low-pass filter is determined based on the output of the up / down counter.
The zero cross can be detected very easily.

[Embodiment] Next, a button telephone device according to an embodiment of the present invention will be described with reference to the drawings. In addition, this embodiment will be described in order according to the following items.

(1) Outline of button telephone device (2) Outline of operation of button telephone device (3) Outline of digital signal generator (4) Triangle wave generation circuit (5) PLL circuit (6) Amplitude control signal generation circuit (7) Comparison slice circuit ( 8) DLP filter (9) Sample and hold circuit (10) Output control circuit 47 and adder 52 (11) Linear non-linear conversion circuit [(1) Button telephone device overview] Buttons shown in principle in FIG. 1 (A) The telephone device includes a main device 1 and a telephone as a plurality of terminal devices connected to the main device 1.
It consists of 2a, 2b, 2c, 2d, 2e and 2f. An external line, that is, a local line 3 is also connected to the main device 1. Therefore, the main unit 1 performs exchanges for the extension telephones 2a to 2f, and at the same time, the telephones 2a to 2f are exchanged.
Connect 2f to station line 3. The main device 1 includes a station line trunk 4 as an external line interface, an internal line trunk 5 as an internal line interface, a switching device 6, and a signal trunk 7.
And a highway bus 8 interconnecting them and a microcomputer 9.

The office line trunk 4 includes a device for A / D converting a signal input from the office line 3 and a D / A conversion for a signal output to the office line 3.

The switching device 6 includes a highway switch (call switch), and connects the extension telephones 2a to 2f to the office line 3 and mutually connects the extension telephones 2a to 2f.

The signal trunk 7 comprises a digital signal generator 10 of particular relevance to the present invention. The digital signal generator 10 time-divisions a dial tone signal, a ringback tone signal, a hold tone signal, and a multifrequency signal (DTMF) which is a signal corresponding to a dial number of 0, 1, 2 ... by dial operation. It is a circuit formed by. The digital signal generator 10 will be described in detail later.

The microcomputer 9 includes a CPU (central processing unit) 11 and a memory 12, and controls all the operations. In addition, memory
The dial sound generation condition data, the ringback sound generation condition data, the held sound generation condition data, and the multi-frequency sound signal generation condition data are written in the area 12 in advance. A signal line 13, a data bus 14, an address bus 15 and a signal line 16 connect the microcomputer 9 to the switching device 6 and the signal trunk 7. The signal line 13 has a data write pulse transmission function for instructing to write the audio frequency signal generation condition data read from the memory 12 under the control of the CPU 11 into the memory of the interface of the digital signal generator 10. The data bus 14 has a function of transmitting the audio frequency signal generation condition data read from the memory 12,
Further, it is used to give exchange data from the CPU 11 to the exchange device 6. The address bus 15 has a function of transmitting an address signal for writing the audio frequency signal generation condition data in the memory of the interface of the digital signal generator 10, and further, the bus 14 is provided in the exchange control memory included in the exchange device 6. It is used to transmit the write address signal of the exchange data supplied from.

In order to synchronize the digital signal generator 10 with the switching device 6, a synchronization signal line 17 and a clock signal line 18 are provided between them. Although illustration is omitted, a synchronizing signal line and a clock signal line are also provided between the switching device 6 and the office line and extension trunks 4 and 5.

Local and extension trunks 4, 5 and microcomputer 9
A control bus 19 to and from the trunk 11 performs time-divisional exchange of control signals between the trunks 4 and 5 and the CPU 11, and a destination selection signal (exchange data etc.) obtained by dialing the telephones 2a to 2f. ) To CPU11 and C
It is for giving a call signal or the like from the PU 11 to each of the telephones 2a to 2f. The CPU 11 creates data for controlling the switching device 6 in response to a destination selection signal obtained from the control bus 19, and when the destination is a station line, the control bus 19
Sends a selection signal to the trunk line trunk 4 and, if the other party is an extension telephone, sends a calling signal to the telephone via the control bus 19.

The highway bus 8 includes a plurality of upstream highways from each of the trunks 4, 5, and 7 to the switching device 6 and a plurality of downstream highways from the switching device 6 to the office line and the extension trunks 4 and 5. Since the signal trunk 7 does not need to be supplied with data from the switching device 6, it is not connected to the downlink highway.

As shown in FIG. 2 (A), the highway bus 8 is used after 125 μs is time-divided into 32 channels from 0 channel to 31 channel. Allocation time per channel (1
Since 8-bit data is transmitted in a time slot, the data transmission rate of the unit channel is 64 kilobits / second.

Telephones 2a to 2f connected to the extension trunk 5 via the transmission line 20
As shown in FIG. 1 (B), it has an A / D converter 21 for A / D converting the transmission signal and a D / A converter 22 for D / A converting the reception signal. Further, the telephones 2a to 2f are similar to ordinary telephones in that the telephone circuit 23, the transmitter 24, the receiver 25, the hook switch 26, the dial switch 27, and the ring tone generator.
28, a holding sound switch 29, and a CPU, a memory, a synchronizing circuit, and the like (not shown).

[Outline of (2) Button Telephone Device Operation] The operation when the telephone 2a calls a telephone (not shown) having an outside line is as follows. When the handset consisting of the transmitter 24 and the receiver 25 is lifted to dial the telephone 2a and the hook switch 26 is put into the off-hook state, this goes through the control transmission line 20, the extension trunk 5 and the control bus 19 to the CPU 11
In response to the off-hook, the CPU 11 reads the dial tone signal generation condition data from the memory 12 and supplies it to the digital signal generator 10. The digital signal generator 10 generates a dial tone signal determined based on the dial tone signal generation condition data in the form of a digital signal. The obtained dial tone signal is exchanged by the exchange device 6 and is sent to the extension trunk 5 through the highway bus 8 in a time division manner.
It is sent to the telephone 2a that is off-hook via the transmission line 20.
Since the telephone set 2a includes a D / A converter, the dial tone signal in digital form is converted into an analog signal. The time division transmission of the dial tone signal is performed according to FIG. That is, the second
As shown in FIG. 2B, when a synchronization signal is applied to the digital signal generator 10 from the synchronization signal line 17 in the time slot of channel 1 in FIG. 2A, as shown in FIG. The dial tone signal is synchronously output to the highway bus 8, exchanged by the exchange device 6, and sent to the telephone set 2a via the bus 8 and the extension trunk 5.

When a dial operation is performed on the telephone set 2a, a destination selection signal is generated and given to the CPU 11 through the transmission line 20, the extension trunk 5 and the control bus 19, and the CPU 11 responds to this by the digital signal generator 10 The switching device 6 is controlled so as to connect to the vacant office line 3. Further, the CPU 11 uses a digital multi-frequency signal (DT) corresponding to the selection signal given by the telephone 2a.
Condition data for generating MF) is read from the memory 12 and given to the digital signal generator 10. The digital signal generator 10 generates a multi-frequency signal having a frequency and an amplitude determined by the condition data, which is exchanged by the exchange device 6 and sent to the office line trunk 4 via the highway bus 8, where the office line trunk 4 is connected. Is converted to conform to 3. The selection signal 1 is, for example, a synthesized sound of a 697 Hz frequency signal and a 1209 Hz frequency signal. Therefore, the CPU 11 controls the digital signal generator 10 to simultaneously generate the above two frequency signals.
To control. Other multi-frequency signals, such as the selection signals 2-9 and 0, are generated in a similar manner. The minimum pause between each selection signal (multi-frequency signal) is obtained by controlling the signal transmission stop for a fixed time by the timer in the CPU 11.

When the call of the telephone of the outside line is started, a ringback tone signal is input from the exchange connected to the office line 3 to the office line trunk 4 via the office line 3. The trunk line trunk 4 confirms that the ringback sound signal is obtained via the control bus 19 to the CPU 1
Notify 1. In response to this, the CPU 11 reads the ringback sound signal generation condition data from the memory 12 and sends it to the digital signal generator 10. The digital signal generator 10 generates a digitized ringback tone signal containing frequency and amplitude information determined by the condition data, which is sent to the calling telephone 2a.

When the calling telephone 2a turns on the hold tone switch 29 after the call path with the calling telephone 2a is formed by off-hook of the called telephone, a signal indicating hold is transmitted to the transmission path 20,
It is given to CPU11 via extension trunk 5 and signal line 19, and C
The PU 11 reads out the holding tone signal generation condition data from the memory 12 and gives it to the digital signal generator 10. In response to this, the digital signal generator 10 creates a hold tone signal and sends it to the central line trunk 4. The station line trunk 4 converts the digital hold tone signal to analog and sends it to the receiving side telephone.

As is clear from the above, the dial tone signal is stored in the memory 12,
The ringback sound signal, the multi-frequency signal, and the hold sound signal are not written as they are, but the generation condition data (frequency control data, amplitude control data) are written.
Therefore, many signals can be generated with a small memory capacity.

In addition, the digital signal generator 10 is connected to a large number of terminal telephones 2a ...
Since it is used in 2f in a time division manner, it is possible to obtain signals for a large number of telephones by one digital signal generator 10. If there are many telephones 2a to 2f connected to the main device 1, a plurality of digital signal generators 10 are provided.

[(3) Outline of Digital Signal Generator] FIG. 3 shows the digital signal generator 10 of FIG. 1 (A) in detail. The digital signal generator 10 includes first and second audio signal digital signal generating circuits 30 and 31 having the same configuration. These are connected to a common CPU interface 32 and timing circuit 33.

The first digital signal generating circuit 31 has a triangular wave generating circuit 34 that generates a digital triangular wave signal corresponding to an analog triangular wave that is approximate to an analog audio frequency signal.
The triangular wave generating circuit 34 includes an up / down counter, and periodically generates a digital triangular wave signal by repeating up-counting and down-counting. In order to obtain audio signals of various frequencies, it is necessary to change the frequency of the triangular wave corresponding to the audio signal. Triangular wave generation circuit
The frequency of the triangular wave output from 34 can be changed by the clock of the up / down counter. Therefore, an analog PLL (Phase Locked Loop) circuit 35 is connected to the triangular wave generation circuit 34 by a line 36 as a variable clock signal generation circuit. The output frequency of the PLL circuit 35 for changing the pitch of the sound is set by the frequency control data read by the CPU 11 from the memory 12 of FIG. Therefore, the PLL circuit 35 includes the write signal line 13 of FIG.
It is connected to the CPU interface 32 to which the data bus 14 and the address 15 are connected by the bus 37 and outputs the frequency signal designated by the CPU 11.

Changing the maximum amplitude of the triangular wave changes the strength of the sound. However, it is difficult for the triangular wave generation circuit 34 to simultaneously control the frequency and the maximum amplitude of the triangular wave. Therefore, in this method, the triangular wave generation circuit 34 always generates a triangular wave having the same maximum amplitude, and then the triangular wave is sliced into a trapezoidal wave to change the amplitude. The amplitude control signal generation circuit 38 is a circuit for generating an amplitude control signal for slicing a triangular wave, and is the CPU interface 32 of FIG.
Connected to the bus 37. The amplitude control signal generation circuit 38 outputs an amplitude control signal (slice level signal) indicating a slice level corresponding to the amplitude control data given from the CPU 11 in FIG.

The comparison slice circuit 39 is connected to the triangular wave generation circuit 34 by the parallel transmission line 40, and is also connected to the amplitude control signal generation circuit 38 by the parallel transmission line 41. The comparison slice circuit 39 includes a digital comparison circuit, compares the triangular wave with the amplitude control signal (slice level signal), slices the triangular wave when the triangular wave exceeds the amplitude control signal, and outputs a trapezoidal wave. . From the comparison slice circuit 39, a digital signal including frequency information (pitch information) and amplitude information (sound intensity information) of the desired audio signal is obtained.

A digital low-pass filter 43 (hereinafter referred to as a DLP filter) connected to the comparison slice circuit 39 through a parallel transmission line 42.
Is to attenuate the harmonic distortion component of the digital signal.

Samples connected to the DLP filter 43 by parallel transmission line 44
The hold circuit 45 is a circuit that samples a digital signal at 8 kHz, holds the obtained sample, and outputs the sample.

The sample and hold circuit 45 is connected to the output control circuit 47 by the transmission line 46. A second digital signal generating circuit 31 for audio signals is also connected to the output control circuit 47 by a transmission line 48. Whether the output control circuit 47 executes addition of the first digital signal given from the transmission line 46 and the second digital signal given from the transmission line 48 based on the instruction of the CPU 11 in FIG. To decide. This addition is necessary when obtaining the chord of the multi-frequency signal and the melody holding tone. The output control circuit 47 is connected to the CPU interface 32 via the bus 37 to receive an addition instruction from the CPU 11,
Moreover, the timing circuit 33 of the input stage is connected by the signal lines 49a and 49b.
It is connected to the. First and second if addition is required
Of the digital signal of the above are simultaneously sent to the adder 52 by the transmission lines 50 and 51. When addition is unnecessary, the first and second digital signals are sent to the adder 52 at different timings.

A linear non-linear conversion circuit 58 connected to the output transmission line 57 of the adder 52 converts a linear digital signal into a non-linear digital signal, and the transmission line 59 produces first and second parallel serial (P / S) conversion registers. Input into 54 and 56. Each of the P / S conversion registers 54 and 56 serially converts the first and second digital signals or the added signal and sends them to the transmission lines 60 and 61. To implement this control, each register 54, 56
The signal lines 53a, 53b, 53c, 55a, 55b, 55c are connected to the output control circuit 47. The output transmission lines 60 and 61 become the bus 8 in FIG. 1 (A).

The digital signal generator 10 of FIG. 3 further includes a large number of signal lines 62, 63, 64, 65, 6 in order to operate the respective parts in association with each other.
6, 67, 68, 69, 70, 71, 72, 73. Also, the timing circuit 33 and the second audio signal digital signal generation circuit
31 is also provided with 31 as a signal line corresponding to the signal lines 36, 62, 66, 67, 71, 73 in the first digitized voice frequency signal generation circuit 30. There is.

Next, each part of FIG. 3 will be described in more detail.

[(4) Triangular Wave Generating Circuit] The triangular wave generating circuit 34 of FIG. 3 includes an up / down counter 80, a T-type flip-flop 81, a zero detecting circuit 79, and a zero delay pulse generating circuit 82 as shown in FIG. Become. The clock input terminal CK of the up / down counter 80 is connected to the PLL circuit 35 by the signal line 36, and the output terminal OUT is connected to the triangular wave data transmission line 40 and the zero detection circuit 79 and the zero delay pulse generation circuit 82. ing.
The zero detection circuit 79 is connected to the output terminal of the up / down counter 80, detects the zero time point of the output digital signal, and flips a zero detection pulse in the clock period of zero.
It is applied to the trigger input terminal T of 81 and the signal line 64. The Q output terminal of the flip-flop 81 is connected to the DLP of FIG.
It is connected to the filter 42.

The up / down counter 80 operates in a 192-ary system (n = 192), and if an analog triangular wave as shown in FIG. 5 (A) is required, it corresponds to FIG. 5 (B).
It outputs a digital triangular wave as shown in. When a clock pulse is input to the clock input terminal CK at the cycle Tc, the count value increases by one in response to each clock pulse, and the count value is n (decimal 192, hexadecimal C
When it becomes O), it counts down one by one, and when the count value becomes zero, it counts up again by one and outputs a digital signal (absolute value) of 8 bits to hexadecimal to the output terminal OUT. The period of the digital triangular wave is Ta / 2 with respect to the period Ta of the analog triangular wave, and the analog triangular wave takes both positive and negative values, whereas the digital triangular wave outputs only positive values. Therefore, the flip-flop 81 is triggered by a pulse indicating that the count value obtained from the zero detection circuit 79 has become zero, and the output of the flip-flop 81 is output every one cycle of the digital triangular wave as shown in FIG. 5 (C). Inversion is performed to obtain a 1-bit polarity signal (code signal) on the signal line 63. As a result, a loopback (fo) consisting of an 8-bit absolute value and a 1-bit polarity code
lded) format hexadecimal code is obtained.

FIG. 6 shows in detail the state of each part of FIGS. 3 and 4.
The output of the up / down counter 80 shown in FIG. 6 (B) changes every time the clock pulse of FIG. 6 (A) is input. Output signal line 63 of flip-flop 81 in FIG. 6 (C)
The value of changes as in FIG. 5 (C). The pulse of the signal line 64 shown in FIG. 6 (D) is generated corresponding to the period in which the counter value in FIG. 6 (B) becomes zero.

The zero-delay pulse generation circuit 82 is a circuit that detects 89 in hexadecimal, and a circuit that generates 89 in hexadecimal and 89 in hexadecimal.
And an output of the up / down counter 80, and a comparator circuit for generating a zero delay pulse when they match each other. Therefore, the count value is shown on the signal line 65 in FIG. 6 (E).
A pulse is generated when the hexadecimal number reaches 89. This zero-delay pulse generator corresponds to a position delayed by 0.71 × π / 2 from the zero-cross detection pulse of the digital triangular wave in FIG. 6 (D). The pulse in Fig. 6 (E) is DLP.
It is generated corresponding to the zero-cross of the digital signal of the output stage of the filter 42.

If the cycle T2 of the clock pulse of the up / down counter 80 is shortened, the repetition frequency of the digital triangular wave generation becomes high, and when this is D / A converted, a high frequency audio signal can be obtained. Therefore, it is possible to change the frequency (pitch) of a desired voice frequency signal such as a dial tone, a ringback tone, a hold tone, and a multi-frequency signal according to the cycle (frequency) of the clock pulse. The relationship between the cycle Ta of the analog triangular wave, the cycle Tc of the clock, and the maximum count value n is as follows.

Ta = 4 · n · Tc (1) In this embodiment, it is possible to generate a digital triangular wave so that the frequency of the analog triangular wave of FIG. 5 (A) is in the range of 168.0 Hz to 2666.7 Hz.

If the digital signal of the triangular wave is expressed in the folded digital signal format consisting of the absolute value and the polarity, the maximum count value n of the up / down counter 80 can be made half of the minimum to the maximum (peak-to-peak) of the analog triangular wave. As a result, downsizing and cost reduction of the up / down counter 34 can be achieved. Further, the slice processing in the comparison slice circuit 39 of FIG. 3 becomes easy.

[(5) PLL Circuit] As shown in FIG. 7, the PLL circuit 35 includes a phase comparison circuit 83, a loop filter 84, a VCO (voltage controlled oscillator) 85, and first and second frequency dividing circuits 86 with built-in registers. , 87 and. The phase comparator circuit 83 receives the reference input frequency signal of 8 kHz from the timing circuit 33 of FIG. 3 and the output frequency of the VCO 85 divided by the first divider circuit 86. If the reference input frequency is Fr and the frequency division ratio of the frequency dividing circuit 86 is N,
An NFr frequency signal can be obtained from VCO85. In this embodiment, the output of the VCO 85 is further frequency-divided by the second frequency dividing circuit 87 and sent to the signal line 36 as a clock signal. PLL
The circuit 35 has a function of setting the frequency of the audio signal. Frequency control data supplied from the CPU 11 in FIG. 1 is supplied to the frequency dividing circuits 86 and 87, and the CPU interface 32 and the bus 37 in FIG.
Enter via and. The frequency dividing circuits 86 and 87 are programmable dividers and are composed of programmable counters. The frequency dividing circuits are set to the frequency dividing ratio designated by the CPU 11 and overflow each time a predetermined value is counted to generate one pulse. The CPU 11 gives initial values to the counters of the frequency dividing circuits 86 and 87. When this initial value is changed, the division ratio changes and VC
The output frequency of O85 also changes. Of course, this PLL circuit 35
The dial tone, ringback tone, hold tone, and various frequencies within the range necessary for forming a multi-frequency signal can be output.

If the frequency dividing ratio can be changed significantly by the first frequency dividing circuit 86, the second frequency dividing circuit 87 is unnecessary, but
VCO85 by increasing the division ratio of the frequency divider circuit 86
There is a problem that the oscillation frequency range must be widened, and a problem that the jitter of the output signal of VCO5 increases because the multiple increases. So in this example,
A second frequency divider circuit 87 is provided, which allows the output of VCO85 to be 1/2, 1 /
Divide by 4 and 1/8 to get frequencies of 2, 3, and 4 octaves.
The output frequency range of the VCO 85 is 1.032MHz to 2.048MHz, and the frequency of the clock supplied to the triangular wave generation circuit 34 is VC.
Same as the output of O85 or 1/2, 1 / in the second frequency divider circuit 87
It is equivalent to the frequency divided into 4 and 1/8.

By the way, the reference input frequency of the phase comparison circuit 83 is 8 kHz.
Is used. By using 8 kHz in this way, aliasing noise at the time of sampling at 8 kHz in the sample and hold circuit 45 in the subsequent stage can be prevented. That is, since the triangular wave generating circuit 34 forms a digital signal by the up / down counter 80, it samples an analog triangular wave at the clock frequency fc = 1 / Tc and generates an output equivalent to that encoded. Clock frequency fc for the fundamental wave (sine wave) of triangular wave with frequency fa
If sampling is performed, frequency components such as fc-fa, fc + fa, 2fc-fa and 2fc + fa are newly generated as shown in the frequency spectrum of FIG. Therefore, the triangular wave generating circuit 34 generates a digital signal containing the frequency components shown in FIG. The harmonic distortion component of the digital triangular wave is the DLP filter 43
However, if a signal including the components shown in FIG. 8 is input to the sample and hold circuit 45 and is sampled again here, a new frequency component (noise) is generated based on this sampling. Now, when the frequency components fa, fc-fa, fc + fa, 2fc-fa, 2fc + fa shown in FIG.
(Fc + fa), 32kHz- (2fc-fa), 32kHz + (2fc + fa)
Frequency components such as By the way, the triangular wave generator 34
If the clock frequency fc in is set to any value other than an integral multiple of 8 kHz, the aliasing frequency component will be 0
Located at ~ 4kHz, it may generate noise or noise. However, in this embodiment, since the clock frequency fc is set to an integral multiple of 8 kHz, the sample and hold circuit
The aliasing frequency generated at 45 overlaps the fundamental wave frequency fa and is no longer perceived as an abnormal sound.

[(6) Amplitude Control Signal Generation Circuit] The amplitude control signal generation circuit 38 is a register as shown in FIG.
90, a counter and signal transmission control circuit 91, and a down counter 92. Register 90 is the bus 37, CPU of FIG.
It is connected to the CPU 11 of FIG. 1 (A) through the interface 32 and stores the amplitude control data (sound intensity data) given from the CPU 11 and the output control signal indicating the sending or stopping of the digital signal. This register 90 is connected to the timing circuit 33 of FIG. 3 by a signal line 93, and reads the amplitude control data and the output control signal under the control of the timing circuit 33.

The counter control circuit 91 gives a transmission prohibition signal to the sample / latch circuit 45 of FIG. 3 through the signal line 70 when an output control signal indicating prohibition of digital signal transmission is written in the register 90 connected here, and digital output is performed. Is prohibited. At the same time, a maximum value setting signal is given to the preset terminal P of the down counter 92 through the signal line 95 to set the counter output value to an initial value equal to or greater than the maximum count value of the up / down counter 80 in FIG.

When the CPU 11 of FIG. 1 (A) generates an output control signal for releasing transmission inhibition and also generates amplitude control data, the down counter 92 performs a down count operation designated by the amplitude control data. In this embodiment, a constant value is output from the down counter 92 when a dial sound, a ringback sound, or a multi-frequency signal is generated, and the output of the down counter 92 is decreased with time when a hold sound is generated. Down counter 92
The 8-bit output obtained from the above is given to the comparison slice circuit 39 of FIG. 3 by the parallel transmission line 41.

By the way, it is desirable to start the comparison in the comparison slice circuit 39, change the slice level, and start the data transmission in the sample latch circuit 45 in synchronization with the zero cross of the digital triangular wave in order to reduce the waveform distortion of the audio signal. In order to achieve this synchronization, the signal lines 64 and 65 and the PLL derived from the triangular wave generating circuit 34 of FIG.
The signal line 73 derived from the circuit 35 is a counter control circuit.
Connected to 91. The counter control circuit 91 switches the output of the counter 92 in synchronization with the pulse of the signal line 64 indicating the zero cross of the digital triangular wave shown in FIG. 6 (D). That is, the CPU 11 does not immediately output the slice level output from the counter 92 when the CPU 11 outputs the signal for releasing the digital signal transmission prohibition, but the slice level is synchronized with the pulse indicating the zero cross in FIG. 6D. Is output. When the CPU 11 outputs amplitude control data that gradually reduces the slice level, the slice level is switched in synchronization with the zero cross of the triangular wave.

Since the DLP filter 42 is provided between the comparison slice circuit 39 and the sampling / latch circuit 45, delay of the digital signal occurs, and the zero cross of the output waveform of the DLP filter 42 is shown in hexadecimal notation in FIG. 6 (B). Is generated with a count value 89 shown by, and a pulse is generated on the signal line 65 as shown in FIG. 6 (B). The amplitude control signal generation circuit 38 shown in FIGS. 3 and 9 is a CP.
FIG. 6 (E) showing the time point when the triangular wave or the trapezoidal wave becomes zero cross at the output stage of the DLP filter 44 without immediately outputting the digital signal from the sampling / latch circuit 45 even when receiving the command to send the digital signal from U. The digital signal (triangular wave or trapezoidal wave) is output in synchronization with the pulse. The signal line 70 derived from the counter control circuit 91 of the amplitude control signal generation circuit 38 controls the start of transmission of the above digital signal.

[(7) Comparison Slice Circuit] As shown in FIG. 10, the comparison slice circuit 39 includes a digital comparison circuit 100 and first and second gates 101 and 102. The comparator circuit 100 includes an output transmission line 40 of the triangular wave generation circuit 34.
And the output transmission path 41 of the amplitude control signal generation circuit 38 is connected. This comparison circuit 100 has an 8-bit digital triangular wave 40a shown in FIG. 11 (A) given from one transmission line 40 and an 8-bit amplitude control signal 41a shown in FIG. 11 (A) given from the other transmission line 41. And the digital triangular wave 40a generates an output of a first level (for example, a high level) during a period (t0 to t1) (t2 to t3) in which the digital triangular wave 40a is smaller than the amplitude control signal 41a, and the digital triangular wave 40a outputs the amplitude control signal. A second level (eg, low level) output is generated during a period (t1 to t2) larger than 41a. The first gate 101 connected between the transmission line 40 of the triangular wave 40a and the transmission line 42 of the slice output becomes the signal transmission state (ON state) in response to the first level output of the comparison circuit 100. The second gate 102 connected between the transmission path 41 and the output transmission path 42 of the amplitude control signal 41a is in a signal transmission state in response to the second level output of the comparison circuit 100 inverted by the inverter 103. (ON state). FIG. 6 and FIG. 11 show the operation of each part in principle when obtaining a voice signal of constant frequency and constant amplitude (for example, dial tone). In this case, the down counter 92 of the amplitude control signal generating circuit 38 generates the amplitude control signal 41a composed of a digital signal of a constant level only during a necessary period. In FIG. 6 (F), the amplitude control signal 41a
The size of is shown in hexadecimal 88. Although the triangular wave 40a is shown as a linear slope in FIG. 11 (A), since it is actually the output of the up / down counter 80, FIG. 6 (B).
As shown in (4), it changes stepwise for each clock pulse. Since the up / down counter 80 obtains a digital signal showing a triangular wave, this digital signal is the same as the linear data obtained based on the linear quantization. 11th
During the period from t1 to t2 in the figure, the triangular wave 40a changes to the amplitude control signal 41a.
It becomes larger than (slice level), so comparison circuit 10
The output of 0 becomes the second level, the first gate 101 is turned off, the second gate 102 is turned on, and the value of the amplitude control signal 41a (hexadecimal 88) becomes the second level. Output is made as shown in FIG. FIG. 11B shows a digital signal on the common output transmission line 42 of the two gates 101 and 102.
It is an analog display of 42a. The digital signal 42a obtained from the comparison slice circuit 39 corresponds to an analog trapezoidal wave. The cycle of the triangular wave 40a and the sliced digital signal 42a is 1/2 of the cycle of the finally requested audio signal, but at the time of D / A conversion, FIG. 11 (C).
Since the polarity is inverted every other one as shown in (3), the required period (frequency) is obtained.

When changing the levels of various voice frequency signals required for telephone exchange, the magnitude of the amplitude control signal 41a is changed.
As a result, the maximum amplitude of the trapezoidal wave shown in FIG. 11B changes, and the amplitude of the audio frequency signal after D / A conversion also changes.

In order to distinguish the dial sound and the ringback sound, it is necessary to give a difference between the frequencies of the two. In this case, the frequency of the clock supplied from the PLL circuit 35 of FIG. 3 to the triangular wave generation circuit 34 is changed to change the frequency of the triangular wave 40 shown in FIG.
Change the cycle (frequency) of a.

It is desirable from the viewpoint of hearing that the held sound is a damped sound rather than a continuous sound of the same pitch. FIG. 12 shows in analog form the principle of generating a damped sound by changing the envelope of a trapezoidal wave.
The digital triangular wave 40a is repeatedly generated with a constant amplitude as in the case of FIG. 11 (A). On the other hand, the amplitude control signal 41a provided from the amplitude control signal generation circuit 38 is gradually reduced by down-counting the down counter 92 shown in FIG. Since the operation of the comparison slice circuit 39 is exactly the same as that of FIG. 11, the level of the output digital signal 42a of the comparison slice circuit 39 is gradually reduced as shown in FIG. 12 (B). When the D / A conversion, the trapezoidal wave in Fig. 12 (B)
When the polarity is reversed every other time, an approximate sine wave having a desired frequency is obtained as in the case of FIG. 11 (C).

In FIG. 12, the level of the amplitude control signal 41a composed of the output of the down counter 92 changes for each triangular wave for convenience of illustration, but the level of the amplitude control signal 41a is switched at an integer multiple of the cycle of the triangular wave. It is being appreciated. In addition, the amplitude control signal 41
The level of a is synchronized with the zero cross of the triangular wave 40a. If the amplitude control signal 41a is switched at a position other than the zero crossing as shown by the dotted line in FIG. 12 (A), it is sliced as shown by the dotted line in FIG. Will increase.

FIG. 13 shows a case where the envelope of the trapezoidal wave is controlled by changing the clock cycle of the down counter 92 of the amplitude control signal generation circuit 38 during the gradually decreasing operation. Since the clock is input to the down counter 92 at a relatively short cycle T1 in the section from t0 to t1, the amplitude control signal obtained from the down counter 92.
Although the level of 41a rapidly drops, the level of the amplitude control signal 41a slowly drops because the clock pulse of the down counter 92 is input in the period T2 longer than T1 in the interval from t1 to t2. Such switching control is executed by a command from the CPU 11. The level change speed of the amplitude control signal 41a is easily achieved by changing the frequency of the clock of the down counter 92. Therefore, various envelopes can be obtained. Based on the comparison operation shown in FIG. 13 (A), the envelope output shown in FIG. 13 (B) is obtained.

When the amplitude control signal 41a becomes zero in FIGS. 12 (A) and 13 (A), a signal transmission prohibition signal is formed by the counter and the signal transmission control circuit 91 shown in FIG. 9 and has a predetermined delay. Then, the signal is transmitted from the signal line 70.

[(8) DLP Filter] The DLP filter 43 generates a harmonic component of the digital signal which is considered to be generated when the digital signal 42a shown in FIG. 11 (B) and FIG. 12 (B) is D / A converted. It is for removing to some extent in advance at a stage. This DLP filter 43
Are set so that the transfer function H (z) is as follows.

H (z) = (1/128) / [1- (127/128) Z ^-1 ] (2) Here, Z ^-1 means a delay of one sample period. The output signal series Yn obtained corresponding to the input signal series Xn is set to follow the following difference equation.

Yn = (1/128) (Xn-Yn-1) + Yn-1 (3) Therefore, this DLP filter 43 is equivalent to the principle diagram shown in FIG. The DLP filter 43 of FIG. 14 includes a subtracter 105 that subtracts the input signal Xn from the output signal Yn-1 that is one sample before the input signal Xn, and the subtraction value (Xn-Yn-1) has a coefficient of 1
Multiplier 106 that multiplies / 128 and adder 107 that adds the output signal Yn-1 that is one sample before Xn to the multiplication output.
And a circuit 108 for obtaining the output signal one sample before.

The specific circuit of the DLP filter 43 is, as shown in FIG. 15, an input sample / hold circuit 110 and an addition / subtraction input control circuit 111.
An adder / subtractor circuit 112, a temporary storage register 113, and an output sample and hold circuit 114. As is clear from a comparison between the principle circuit of FIG. 14 and the concrete circuit of FIG. 15, in the concrete circuit, one adder / subtractor circuit 112 is used in time division to perform necessary subtraction and addition. . Next,
A more detailed description will be given with reference to FIG.

The input terminal of the input sample and hold circuit 110 is connected to the comparison slice circuit 39 of FIG. 3 by an 8-bit digital signal (absolute value) transmission line 42, and the 1-bit polarity signal line 63 of FIG. It is connected to the triangular wave generation circuit 34. The sampling pulse input terminal of the input sample and hold circuit 110 is connected to the timing circuit 33 of FIG. 3 by a signal line 67. The timing pulse of the timing signal line 66 input to the DLP filter 43 is shown in FIG. 6 (A) as shown in FIG. 6 (H) and FIG. 16 (A).
The clock signal is divided by 2 and is generated at half the clock frequency. The timing pulse of the other timing signal line 67 is shown in FIG.
As shown in FIG. 16 (B), the timing pulses in FIGS. 6 (H) and 16 (A) are phase-shifted by about 90 degrees.

The input sample and hold circuit 110 synchronizes with the leading edge of the timing pulse of FIG. 16 (B) and the input signal of FIG. 16 (C).
Read the polarity signal of Xn and signal line 63, hold for one sample time until the leading edge of the next timing pulse, and
It is sent to the transmission line 115 as shown in FIG. The first
In FIG. 6, the polarity signal is omitted to simplify the drawing.

The addition / subtraction input control circuit 111 is connected to the input sample and hold circuit 110 via transmission lines 115 and 116, is connected to the temporary storage register 113 via transmission lines 117 and 118, and is further connected via a signal line 66 shown in FIG. Timing circuit
33 is connected. The addition / subtraction input control circuit 111 is the first
As shown in FIG. 7, a first gate 119 that selectively passes data on the transmission lines 115 and 116, a second gate 120 that selectively passes data on the transmission lines 117 and 118, and a bit addition circuit 121. , OR gate 122. First gate 119 is first
In response to the low level of the timing signal shown in FIG. 6 (A), the data transmission state is entered, and the 8-bit input digital signal of the transmission line 115 and the 1-bit polarity signal of the transmission line 116 are selected and output. The 8-bit digital signal selected by the first gate 119 is converted into a 15-bit signal in the bit addition circuit 121 and sent to the parallel transmission line 119. The bit addition circuit 121 outputs 15 bits B1 to B15 from MSB to LSB. When there is no input signal, each bit is output.
B1 to B15 are configured to be zero. Since the first and second gates 119 and 120 do not turn on at the same time, the bit addition circuit 121 can be used in a time division manner.

The 8-bit input digital signal passes through the first gate 119 and only the lower 1 bit is further input through the OR gate 122 to the upper 8 bits B1 to B8 of the bit adding circuit 121. At this time, since the lower 7 bits of the bit addition circuit 121 outputs zero, the 8-bit signal is eventually converted to 15 bits and output to the transmission path 123.

On the other hand, the 8-bit signal on the output transmission line 117 of the temporary storage register 113 passes through the second gate 120 and the upper 1 bit (MSB)
Is further input to the lower 8 bits of the bit addition circuit 122 through the OR gate 122. At this time, since the upper 7 bits output zero, the 8-bit signal is eventually converted into 15 bits, and the arithmetic processing equivalent to the multiplication of 1/128 in FIG. Is output to. So independently 1
Since it is not necessary to provide a / 128 multiplier, the circuit configuration is simplified and the cost is reduced.

The 1-bit polarity signals of the transmission lines 116 and 118 are also selected in time division by the first and second gates 119 and 120, and the output transmission line 12
Sent to 4.

The control terminal of the first gate 119 is connected to the signal line 66 via the inverter 125, and the control terminal of the second gate 120 is directly connected to the signal line 66. The signal line 66 is connected to the timing circuit 33 of FIG. 3 and receives the timing signal shown in FIG. 16 (A). The first gate 119 is turned on in response to the low level of the timing signal in the period t2 to t4 in FIG. 16 (A), and extracts the input digital signal Xn shown in FIG. 16 (D). This extracted data is a bit addition circuit
Output transmission line 123 through 121 in the period from t2 to t4 in FIG.
Sent to. On the other hand, the second gate 120 is turned on in response to the high level of t4 to t6 in FIG. 16 (A),
The output digital signal of the temporary storage register 113 shown in FIG. 16 (H) is extracted. The data extracted here is sent to the transmission path 123 through the bit addition circuit 121 during the period from t4 to t6 in FIG. As a result, the input digital signals Xn, Xn + 1 ... And the register output signals (Xn-Yn-1) / 128, (Xn + 1-Yn) are input to the transmission line 123 as shown in FIG.
A time division multiplexed signal with / 128 …… is obtained.

The input terminal of the adder / subtractor circuit 112 in FIG. 15 is connected to the adder / subtractor input control circuit 111 by transmission lines 123 and 124 and to the output transmission lines 44 and 69 of the output sample and hold circuit 114. In the adder / subtractor circuit 112, an input digital signal as shown in, for example, t2 to t4 in FIG.
Xn and a register output signal (Xn−
Yn-1) / 128 time division signal and the output digital signal shown in FIG. 16 (E) are added, and the digital signal shown in FIG. 16 (G) is added to the 15-bit output transmission line 126. Output.

Calculation output Xn-Yn output from t2 to t3 period of FIG. 16 (G)
-1 corresponds to the output of the subtractor 105 in FIG. 14, and [(Xn-Yn-1) / 128] + Yn-1 in the period from t4 to t6 is the adder 10 in FIG.
It corresponds to the output of 7. Switching between the addition operation and the subtraction operation of the addition / subtraction circuit 112 is performed by the timing signal of FIG. 16 (A) supplied to the signal line 66. As is clear from the relationship between FIGS. 16A and 16G, the subtraction operation is performed in response to the low level of the timing signal in FIG. 16A, and the addition operation is performed in response to the high level.

The temporary storage register 113 is provided with the transmission lines 126 and 1 of the upper 8 bits.
The bit polarity signal transmission line 127 is connected to the addition / subtraction circuit 112. This temporary storage register 113 is shown in FIG. 16 (G) in response to the fall of the timing signal in FIG. 16 (B) from high level to low level as shown in FIG. 16 (H).
The subtraction outputs (Xn-Yn-1), (Xn + 1-Yn), ... Are read and held until the next sampling time. However,
Since this temporary storage register 113 has 8 bits for digital signals (absolute value) and 1 bit for polarity (sign) signal, the upper 8 bits of the 15-bit digital signal obtained from the adder / subtractor circuit 112 are used. A bit,
Holds only one bit of the polarity signal. For example, Xn-Yn-1 in the period from t2 to t4 in FIG. 16 (G) is obtained in the period from t3 to t7 in FIG. 16 (H), so that FIG. 16 (H) in the period from t4 to t5.
It becomes possible to execute the addition of the signal in FIG. 16 and the signal in FIG. 16 (E).

The input of the output sample and hold circuit 114 is coupled to the output of the adder / subtractor circuit 112 by a 15-bit absolute value transmission line 128 and a 1-bit polarity signal transmission line 129. The output sample-and-hold circuit 114 is provided with a first signal supplied from the signal line 67.
The addition / subtraction output of FIG. 16 (G) is sampled in synchronization with the rise of the timing signal shown in FIG. 6 (B) from the low level to the high level, and is held until the next sampling time. First
The rising time of the timing signal in FIG. 16 (B) corresponds to the addition output period in FIG. 16 (G).
Data in the period t4 to t5 in Figure (G) and t5 to t8 in Figure 16 (E)
It is the same as the period data. Although the added value in FIG. 16 (G) is shown to end at t5, the output sample / hold circuit 114 actually has a slight delay.
It is held until it is sampled at.

The output terminal of the 15-bit digital signal (absolute value) of the output sample and hold circuit 114 is connected to the addition / subtraction circuit 112 by the transmission line 44a, and the 1-bit polarity signal output terminal is also connected to the addition / subtraction circuit 112 by the transmission line 69a. There is. The output sample-and-hold circuit 114 and the sample-and-hold circuit 45 at the next stage shown in FIG.
, And OR gate 130 and two signal lines 68, 69.

Figure 18 shows the output sample and hold circuit 1 of the DLP filter 43.
It shows in detail the connections of the 14 data output stages. The transmission line 44a for connecting to the adder / subtractor circuit 112 consists of 15 bits, but the transmission line 44 for connecting to the sample and hold circuit 45 of FIG. 3 is counted from the upper bits from the second bit B2 to the eleventh bit B11. It is said to be a 10-bit transmission line. The 12th bit B12 and the 13th bit B13 are connected to the OR gate 130, and the signal line 68 is connected to this output. When a triangular wave or a trapezoidal wave is input to the DLP filter 43, an output attenuated by about 6 dB is obtained, so that the most significant bit B1 of the output of the DLP filter 43 is always zero. Therefore, the most significant bit B1
There is no problem even if the output is omitted by omitting. The OR gate 130 produces one bit of the logical sum of the twelfth bit B12 and the thirteenth bit B13 in order to reduce the quantization error, and attaches this one bit to 10 bits of the transmission line 44 and outputs it. Eventually, the 11-bit digital signal will be output from the DLP filter 43.

The 11 bits of the output of the DLP filter 43 are determined in relation to the required bits in the adder 52 and the linear nonlinear conversion circuit 58. That is, in order to convert a linear input into an 8-bit nonlinear output in the linear nonlinear conversion circuit 58, 12-bit input is required. If the input and output of the adder 52 are 12 bits when the sum of the output digital signals of the first and second audio signal digital signal generating circuits 30 and 31 is formed and output by the adder 52, overflow occurs. there's a possibility that. Therefore, the input of the adder 52, that is, the DLP filter 43
The output of should be limited to 11 bits.

A very important point of the DLP filter 43 of FIG. 15 is that the frequency of the timing signal of FIGS. 6 (H) and (I) is shown in FIG. 6 (A).
The frequency of the timing signals on the signal lines 66 and 67 changes in proportion to the frequency of the triangular wave or the trapezoidal wave input from the transmission path 42, because the frequency of the clock signal is 1/2. By controlling the DLP filter 43 in this way, the DLP filter 43 is controlled regardless of changes in the frequency of the triangular wave or the trapezoidal wave, that is, the fundamental wave frequency.
The gain characteristic (amplitude characteristic) and the phase characteristic of the DLP filter 43 can be made substantially constant. Next, this will be described in detail.

Z in the equation (2) showing the transfer function H (z) of the DLP filter 43 already described is z = e ^jωT (4) (where ω is an input digital signal in the DLP filter 43, that is, a triangular wave or a trapezoidal wave) Angular frequency of fundamental wave, T
Is the sampling period), the transfer function H
(Z) is given by the following equation.

H (z) = (1/128) / [1- (127/128) e- ^jωT ] = (1/128) / [1- (127/128) (cosωT-jsinω
T)] (5) This absolute value of H (z) | H (z) | is given by the following equation.

By the way, the sampling period T in the DLP filter 43
(Radian) is an integer multiple of the frequency of the triangular wave or the trapezoidal wave. That is, FIG. 6 (H) (I) and FIG. 16 (A) given to the DLP filter 43 by the signal lines 66 and 67.
The timing signal shown in (B) is generated at half the frequency of the clock in FIG. 6 (A). 1 of triangular wave or trapezoidal wave
The number of clock pulse inputs of the counter of period Ta is a 192-ary up / down counter for generating a digital triangular wave.
Since the maximum count value of 0, which is 4 times the n = 192, is 768, the number of sampling pulses input to the DLP filter 43 is 384, which is half of 768, and the sampling frequency is 384Ω.
Becomes Therefore, the sampling period T in the DLP filter 43 is T = 2π / 384 (radian). When the absolute value of the transfer function H (z) is counted based on this, the following value is obtained.

If this is taken to be a dB value, then 20log0.432 = −7.29dB (8). In short, the sampling frequency of the DLP filter 43 is 384 ω, which is 384 times the fundamental frequency ω of the triangular wave or trapezoidal wave.
Therefore, the transfer function value is determined regardless of the fundamental wave frequency ω of the triangular wave or the trapezoidal wave. As a result, the amplitude characteristic of the DLP filter 43 is kept substantially constant even if the fundamental frequency ω changes. This means that a single DLP filter 43 can process digital signals of various frequencies. Considering this amplitude characteristic in correspondence with an analog low-pass filter, it is equivalent to that the cutoff frequency extends to the high frequency side as the frequency of the input signal increases.

The phase characteristic of the DLP filter 43 can be expressed by the following equation based on the equation (5).

tan (LH) = (127/128) sinωT / [1- (127/128) cosωt] = (127/128) sin (2π / 384) / [1- (127/128) cos (2π / 384)] (9) Substituting T = 2π / 384ω into T of the equation (9) gives the following value.

tan (LH) = 2.043 Therefore, the phase difference between the input signal and the output signal of the DLP filter 43 is as follows.

LH = tan ⁻¹ 2.043 = 11.1156 = 0.71 × π / 2 (10) This phase difference is a constant value regardless of the frequency of the input signal of the DLP filter 43. When the phase of the equation (10) is represented by the count number of the up-dawka counter 80 in FIG. 4, it is 136 counts based on 0 count, and is 88 in hexadecimal. As is clear from a comparison between FIG. 19 (A) showing the input triangular wave of the DLP filter 43 in analog correspondence and FIG. 19 (B) showing the output waveform of the DLP filter 43 in analog correspondence, there is 0.71 × π between the two. There is a fixed phase difference of / 2. Like this
If the phase characteristic of the DLP filter 43 is constant, there is an advantage that the zero-cross point can be easily determined regardless of the change in the frequency of the input signal. Therefore, in this embodiment, the zero-delay pulse generation circuit 82 of FIG. 4 predicts and determines the zero-cross point of the output signal of the DLP filter 43, and this is used as the zero-cross signal. Like this DLP
How to determine the zero crossing of the output of filter 43
This is more advantageous in terms of circuit configuration than the method of providing a zero cross detection circuit at the output stage of the filter 43.

[(9) Sample-and-Hold Circuit 45] The sample-and-hold circuit 45 provided at the output stage of the DLP filter 43 in FIG. 3 has a frequency of 8 kHz according to the CCITT recommendation, and the sample-and-hold circuit 45 in FIG. The output of the DLP filter 43 shown in FIG. 6 (J) is sampled by the sampling pulse and output as shown in FIG. 6 (L). 10-bit transmission line 44 connected to DLP filter 43
And the input data given by the least significant 1-bit signal line 68 and the 1-bit polarity signal line 69 are sampled in synchronization with the 8 kHz timing signal of the signal line 71 derived from the timing circuit 33 of FIG. To be done. The sample-and-hold circuit 45 is also connected to the amplitude control signal generating circuit 38 by a signal line 70 in order to control transmission of a digital signal. The output of the sample and hold circuit 45 becomes zero when the signal indicating the data transmission prohibition is generated on the signal line 70. As described above, the start of sending the digital signal in the sample and hold circuit 45 is synchronized with this zero cross. That is, in response to the generation of a pulse corresponding to the zero cross of the waveform of FIG. 19B from the zero delay pulse generation circuit 82 of FIG. 4, the counter and signal transmission control circuit 91 of FIG. The signal indicating the release prohibition is output to. This prevents abrupt changes in the amplitude of the digital signal and the analog signal corresponding to the digital signal, and provides a audible sound.

If the sample and hold circuit 45 samples the input signal at a sampling frequency of 8 kHz, a new frequency component is generated based on this. If this new frequency component is within the range of 4 kHz or less of the voice frequency band, it becomes noise. As already explained, the noise frequency component contained in the input signal is an integer multiple of the sampling frequency (8kHz), so
The noise frequency component of 4 kHz or less generated when the input signal including the noise frequency component is sampled, the triangular wave matches the fundamental wave frequency component of the trapezoidal wave, and the generation of abnormal noise is reduced.

[(10) Output control circuit 47 and adder 52] In FIG. 3, the 1-bit polarity signal and the 11-bit digital signal (absolute value) of the first and second audio signal digital signal generating circuits 30 and 31 are shown. 12-bit output transmission lines 46 and 48 are connected to the output control circuit 47. Further, the output control circuit 47 is connected to the CPU interface 32 via the bus 37.
Are connected, and an addition command is given from the CPU 11 of FIG. Further, the output control circuit 47 is connected to the timing circuit 33 through signal lines 49a and 49b in FIG.
The output timing signal shown in (D) is applied. In addition,
Another signal line not shown in FIG. 3 is also provided between the timing circuit 33 and the output control circuit 47.

In the case of the single tone generation mode (non-addition mode), the operation shown in FIG. 20 is performed. As shown in FIG. 20 (A), one transmission line 46
The first digital signal input from YAN, YAn + 1, YA
n + 2 ... and the other transmission line 4 as shown in FIG.
Second digital signal YBn, YBn + 1, YBn input from 8
If +2 ..., Even if these are input at the same time, signals are not simultaneously given to the transmission lines 50 and 51 to the adder 52 as shown in FIGS. 20 (E) and (F). In order to execute this control, the timing circuit 33 sends out the data extraction pulse shown in FIGS. 20C and 20D to the signal lines 49a and 49b. The first and second extraction gates (not shown) included in the output control circuit 47 are responsive to the extraction pulses of FIGS. Extract the signal of B),
Output as shown in FIGS. 20 (E) and (F). Figure 20 (E)
A signal indicating zero is output except during the period in which the digital signal is extracted in (F). The adder 52 is shown in FIG. 20 (E).
The first and second signals of (F) are input in a time division manner, and a signal to which zero is added is output to the transmission line 57 as shown in FIG. 20 (G). That is, the adder 52 outputs the input signal as it is. The adder 52 has 12 bits for a digital signal (absolute value) and 1 bit for a polarity signal, and generates an output of 13 bits. The output of the adder 52 is converted to 8-bit (7-bit absolute value, 1-bit polarity) non-linear data by the linear non-linear conversion circuit 58 at the next stage, and is transmitted through the transmission line 59 to the first and second P /
It is sent to the S (parallel / serial) conversion registers 54 and 56.

The first and second P / S conversion registers 54, 56 are provided with signal lines 53a, 53
It is connected to the output control circuit 47 by b, 53c, 55a, 55b and 55c. The signal lines 53a, 53b, 53c connected to the first P / S conversion register 54 are shown in FIGS. 20 (H) (I) (J).
The signals shown in are respectively given. The pulse of the signal line 53a of FIG. 20 (H) is generated during the extraction period of the first signal of FIG. 20 (C) (E) and is included in the output of the adder 52 as the first pulse.
Signals YAn, YAn + 1, YAn + 2, ... Of these signals are latched in the first P / S conversion register 54. The first signal latched in the P / S conversion register 54 is the timing shown in FIG. 20 (J) given by the signal line 53c during the output timing pulse of FIG. 20 (I) given to the signal line 53b. It is read out serially in synchronization with the pulse (clock pulse) and sent to the transmission line 60 as shown in FIG. The transfer rate of this signal is 8 bits every 125 μs, which is 64 kbps after all.

The second P / S conversion register 56 is supplied with the latching pulse shown in FIG. 20L corresponding to the extraction period of the second signal through the signal line 55a. As a result, the signal corresponding to the second signal included in the output of the adder 52 is latched and latched by the same signal as that shown in FIGS. 20 (I) and (J) given to the signal lines 55b and 55c. The signal is serially output to the transmission line 61 as shown in FIG. The independent use of the first and second digital signal generating circuits 30 and 31 for voice signals makes it possible to cope with the case where a plurality of telephones simultaneously request different or the same signal tones. Although the first and second signals are simultaneously output in FIGS. 20 (K) and 20 (M), it does not matter if they are output at different times.

FIG. 21 shows the timing when the first signal of the transmission line 46 and the second signal of the transmission line 47 are added and output when obtaining a chord of the melody holding tone or when obtaining a multi-frequency signal. 21st
The first and second signals of the transmission lines 46 and 47 of FIGS. 21A and 21B are simultaneously extracted in the output control circuit 47 based on the extraction pulse of FIGS. E) As shown in (F), the signals are sent from the transmission lines 50, 51 to the adder 52, where they are added and added signals YAn + YBn, YAn + 1 shown in FIG. 21 (G).
+ YBn + 1 ... And sent to the transmission line 57. Adder 5
Since 2 can obtain an output with an absolute value of 12 bits and a polarity of 1 bit, overflow does not occur even if two 11-bit signals are added. The addition signal is converted into an 8-bit non-linear signal by the linear non-linear conversion circuit 58, and is written in the P / S conversion register 54 at the leading edge of the latch signal in FIG. ) Signal, read the 21st
The addition signal is serially output to the transmission line 60 as shown in FIG.

In FIG. 21, the nonlinear addition signal is written only in the first P / S conversion register 54, but in the second P / S conversion register 56
You can write in at the same time.

[(11) Linear Non-Linear Conversion Circuit 58] A 12-bit digital signal and a 1-bit polarity signal are input to the linear non-linear conversion circuit 58 through the transmission line 57, and this is
It is converted into an 8-bit signal consisting of a 7-bit non-linear digital signal and a 1-bit polarity signal in accordance with CCITT Recommendation G711. The linear non-linear transformation law is
There are two types, 13-line approximation and A-law. In the present embodiment, there is a μ-law and A-law switching signal terminal 131, and the μ-law operation is performed when a high level signal is applied thereto, and the A-law operation is performed when a low level signal is applied.

FIG. 22 shows the correspondence between the 12-bit linear data and the corresponding 7-bit nonlinear data (compression data) according to the μ-law. However, in the case of this μ-law conversion, an adder
After the shift amount 16 is added to the output of 52 by the adder built in the linear nonlinear conversion circuit 58, the μ conversion law of FIG. 22 is applied.

FIG. 23 shows the correspondence between the 12-bit linear data and the corresponding 7-bit non-linear data (compression data) according to the A law. In FIGS. 22 and 23, WXYZ indicates either 0 or 1, * indicates a bit unrelated to conversion, and indicates an inversion of W and Y. The polarity signal is irrelevant to the linear non-linear conversion, and is added to the most significant 7-bit non-linear data and sent to the transmission line 59.
The 8-bit non-linear data (PCM signal) is suitable for a normal PCM communication interface and is convenient for mass production of button telephone devices.

[Modifications] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) Although two digital signal generating circuits 30 and 31 for audio signals are provided in FIG. 3, one of them may be omitted. In addition, one or more digital signal generating circuits for audio signals having the same configuration as these may be added. Even if it is added, the adder 52, the linear nonlinear conversion circuit
It is desirable to use the 58 in a time division manner in order to simplify the circuit. If you add two or more digital signal generation circuits,
It is possible to create two chords at the same time.

(2) Timing signals of the signal lines 53b and 53c and the signal lines 55b and 5
The P / S conversion registers 54 and 56 may output 8-bit digital signals at different times by outputting the timing signal of 5c at different times.

(3) In this embodiment, the data is transmitted serially on the bus 8 in FIG. 1, but it may be transmitted in parallel.

(4) Instead of using the adder in the linear non-linear conversion circuit 58 to add the shift amount 16 required when performing the linear non-linear conversion according to the μ-law, the adder 52 in the previous stage may be used. Good.

(5) D / A for converting digital signals into audio signals
The converter may not be provided in the telephones 2a to 2f, but may be provided in the extension trunk 5.

(6) Of course, it can be applied to the case where the telephones 2a to 2f are integrated with a facsimile or the like.

(7) In order to exchange control signals between the CPU 11 and each of the telephones 2a to 2f, a control signal line may be provided independently of the transmission line 20.

(8) The number of highways for time-division multiplexing transmission of call data and voice signal digital signals on the bus 8 in the main unit 1 of FIG. 1 is two in the embodiment, but may be one. It may be more than two.

(9) Even if all of the dial tone, ringback tone, hold tone, and multi-frequency signal (DTMF) are not generated based on the digital signal generator 10 and some of them are generated by another means. Good. The ringing signal may also be formed on the basis of a digital signal generator.

(10) Instead of forming a folded digital signal, the up / down counter 80 may form a digital signal having the same period as the desired analog signal. In this case, the polarity signal becomes unnecessary.

(11) In the embodiment, a hexadecimal digital signal is obtained from the triangular wave generating circuit 34, but a binary or octal digital signal may be obtained.

(12) The down counter 92 is an up / down counter,
An amplitude control signal whose level gradually increases or an amplitude control signal which gradually increases and then gradually decreases may be formed.

[Effects of the Invention] As is apparent from the above, according to the present invention, it is possible to easily achieve transmission and / or inhibition of data at the zero crossing point in the output stage of the digital low-pass filter.

[Brief description of drawings]

FIG. 1 (A) is a block diagram showing a key telephone device according to an embodiment of the present invention, FIG. 1 (B) is a block diagram showing the principle of the telephone of FIG. 1, and FIG. FIG. 3 is a diagram for explaining the timing of data transmission on the bus, FIG. 3 is a block diagram showing in detail the digital signal generator of FIG. 1, and FIG. 4 is a block diagram showing in detail the triangular wave generating circuit of FIG. 4 is a diagram for explaining the operation of each part of FIG. 4, FIG. 6 is a diagram showing a timing relationship of each part of FIG. 3, FIG. 7 is a block diagram showing in detail the PLL circuit of FIG. 3, and FIG. FIG. 9 is a diagram showing the distribution of frequency components generated by sampling the fundamental wave frequency signal, FIG. 9 is a block diagram showing in detail the amplitude control signal generating circuit of FIG. 3, and FIG. 10 is a comparison slice circuit of FIG. Fig. 11 shows the detailed block diagram of Fig. 10. FIG. 12 is a diagram for explaining the operation, FIG. 12 is a diagram for explaining the operation when the level of the amplitude control signal is changed with time in the circuit of FIG. 10, and FIG. 13 is an amplitude in the circuit of FIG. FIG. 14 is a diagram for explaining the operation when the control signal level is changed with time and the changing speed is changed. FIG. 14 is a principle diagram of the DLP filter of FIG. 3, and FIG. 15 is a DLP of FIG. FIG. 16 is a block diagram showing the filter in detail, FIG. 16 is a diagram showing the timing relationship of each part in FIG. 15, FIG. 17 is a block diagram showing in detail the add / subtract input control circuit of the DLP filter of FIG. 15, and FIG. The circuit diagram showing the connection of the output stage of the output sample and hold circuit in the figure in detail, Fig. 19 shows the analog relationship between the input and output of the DLP filter, and Fig. 20 shows the diagram of Fig. 3 when a single sound is generated. Timing relation between output control circuit and each part of the latter stage FIG. 21, FIG. 21 is a diagram showing a timing relationship between the output control circuit of FIG. 3 and each part of the latter stage when a chord is generated, and FIG. 22 is a diagram showing a μ law of the linear nonlinear conversion circuit of FIG. FIG. 23 is a diagram showing the A law of the linear non-linear conversion circuit of FIG. 2a to 2f ... Telephone, 10 ... Digital signal generator, 11 ...
... CPU, 12 ... memory, 34 ... digital triangular wave generation circuit, 35 ... PLL circuit, 3 ... amplitude control signal generation circuit, 39
…… Comparison slice circuit, 43 …… DLP filter, 45 …… Sample and hold circuit.

Claims (1)

[Claims] 1. A clock signal generating circuit, and an up / down counter for periodically repeating an up-counting operation and a down-counting operation in response to a clock signal obtained from the clock signal generating circuit to generate a digital triangular wave signal. A digital low-pass filter for removing a harmonic distortion component of a digital triangular wave signal obtained from the up-down counter or a signal whose amplitude is controlled; and a digital low-pass filter provided between the digital low-pass filter and the output transmission line. A sample and hold circuit that samples the output of the filter at a predetermined frequency and holds and outputs it only for a predetermined time; and a zero point when the output digital signal of the digital low-pass filter has a periodicity and becomes zero. Determined by counter output A zero time point determination circuit, a data transmission control signal supply means for providing a data transmission control signal indicating whether or not to transmit a digital signal from the sample and hold circuit, the zero time point determination circuit and the data transmission control signal supply means And a signal for controlling the sample and hold circuit so that the data transmission control signal is used to inhibit or cancel the inhibition of the transmission of data in synchronization with the zero time point. A digital signal generator comprising a control circuit for controlling transmission of a digital signal from the circuit.