JPH0795231B2 - Modulation signal generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating a modulation signal for imparting a modulation effect to a musical tone signal in an electronic musical instrument or a musical tone effect imparting device.

[0002]

2. Description of the Related Art In electronic musical instruments, a large number of modulation waveform generators are used to impart various modulation effects such as vibrato, tremolo, and ensemble. For example,
Japanese Unexamined Patent Publication No. 52-112313 discloses that a separate modulation waveform generator is provided for each modulation effect of frequency modulation, tone color modulation, and amplitude modulation. In addition, actual public Sho 53-133
In No. 82, a plurality of series of modulation waveform generators are provided separately,
It is shown that the phases of the modulated waveform signals generated in each are shifted by a predetermined amount, or a plurality of modulated waveform signals having different frequencies or phases are combined to obtain a special modulated waveform signal. Further, Japanese Utility Model Application Laid-Open No. 57-88193 discloses that a separate modulation waveform generator is provided for each of a plurality of tone generation sequences.

Further, Japanese Patent Laid-Open No. 58-83894 discloses that a plurality of modulation signals are generated in a time division manner and a plurality of input signals are time-divisionally modulated differently.
Japanese Unexamined Patent Publication No. 57-99696 discloses that the phases of modulation signals independently generated in a plurality of streams are forcibly synchronized. Japanese Unexamined Patent Publication No. 58-25696 discloses that a plurality of modulation signal waveforms stored in a storage device are selectively selected and read.

[0004]

In any of the above-mentioned conventional modulation signal generators, the modulation signals generated in a plurality of channels are combined to create a new modulation signal, or a combination channel for that purpose is arbitrarily set. Nothing is shown about changing the settings or performing free modulation signal synthesis. In addition, the initial phase of the modulation signal generated on multiple channels can be freely set to create a multi-phase modulation waveform (multiple modulation waveforms with different phases), enabling phase-shifted modulation control. Nothing is shown about freely setting the initial phase for each channel.

The present invention has been made in view of the above points, and when a modulation signal is independently generated in each channel, it is possible to form a modulation waveform by combining, and a combining channel for that can be arbitrarily set. It is an object of the present invention to provide a modulation signal generator capable of freely synthesizing modulation signals by enabling setting and setting.

[0006]

SUMMARY OF THE INVENTION A modulation signal generator of the present invention is a modulation signal generator which generates a modulation waveform signal in a plurality of channels in a time division manner, and a waveform table storing a predetermined waveform. A time division channel instructing means for instructing time division timing of each of the plurality of channels,
Frequency setting means for setting the frequency of the modulating waveform signal to be generated in each channel, and time division instructed by the time division channel instruction means according to the frequency set in correspondence with each channel by the frequency setting means. Read-out means for reading the waveform signal of each channel from the waveform table at a timing, combined channel setting means for setting a channel to be combined with the modulating waveform signal, and each channel read from the waveform table And a synthesizing unit for performing an operation of synthesizing the waveform signals of the channels set by the synthesizing channel setting unit among the waveform signals.

Correspondence between each of the above-mentioned constituent elements and the embodiment described below is as follows:
The time division channel instructing means is the channel counter 1, the frequency setting means is the frequency data table 8, the reading means is the RAM 4 and the adder 5, the combining channel setting means is the combining control table 14, and the combining means is the adder 12 and the register 13. It corresponds almost to each part.

[0008]

The modulating waveform signal is time-divisionally read from the waveform table for each channel according to the frequency set for each channel. The synthesis channel setting means arbitrarily sets the channel to which the modulation waveform signal is to be synthesized,
The synthesizing means performs an operation of synthesizing the waveform signals of the channels set by the synthetic channel setting means out of the read waveform signals of the respective channels. Therefore, a new waveform for modulation can be created by synthesizing the waveform signals for modulation generated in an arbitrary channel, and it is possible to freely synthesize the modulation signals.

[0009]

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In FIG. 1, a channel counter 1 corresponds to a time-division channel setting means for setting time-division timings of a plurality of channels. If the number of channels is 16, the channel counter 1 is composed of a modulo 16 counter and outputs a master clock pulse φM. Count 0
Channel number data CHD from 1 to 15 are sequentially generated in a time division manner. FIG. 2 is a diagram showing a state in which the channel number data CHD changes in response to the master clock pulse φM. 16 time-shared from 0 to 15
In each channel, 16 modulation signals are independently generated.

The waveform table 2 stores one or a plurality of different waveforms (for example, sine wave and triangular wave),
When a plurality of waveforms are stored, one waveform to be read is selected according to the waveform selection data WSEL from the waveform selection table 3 as described later.

The reading means for reading the waveform table 2 is a random access memory (hereinafter referred to as RAM) 4
And an adder 5. The RAM 4 is provided with as many addresses as the number of channels for storing the phase address data qF for reading the waveform table, and the write address input WA is supplied with the channel number data CHD output from the channel counter 1 and the read address. The output of the synchronization channel table 6 described later is given to the input RA.

The read output of the RAM 4 is given to the adder 5, and the output of the adder 5 is given to the phase address input of the waveform table 2 and the data write input of the RAM 4 via the adder 7 for phase shift. To be The other input of the adder 5 is the frequency data F which is the increment value (change value) of the phase address data qF per calculation unit time.
It is given from the frequency data table 8 through the gate 9.

The frequency data table 8 stores frequency data F for setting the frequency of the waveform signal to be read from the waveform table 2 for each channel, and the frequency data F of each channel is the channel number data CH.
It is read out in a time division manner according to D. As will be described later, the gate 9 is provided for synchronization control, and is normally opened (when synchronization control is not performed), and the frequency data F read from the table 8 is sent to the adder 5. The frequency data F is repeatedly supplied (or may be subtracted) in the phase accumulator constituted by the RAM 4 and the adder 5. That is, the waveform table 2
In the normal read control of, the channel is designated as the read address of the RAM 4 in the time slot of the channel, the previous phase address data (q-1) F for the channel is read from the RAM 4, and the adder 5 writes it. Frequency data F is added to add new phase address data qF (where q is 1,
2, 3 ... Sequentially changing numbers, which indicates the number of times F has been accumulated), and on the other hand, the channel is designated as a write address of the RAM 4, and the obtained phase address data qF
Is stored at the address of the channel. In this way, the frequency data F is independently accumulated in time division for each channel, and the phase address qF that sequentially changes at the rate of change corresponding to the set frequency is obtained in time division for each channel. As is well known, the accumulator consisting of the RAM 4 and the adder 5 has a predetermined modulo number, and the modulo number is taken as one cycle to set the phase address data qF.
Changes repeatedly.

The synchronization channel table 6 stores, for each channel, the number data (synchronization channel data SCHD) of the channel with which the waveform signal of that channel is to be synchronized, and each channel number data CHD given from the counter 1 The synchronous channel data CHD for each channel is read out in a time division manner. An example of the setting contents of this table 6 is shown in the following table. Of course, the setting is not limited to this, and can be set in any mode.

Table 1 Input (CHD) │ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ─────┼─────────────────── ─────── Output (SCHD) │ 0 6 6 15 14 5 6 7 8 9 10 12 12 13 14 15

The channels (0, 5, 6, 7, 8, 9, 10, 1 in the above table) in which the synchronous channel data SCHD having the same value as the own channel number data CHD are stored.
2, 13, 14, 15) means that the waveform table 2 should be read by the above-described normal read control without performing the synchronous read control. Data CHD and SCHD
Channels with different values of (1, 2, 3, 4, 1 in the above table
1) means that synchronous read control should be performed. The sync channel data SCHD read from the sync channel table 6 is given to one input of the comparator 10 and, as described above, the read address input RA of the RAM 4 is input.
Given to. The channel number data CHD from the counter 1 is applied to the other input of the comparator 10. The comparator 10 outputs a match signal EQ of "1" when the values of both inputs match.
Which causes the gate 9 to open. When they do not match, the match signal EQ is "1" and the gate 9 is not opened.

The normal read control will be described by taking channel 6 in Table 1 as an example. The value of the synchronous channel data SCHD read from the synchronous channel table 6 in the time division time slot of channel 6 is the channel number data at that time. Since it is “6” which is the same as the value of CHD, the coincidence signal EQ is output from the comparator 10, the gate 9 is opened, and the frequency data F of the channel 6 is added to the adder 5
Given to. At this time, the same channel 6 is used for the write address input WA and the read address input RA of the RAM 4.
The channel number data CHD and the synchronous channel data SCHD that specify the are input. Therefore, as described above, the frequency data F of the channel 6 is repeatedly added in the time division time slot of the channel 6, and the phase address data qF corresponding to the frequency set for the channel 6 is generated.

The synchronous read control will be described by taking channel 1 in Table 1 as an example. The value "6" of the synchronous channel data SCHD read from table 6 in the time division time slot of channel 1 is the channel number at that time. Since it is different from the value "1" of the data CHD,
The coincidence signal EQ is not output, the gate 9 is closed, and the frequency data F is not given to the adder 5. On the other hand, since the read address input RA of the RAM 4 is supplied with the data SCHD indicating the channel "6", the phase address data qF of the channel 6 is read from the RAM 4 despite the time division timing of the channel 1. , Is input to the waveform table 2 as phase address data of channel 1 via the adders 5 and 7. Thus
The phase address data qF for reading the wave number table of channel 1 is forcibly synchronized with the phase address data qF of channel 6, and the frequencies of both channels become the same.

The phase shift table 11 stores the initial phase data θ for setting the initial phase of the waveform signal of each channel for each channel, and the initial phase data of each channel according to the channel number data CHD from the counter 1. Read θ in a time division manner. This initial phase data θ
Is given to the adder 7 and added to the phase address data qF from the adder 5. The output qF + θ of the adder 7 is given to the phase address input of the waveform table 2. In this way, the phase address data qF for reading the waveform table 2 is phase-shifted independently for each channel according to the initial phase data θ for each channel, and independent phase shift control is realized for each channel.

The waveform selection table 3 is provided when a plurality of different waveforms are stored in the waveform table 2, and the waveform selection data WSEL for selecting the waveform to be read is stored for each channel. , And this is read out in time division according to the channel number data CHD. When the number of waves stored in the waveform table 2 is one, this waveform is the phase address data q of each channel.
It is read out in a time division manner according to F + θ (qF when θ is 0). When a plurality of types of waveforms are stored in the waveform table 2, the waveform selection data WSE for each channel
The waveform is selected by L in a time division manner, and the selected waveform corresponds to the phase address data qF +
It is read according to θ (or qF).

The waveform signal of each channel read out from the waveform table 2 in a time division manner is input to the adder 12 for waveform synthesis. The output of the adder 12 is supplied to an appropriate modulation effect imparting circuit (not shown) as an output signal (that is, a modulation signal) of the modulation signal generator and is also input to the register 13. The register 13 is for delaying the waveform signal of each channel by the time slot length of one channel, and at the end of the time slot of each channel, acquires and captures the waveform signal of that channel according to the master clock pulse φM. The waveform signal is output during the time slot of the next channel. This register 1
The output of the synthesis control table 14 is given to the clear input of No. 3, and this clear input signal is "1".
In the case of, the contents of the register 13 are not cleared and the waveform signal of the previous channel is supplied from the register 13 to the adder 12. However, in the case of "0", the contents of the register 13 are cleared and the contents of the previous channel are cleared. The waveform signal is prevented from being given to the adder 12.

The synthesis control table 14 stores, for each channel, synthesis control data MXD indicating whether or not the waveform signal of the previous channel and the waveform signal of its own channel should be added and synthesized, and according to the channel number data CHD. The composite control data MXD of each channel is read out in a time division manner. This data MXD is "1" when the waveform signal of the previous channel and the waveform signal of its own channel are to be added and synthesized, and is "0" otherwise. The following table shows an example of the setting contents of the table 14.

Table 2 Input (CHD) │ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ─────┼─────────────────── ─────── Output (MXD) │ 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1

Combining control will be described by taking channels 1, 2, and 3 in the above table as an example. In the time slot of channel 1, the combining control data MXD read from the table 14 is "0", and the preceding channel. Since the waveform signal of 0 is cleared by the register 13, the waveform signal of channel 1 is output as it is from the adder 12 without being mixed with the waveform signals of other channels. In the next channel 2 time slot, the combined control data MX
Since D is "1", the waveform signal of channel 1 immediately before it is not cleared by the register 13 and is given to the adder 12. Therefore, a signal obtained by adding the waveform signals read from the waveform table 2 in channels 1 and 2 is output from the adder 12 in the time slot of channel 2, and finally is output as the modulation signal of channel 2. In the next channel 3 time slot, the combined control data MX
Since D is "1", the signal output from the adder 12 in the time slot of the channel 2 immediately before that, that is, the added and synthesized waveform signal of channels 1 and 2 is not cleared by the register 13 and is given to the adder 12 as it is To be Therefore,
A signal obtained by adding the three waveform signals read from the waveform table 2 in the channels 1, 2, and 3 is output from the adder 12 in the time slot of the channel 3 and finally output as the modulation signal of the channel 3. .

In the example of FIG. 1, the output of the adder 12 is delayed by the register 13, but the read output of the waveform memory 2 is delayed by the register 13, and this delayed output and the read output of the waveform memory 2 are delayed. You may make it add.
Further, instead of the register 13, the adder 1 is provided by a delay circuit that is delay-controlled by the master clock pulse φM.
2 may be delayed or the output of the waveform table 2 may be delayed, and control of whether or not to give the delayed output to the adder 12 may be performed by the gate circuit according to the synthesis control data MXD.

Further, in the example of FIG. 1, the channels that can be combined are limited to the adjacent channels, but the delay time in the delay means (register 13) may be set to 2 time slots or more. Synthesis can be performed even between. Further, the register 13 (that is, the delay means) may be modified as shown in FIG. 3 so that waveform synthesis can be performed between arbitrary channels. In FIG. 3, the adder 12 is included in the shift register 15 having 15 stages, which is one less than the number of channels.
The output signal of FIG. 1 is input and sequentially shifted according to the master clock pulse φM. Therefore, the latest sampling point amplitude data of the waveform signal of each channel is held in each stage of the shift register 15. The output of each stage of the shift register 15 is input in parallel to the selector 16 and is selected according to the synthesis control data MXD ′ given from the synthesis control table 14. The selected signal is given to the adder 12. In this case, in the synthesis control table 14, data indicating the stage number of the shift register 15 in which the waveform signal of the channel to be synthesized is held is stored as synthesis control data MXD ′ for each channel. 'Is read corresponding to the time division timing of each channel. The selector 16 selects the output of the stage designated by the synthesis control data MXD ′. Therefore, by arbitrarily setting the content of the synthesis control data MXD 'corresponding to each channel, waveform synthesis with an arbitrary channel is possible. The input signal of the shift register 15 may be the output signal of the waveform table 2.

The configuration for generating the phase address data is not limited to the one using the RAM 4 as shown in the drawing, but other configurations can be arbitrarily used in design. Further, the configuration for synchronization control is not limited to the one using the comparator 10 and the gate 9 as shown in the figure, and any configuration may be used as long as the intended synchronization control can be achieved. For example, in FIG.
It is also possible to omit the comparator 10 and the gate 9 as shown in, and to directly input the output F of the frequency data table 8 to the adder 5 and to provide the adder 7 with the read output of the RAM 4. Moreover, the adder 7 for phase shift or the adder 12 for waveform synthesis may perform not only addition but also subtraction. In particular, the adder 12 may be a multiplier.

Each of the tables 3, 6, 8, 11, and 14 may be composed of an electronic storage circuit, or may be composed of data setting means such as a switch. In the case of an electronic storage circuit, a ROM (read only memory) in which desired setting contents are stored in advance may be used, or a rewritable one such as RAM (random access memory) may be used. When the RAM is used, as shown in FIG. 1, a table setting device 17 including a data setting switch and the like is provided so that each table 3,
It is preferable to be able to change the setting contents for each channel of 6, 8, 11, and 14.

The waveform table 2 may have any structure such as ROM, RAM, or a combination of a plurality of ROMs and RAMs. The modulation signal generator of the present invention is not limited to the hard-wired circuit as shown in the figure, and can be implemented by software processing using a microcomputer, and such implementation is also included in the scope of the present invention. .

[0031]

As described above, according to the present invention, when the modulation waveform signals are independently generated in the respective channels, the channels to be combined are set, and the modulation waveform signals of the plurality of set channels are set. Since a new modulated signal can be generated by synthesizing, the excellent effect that the modulated signals can be freely synthesized can be obtained.

[Brief description of drawings]

FIG. 1 is an electrical block diagram showing an embodiment of a modulation signal generator according to the present invention.

FIG. 2 is a timing chart showing the state of time division time slots of each channel in the embodiment.

FIG. 3 is a block diagram showing a modification of the waveform synthesizing delay means in the embodiment.

FIG. 4 is a block diagram showing a modification example of the synchronous control circuit portion in FIG.

[Explanation of symbols]

1 ... Channel counter, 2 ... Waveform table, 3 ... Waveform selection table, 4, 5 ... RAM and adder for generating phase address data for reading waveform table, 6 ... Synchronous channel table, 7 ... Addition for phase shift Bowl, 8 ...
Frequency data table, 9, 10 ... Synchronous control gate and comparator, 11 ... Phase table, 12, 13 ... Adder for waveform synthesis and register as delay means, 14 ... Synthesis control table, 15 ... Shift register, 16 ... Selector, 17 ... Table setting device.

Claims (5)

[Claims] 1. A waveform signal for modulation is used for a plurality of channels.
A modulation signal generator for generating divisionally, a waveform table storing a predetermined waveform, and dividing channel indication means when instructing time division timing of each of the plurality of channels, said to be generated in each channel modulation Frequency setting means for setting the frequency of the waveform signal for use, and according to the frequency set corresponding to each channel by the frequency setting means, at the time division timing instructed by the time division channel instruction means, Read-out means for respectively reading out the waveform signal of each channel from the waveform table, combined channel setting means for setting a channel to be combined with the modulating waveform signal, and the waveform of each channel read out from the waveform table Calculation of synthesizing waveform signals of channels set by the synthesizing channel setting means among signals Modulation signal generating device comprising a synthesizing means for performing. 2. The synthesizing means delays the waveform signal of each channel read from the waveform table, and the channel set by the synthesizing channel setting means using the output of the delaying means. 2. The modulation signal generator according to claim 1, which comprises an arithmetic means for performing an arithmetic operation for synthesizing waveform signals of the two signals. 3. The synthesizing channel setting means, a readable / writable synthesizing control table that stores data indicating whether or not to synthesize each channel, and a table setting means for rewriting and setting the stored contents of this table. This combining control table is read out according to the time division timing of each channel, and the delay means delays the output of the arithmetic means by a predetermined number of time division time slots. 3. The method for synthesizing the waveform signal read from the waveform table and the output of the delay means when the data read from the synthesis control table is data indicating that the data should be synthesized. Modulation signal generator. 4. The synthesizing channel setting means stores, for each channel, a readable / writable synthesizing control table that stores data that specifies a channel to be synthesized with the channel, and a table for rewriting and setting the stored contents of this table. The combining control table is read in accordance with the time division timing of each channel, and the delay means selects a shift register having a plurality of stages and an output of each stage of the shift register. 3. The modulation signal according to claim 2, further comprising a selection circuit, which controls selection of the selection circuit according to data read from the synthesis control table and provides the selected output to the arithmetic means. Generator. 5. The waveform table stores a plurality of different waveforms, and the reading means independently selects a waveform to be read from the waveform table for each channel, and reads the selected waveform signal. The modulation signal generator according to claim 1, wherein the modulation signal generator is configured as described above.