JPH0794942A - Referrence clock signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a clock signal generating circuit capable of preventing the malfunction of a microcontroller to which a clock signal outputted from an oscillation circuit is supplied by outputting an abnormality signal when the clock signal concerned is shifted from required frequency. CONSTITUTION:A reference clock signal CLK is generated by the oscillation circuit 30. A frequency signal in the signal CLK is converted into a voltage signal VL by a conversion circuit 31. At the time of receiving plural reference voltage VR1, VR2 having respectively different values, a voltage level detecting circuit 32 outputs an abnormality detection signal DET in accordance with judgement whether the voltage signal VV outputted from the circuit 31 is included within the range of the different reference voltage values VR1, VR2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection circuit for detecting abnormal oscillation of an oscillation circuit which supplies a reference clock signal to a microcontroller incorporated in a controlled device.

In recent years, a large number of microcontrollers have been incorporated in these controlled devices, ranging from home appliances such as air conditioners and electronic jars to system components of automobiles.
Various controls are performed.

These microcontrollers are provided with an oscillation circuit for controlling the timing of internal circuits, and as the oscillation circuit, a crystal oscillator, an LC oscillator, a CR are provided.
An oscillator is used. In such a microcontroller, it is necessary to reliably prevent malfunction due to abnormal oscillation of the oscillation circuit.

[0004]

2. Description of the Related Art Conventionally, an oscillator circuit using a crystal oscillator has been used as an oscillator circuit for supplying a reference clock signal to a microcontroller. An example of the oscillator circuit will be described with reference to FIG.

One terminal of a capacitor 51 is connected to both terminals of the crystal unit 50. The other terminal of each capacitor 51 is connected to the ground GND. The resistor 52 and the inverter 53 are connected in parallel to the crystal oscillator 50, and the output terminal of the inverter 53 is connected to the input terminal of a Schmitt type inverter 54 having hysteresis.

The electrical equivalent circuit of the crystal oscillator 50 is basically an RLC series circuit, but a capacitance between electrodes using the oscillator as a dielectric is further added in parallel. When an alternating voltage is applied to the crystal unit 50, the crystal unit 50 vibrates and oscillates due to the piezoelectric effect. The oscillation output signal of the crystal unit 50 is a sine wave, is converted into a square wave by the Schmidt type inverter 54, and is supplied to the microcontroller as the reference clock signal CLK.

In the oscillation circuit, the inverter 53,
Reference numeral 54 is built in the microcontroller, and the rest are configured as external elements.

[0008]

However, in home electric appliances such as air conditioners and electronic jars in which the above oscillation circuit is used, dew condensation may occur on the terminals of the external elements of the oscillation circuit. Also, in automobile system parts, dew condensation or foreign matter such as metal pieces may adhere to the terminals of the external element.

When the capacitance of the crystal unit 50 changes due to this dew condensation, the oscillation frequency deviates from the desired frequency. Further, if a metal piece is attached between both terminals of the crystal unit 50, both terminals of the crystal unit 50 may be short-circuited and oscillation may stop.

Therefore, if the oscillation frequency of the oscillator circuit deviates from the desired frequency or the oscillation stops, there is a problem that the microcontroller malfunctions or malfunctions. It is an object of the present invention to output an abnormal signal when a clock signal output from an oscillator circuit deviates from a desired frequency and to prevent malfunction of a microcontroller to which the clock signal is supplied. It is to provide a generation circuit.

[0011]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the reference clock signal CLK is generated by the oscillation circuit 30. The reference clock signal CLK
The frequency signal of is converted into a voltage signal by the conversion circuit 31. The voltage level detection circuit 32 receives the plurality of reference voltages VR1 and VR2 having different values, and the voltage signal _VL output from the conversion circuit 31 receives the plurality of reference voltages VR1 and VR.
The abnormality detection signal DET is output depending on whether it is within the range of 2.

As shown in FIG. 2, the conversion circuit comprises charge pumps 6 to 12 having low pass filters. In addition, the voltage level detection circuit includes the string resistors 15 to 17 that generate the reference voltages VR1 and VR2, and the reference voltage V1.
R1 and VR2 are composed of comparators 13 and 14 for comparing the voltage signal V _L output from the conversion circuit.

[0013]

The reference clock signal CLK is generated by the oscillator circuit 30. The frequency signal of the reference clock signal CLK is converted into a voltage signal by the conversion circuit 31. The reference signals VR1 and VR2 having different values from the voltage signal V _L output from the conversion circuit 31 are compared by the voltage level detection circuit 32, and the abnormality detection signal DET is output based on the comparison result.

The frequency signal of the reference clock signal CLK is
It is converted into a voltage signal V _L by the charge pumps 6 to 12 having a function as a low pass filter. further,
By the comparators 13 and 14, the string resistance 15 to
The reference voltages VR1 and VR2 generated at 17 are compared with the voltage signal V _L.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. As shown in FIG. 2, one terminal of the capacitor 2 is connected to each end of the crystal unit 1. The other terminal of each capacitor 2 is connected to the ground GND. The resistor 3 and the inverter 4 are connected in parallel to the crystal unit 1, and the output terminal of the inverter 4 is connected to the input terminal of a Schmitt type inverter 5 having hysteresis. Then, the reference clock signal CLK is output from the output terminal of the inverter 5.

The drain of an N-channel MOS transistor 6 is connected to the output terminal of the inverter 5.
The drain of the transistor 6 is connected to the gate and functions as a normal diode. The source of the transistor 6 is connected to a low pass filter. This low-pass filter is composed of a resistor 7 connected to the source of the transistor 6, and a capacitor 8 having one terminal connected to the resistor 7 and the other connected to the ground GND.

A resistor 9 is provided on the output side of the low-pass filter.
The drain of the N-channel MOS transistor 10 is connected via. The source of the transistor 10 is connected to the ground GND, and the gate is connected to the connection point of the resistor 11 and the N-channel MOS transistor 12 connected in series between the power supply _Vcc and the ground GND.

The gate of the transistor 12 is connected to the drain of the transistor 12. Then, a constant current flows through the transistor 12 and its drain is maintained at a constant voltage. Therefore, a constant voltage is supplied to the gate of the transistor 10, and the transistor 10 and the resistor 9 operate as a constant current source. A charge pump is configured by the low pass filter, the transistor 6 and the constant current source.

The output signal V _L of the charge pump is input to the inverting input terminals of the two comparators 13 and 14, respectively. The non-inverting input terminals of the comparators 13 and 14 have three resistors 1 connected in series between the power source _Vcc and the ground GND.
5, 16 and 17 are connected to the first connection point and the second connection point. The string resistors 15, 16 and 17 generate two types of reference voltages VR1 and VR2. When the reference clock signal CLK normally oscillates, the output voltage signal V _L of the charge pump is changed to the reference voltages VR1 and V1.
The amount of current of the constant current source is set so as to fall between R2.

When the output signal V _L of the charge pump is smaller than the reference voltages VR1 and VR2, the comparators 13 and 14 output "H" level from the output terminals. On the other hand, when the output signal V _L of the charge pump is higher than the reference voltages VR1 and VR2, the comparators 13 and 14 are "L" from the output terminals.
Output level.

The output signal of the comparator 13 is the inverter 1
5, the output signal DET1 of the inverter 15 is input to one input terminal of the NOR circuit 16. The output signal DET2 of the comparator 14 is input to the other input terminal of the NOR circuit 16. The NOR circuit 16 outputs the detection signal DET based on the output signal DET1 of the inverter 15 and the output signal DET2 of the comparator 14.

Next, the operation of the reference clock signal generating circuit configured as described above will be described with reference to FIG. When an AC voltage is applied to the crystal unit 1, the crystal unit 1 vibrates and oscillates due to the piezoelectric effect. The oscillation output signal of the crystal unit 1 is a sine wave, is converted into a square wave by the Schmitt type inverter 5, and is supplied to the microcontroller as the reference clock signal CLK.

On the other hand, the reference clock signal CLK passes through the transistor 6 and is charged in the capacitor 8. Since the transistor 6 functions as a diode, a current flows only when the drain side has a higher potential than the source side.

If the charge continues to be charged as it is, the output signal V _L of the charge pump is saturated, but a constant current source connected to the output side of the charge pump constantly discharges a predetermined current. Therefore, the output signal V _L of the charge pump shows a voltage level in a state where the charging by the clock signal CLK and the discharging of the constant current source are balanced.

Further, the charge amount charged in the capacitor 8 is proportional to the frequency of the reference clock signal CLK, and the higher the frequency, the larger the charge amount. That is, the output voltage signal V _L of the charge pump is proportional to the reference clock signal CLK.

As shown in FIG. 3, the reference clock signal CL
When the frequency of K is the normal frequency F1, the output voltage signal V _L of the charge pump is higher than the reference voltage VR2 and lower than the reference voltage VR1. Therefore, the output signal DET1 of the inverter 15 is "L" level, and the output signal D of the comparator 14 is
ET2 also becomes "L" level, and NOR16 outputs the detection signal DET of "H" level.

However, when the frequency of the reference clock signal CLK decreases to the frequency F2 due to abnormal oscillation of the oscillation circuit, the output signal V _L of the charge pump also decreases. Then, the output signal V _L of the charge pump is changed to the reference voltage VR2.
When it becomes lower, the output signal DET2 of the comparator 14 becomes "
It becomes H "level. Output signal DET1 of inverter 15
Is still at "L" level, and NOR16 to "L"
The level detection signal DET is output.

Further, when the frequency of the reference clock signal CLK rises from the normal state to F3 due to abnormal oscillation, the output voltage signal V _L of the charge pump rises. Then, the voltage signal V _L of the charge pump is changed to the reference voltage VR1.
When it becomes higher, the output signal DET1 of the inverter 15 becomes higher.
Becomes "H" level. Output signal DET2 of the comparator 14
Is still at "L" level, and NOR16 to "L"
The level detection signal DET is output.

As described above, the detection signal DET is "H" only when the frequency of the reference clock signal CLK is normal.
Is output, and "L" is output when an abnormality occurs. Therefore,
Abnormal oscillation can be easily detected by this detection signal DET.

Next, an example of use of the reference clock signal generation circuit will be described. As shown in FIG. 4, the output signal LDEC of the low voltage detection reset circuit 17 is connected to the set terminal of the RS flip-flop (FF) circuit 18, and the detection signal DET of the reference clock signal generation circuit 19 is connected to the reset terminal. The output terminal of the FF circuit 18 is connected to the reset terminal of the microcontroller.

The low voltage detection reset circuit 17 is a circuit for generating a low voltage detection signal LDEC and resetting the microcontroller when the power supply voltage falls below a set level due to some abnormality.

As shown in FIG. 5, when both the detection signal DET and the low voltage detection signal LDEC are at "H" level, it is judged that the operation is normal, and the reset signal RESET is "
When either the detection signal DET or the low voltage detection signal LDEC is at the "L" level, or both are at the "L" level, it is judged as an abnormal state and reset. The signal RESET becomes "L".

As described above, the low voltage detection reset circuit 1
By combining with 7, when abnormal oscillation is detected or the power supply voltage drops, the microcontroller is reset to notify the abnormality to the outside and
Control can be stopped immediately.

The present invention is not limited to the configuration of the above-described embodiment, and for example, the voltage level detecting circuit 2
The two comparators 13 and 14 may be modified to have hysteresis. With this hysteresis characteristic, the width of the reference voltages VR1 and VR2 can be reduced once it is determined to be abnormal. Therefore, the determination from abnormality to normal becomes strict, and the output voltage signal V _L becomes the reference voltages VR1 and VR2.
Even when there is a fluctuation in the vicinity, it is possible to prevent frequent determination from normal to abnormal or from abnormal to normal.

Further, the non-inverting input terminal and the inverting input terminal of the comparator 13 may be reversely connected and the inverter 15 may be removed, for example, without departing from the gist of the present invention. It is possible.

[0036]

As described in detail above, according to the present invention,
It is possible to provide a clock signal generation circuit capable of preventing the malfunction of the microcontroller in advance.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a reference clock signal generation circuit according to an embodiment.

FIG. 3 is a characteristic diagram showing an operation of the reference clock signal generation circuit of FIG.

FIG. 4 is a block diagram showing a usage example of an embodiment.

5 is an explanatory diagram showing an operation of the circuit of FIG.

FIG. 6 is a circuit diagram showing a conventional oscillator circuit.

[Explanation of symbols]

30 oscillator circuit 31 conversion circuit 32 voltage level detection circuit CLK reference clock signal _VL voltage signal VR1 reference voltage VR2 reference voltage DET abnormality detection signal

Claims (3)

[Claims] 1. An oscillation circuit (30) for generating a reference clock signal (CLK), a conversion circuit (31) for converting a frequency signal of the reference clock signal (CLK) into a voltage signal ( _VL ), and a plurality of conversion circuits (31). A voltage signal (V) output from the conversion circuit (31) upon receiving reference voltages (VR1, VR2) having different values.
A reference clock comprising: a voltage level detection circuit (32) for outputting an abnormality detection signal (DET) depending on whether _L ) is within the range of the plurality of reference voltages (VR1, VR2). Signal generation circuit. 2. The reference clock signal generation circuit according to claim 1, wherein the conversion circuit comprises a charge pump (6 to 12) having a function as a low-pass filter. 3. A string resistor (15) for generating a reference voltage (VR1, VR2) in the voltage level detection circuit.
~ 17), the same reference voltage (VR1, VR2) and the output voltage ( _VL ) of the conversion circuit Comparator (1
3, 14) and 1).
The reference clock signal generation circuit according to 1.