JPH0794622A - Semiconductor device and mounting method thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor in which the pin count can be increased without increasing the size of package or decreasing the pitch of the pin. CONSTITUTION:The semiconductor device comprises a semiconductor element 13, a package 12 sealing the semiconductor element 13, a plurality of lead terminals 20 connected electrically with the semiconductor element 13 and projecting from the package 12, and pin terminals 23 provided in conjunction with the lead terminals 20 each having one end connected electrically with the semiconductor element 13 and the other end projecting from the package.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor device having a semiconductor element in a package and surface-mounted on a mounting substrate, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been required to have a large number of pins and a high density mounting due to the increase in capacity and speed. Up to now, in order to increase the number of pins, it has been proposed to reduce the lead width, two-dimensionally arrange the lead terminals, and further three-dimensionally arrange the lead terminals as a multi-layer structure. Has been done.

Further, as the capacity and speed of semiconductor devices increase, thermal resistance becomes an important issue. In order to maintain stable operation of the semiconductor device, it is necessary to efficiently dissipate the heat generated by the semiconductor element and reduce the thermal resistance. Then, as a semiconductor element adopting a technique for reducing thermal resistance, for example, there are the following types. (1) A radiator fin is provided around the package to improve heat dissipation. In order to form the heat radiation fin, another member may be attached to the package or the package may be directly provided with irregularities. (2) A radiation fin or a plate with low thermal resistance bonded to the island on which the semiconductor element is mounted. (3) Part or all of the island is exposed from the package, and the island is bonded to the heat dissipation part mounted on the mounting board during mounting. (4) Forcibly cooling using a heat pipe or refrigerant.

Further, in many general semiconductor devices, lead terminals and pin terminals used for inputting and outputting electric signals project from the side surface or the lower surface of the package.
However, in recent years, there is a semiconductor device of a type in which terminals are not projected and electrodes are formed on the edges of the package.

Further, an LC as shown in FIGS.
C (Leadless Chip Carrier) 1 is known. This L
The CC 1 has a semiconductor element 2, a metallized electrode 3, a ceramic package 4, a lid 5, and a bonding wire 6. The semiconductor element 2 is wire-bonded to each metallized electrode 3.

[0006]

By the way, of the various semiconductor devices as described above, which are intended for high pin count and high density mounting, when the lead width is reduced, The thermal resistance of increases. In other words, the smaller the lead width, the more difficult it is to efficiently dissipate the heat generated in the semiconductor element. Therefore, it is considered that there is a limit to the miniaturization of the lead width. In addition, when the lead pitch is reduced, the positioning during mounting becomes more difficult. Furthermore, when a three-dimensional lead structure is adopted, it becomes difficult to manufacture a semiconductor device.

Further, in the semiconductor device of the type (1) among the various semiconductor devices described in the above items (1) to (4), it is difficult to reduce the thickness by providing the radiation fins.
In the type (2), since the area around the heat sink is covered with resin, gaps or cracks may occur due to the difference in the coefficient of thermal expansion between the heat sink and the resin, or poor jointability. is there.

Further, in the type (3),
Since an external force is applied to the lead frame and the lead terminal, it is necessary to have rigidity enough to withstand this external force. In order to secure the rigidity, it is necessary to set the lead frame and the lead terminal to be sufficiently thick. However, the thicker these are, the thicker the package is. Therefore, in order to make the package thin, it is necessary that the package material itself has sufficient rigidity. Therefore, it is difficult to select the package material.

Further, in the type (4), it is difficult to miniaturize the semiconductor device because the means for forced cooling is attached to the semiconductor device. Further, when lead terminals and pin terminals are provided in a protruding manner as in many semiconductor devices, the terminals may be bent during handling of the semiconductor device. And when the terminals are bent,
Positioning of terminals becomes difficult during mounting. Especially when an automatic mounting machine is used, the bending of the terminals is likely to cause troubles. Further, as the number of pins is increased, the pitch of the terminals and the diameter or width of the terminals are reduced, so that bending is likely to occur. Therefore, the handling of the semiconductor device becomes more difficult as the number of pins and the pitch are narrowed.

Further, in a semiconductor device of a type having no terminals, a dedicated socket is required for mounting, so that it is difficult to reduce the thickness of the mounting board. Further, when the number of pins is increased, the mounting area tends to be large.

The present invention has been made to solve the above problems, and the object of claim 1 is as follows.
It is an object of the present invention to provide a semiconductor device which can have a large number of terminals without enlarging the package and narrowing the pitch of the terminals.

Another object of the present invention is to provide a semiconductor device which can be thinned without impairing heat dissipation and rigidity. Another object of the present invention is to provide a semiconductor device mounting method capable of stacking semiconductor devices. Further, it is an object of the inventions of claims 9 and 11 to provide a stackable semiconductor device and a mounting method thereof.

[0013]

In order to achieve the above object, the invention of claim 1 is a semiconductor element, a package encapsulating the semiconductor element, and an electrical connection to the semiconductor element. And a plurality of lead terminals protruding from the package, and pin terminals juxtaposed with the lead terminals, one end of which is electrically connected to the semiconductor element and the other end of which protrudes from the package. It is in a semiconductor device.

According to a fifth aspect of the present invention, a semiconductor element having a plurality of electrodes, a heat radiation frame having a signal transmitting portion mounted on the semiconductor element and connected to the electrodes, and the semiconductor element are sealed. And a semiconductor device including a sealing portion.

According to the invention of claim 8, there is provided a semiconductor device having a plurality of electrodes, and a heat dissipation device having a plurality of through holes provided with a signal transmitting portion to which the semiconductor device is mounted and which is connected to the electrodes. In a method of mounting a semiconductor device having a frame and a sealing portion for sealing a semiconductor element, and a signal transmission portion having a cylindrical terminal fitted in a through hole, a mounting pin is inserted into the terminal. The semiconductor device mounting method is characterized in that the mounting pin is penetrated through the heat radiation frame and the mounting pin is made to reach the mounting substrate to mount the semiconductor element on the mounting substrate.

The invention according to claim 9 is a semiconductor device,
A package encapsulating the semiconductor element, a plurality of internal electrodes having one end electrically connected to the semiconductor element and the other end exposed from the main surface under the package, and the package provided with the package. At the same time, at least both ends are exposed from the upper and lower main surfaces of the package, and a semiconductor device is provided with an external electrode for lamination which is electrically insulated from the semiconductor device.

Further, according to the invention of claim 11, a semiconductor element, a package encapsulating the semiconductor element, one end electrically connected to the semiconductor element, and the other end packaged.
Internal wiring exposed from the main surface under the package and external wiring for lamination, which is provided on the package and at least both ends of which are exposed from the upper and lower main surfaces of the package and is electrically separated from the semiconductor device. In the method of mounting a semiconductor device, the semiconductor device is laminated in a plurality of stages, and the internal electrodes and external electrodes of the semiconductor device at the bottom are connected to the corresponding wiring patterns of the mounting substrate, and the internal electrodes of the semiconductor device are also connected. Is sequentially connected to the external electrodes of the lower semiconductor device and is guided to the external electrodes of the lowermost semiconductor device.

Further, the invention of claim 1 enables the semiconductor device to have multiple terminals without enlarging the package and narrowing the pitch of the terminals. Further, according to the invention of claim 5, the semiconductor device can be made thinner without impairing the heat dissipation and the rigidity.

Further, the invention of claim 8 makes it possible to easily stack the semiconductor devices. Further, the inventions of claims 9 and 11 enable the semiconductor devices to be easily stacked.

[0020]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2 show a first embodiment of the present invention, in which reference numeral 11 denotes a semiconductor device. The semiconductor device 11 includes a resin package (hereinafter, referred to as a package) 12, a first and a second semiconductor element 13,
Have fourteen. The semiconductor elements 13 and 14 are mounted on the islands 15 and 16, respectively, and are arranged side by side in the thickness direction of the package 12. Furthermore, the element forming surfaces 17 and 18 of the semiconductor elements 13 and 14 are oriented opposite to each other.

First semiconductor element 13 arranged in the upper stage
Are connected to a large number of lead terminals 20 (only two are shown) via bonding wires 19. Lead terminal 2
0s are radially arranged around the semiconductor element 13 and project from the side surface 21 of the package 12 and are processed into a gull wing type. Here, in order to obtain the lead terminal 20, it is possible to use various general techniques such as punching the lead terminal 20 from the lead frame. Further, the lead end 20 may protrude from two side surfaces of the package 12 or may protrude from four side surfaces.

The second semiconductor element 14 arranged in the lower stage
Is connected to a plate-shaped pin terminal support 22 via a bonding wire 19. That is, the pin terminal support 2
2, a large number of pin terminals 23 (only a part of which are shown) are hung vertically downward, and as shown in FIG.
A large number of wirings 24 (only a part of which are shown) that are individually connected to the wiring 3 are formed. The bonding wire 19 is provided between the second semiconductor element 14 and each wiring 24, and
The semiconductor element 14 and each pin terminal 23 are connected via a bonding wire 19 and a wiring 24.

The pin terminal 23 is the lower surface 25 of the package 12.
Is projected almost vertically from. Further, the tip of the pin terminal 23 reaches a little below the lead terminal 20. Here, as the shape of the package 12, various general shapes such as a square and a rectangular parallelepiped can be adopted.

In the semiconductor device 11 as described above,
Since the lead terminal 20 and the pin terminal 23 are arranged side by side, the diameter and width of the terminal can be reduced, the pitch can be narrowed,
The number of terminals can be increased without making the terminals multi-layered. As a result, it becomes possible to seal the plurality of semiconductor elements 13 and 14 without enlarging the package 12. Further, high density at the time of mounting becomes possible.

Further, since it is not necessary to miniaturize the terminals 20 and 23, it is possible to maintain the heat dissipation characteristic of each of the terminals 20 and 23 to the same degree as the conventional one. Further, when the number of terminals is set to the same level as the conventional one, the diameter, width, pitch, etc. of the terminals can be increased without increasing the size of the package 12. In this case, the heat dissipation characteristics can be improved, the thermal resistance can be reduced, and the positioning at the time of mounting becomes easy.

The present invention can be variously modified without departing from the scope of the invention. For example, although resin is used as the material of the package 12 in this embodiment, various general materials such as ceramics can be applied to the package 12.

Further, in this embodiment, a plurality of semiconductor elements 1 are used.
3, 14 are used, and these are connected to the lead terminal 20 or the pin terminal 23. For example, as in the semiconductor device 31 shown in FIG. Surfaces 17 and 18, and each element formation surface 17,
18 may be connected to the lead terminal 20 or the pin terminal 23.

In this semiconductor device 31, the semiconductor element 32 is inserted into the holding hole 34 of the plate-shaped semiconductor element support 33, and the element forming surfaces 17 and 18 are exposed on the front and back of the semiconductor element support 33. There is. Further, the semiconductor element support 33 is interposed between the lead terminal 20 and the pin terminal support 22 to hold them.

Further, as in the semiconductor device 41 shown in FIG. 4, the package 42 may have a two-layer structure, and the semiconductor elements 13 and 14 may be sealed in the layers 43 and 44, respectively. Lead terminal 2
0 projects from the side surface 21 of the upper layer 43 of the package 42, and the pin terminals 23 project from the lower surface 25 of the lower layer 44. Both layers 43 and 44 are integrally joined. In this semiconductor device 41, the semiconductor element 13,
The element forming surfaces 17 and 18 of 14 are oriented in the same direction.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6 show a second embodiment of the present invention, in which reference numeral 51 denotes a semiconductor device. The semiconductor device 51 includes a heat radiation frame (hereinafter referred to as a frame) 52 made of metal. This frame 52 is formed into a substantially square plate shape and has an upper surface 5
3 has a concave portion 54 at the center. A semiconductor element 55 is housed in the recess 54, and the semiconductor element 55 is bonded to the bottom of the recess 54 with an adhesive 56.

An insulating film 57 is coated on the frame 52. The insulating film 57 is coated on both plate surfaces and side surfaces of the frame 52, but the concave portion 54 is formed.
Is not applied to the inner wall or bottom of the. Furthermore, frame 5
A large number of wirings 58 are formed on the upper surface 53 of the second wiring 58, and the wirings 58 are arranged radially around the recess 54. In addition, a large number of bumps 59 are provided around the recess 54.
Is formed, and the end of the wiring 58 on the side of the recess 54 is electrically connected to the bump 59.

Here, the wiring 58, the bump 59 and the frame
It is insulated from the frame 52 by an insulating film 57. Also,
As a method of manufacturing the wiring 58, various general methods such as etching can be adopted.

The semiconductor element 55 includes the bonding wire 6
It is connected to the bump 59 through 0. Further, the semiconductor element 55 and the bonding wire 60 are not
It is sealed by the sealing resin 61 as a sealing portion supplied to the. The sealing resin 61 rises from the frame 52 and is formed in a rectangular shape. And the sealing resin 6
1 covers the bump 59 and a part of the wiring 58,
These are protected together with the semiconductor element 55 and the bonding wire 60.

Here, various general methods such as transfer molding, potting, and dipping can be adopted as the sealing method. Frame 5
2 has a large number of through holes 62. These through holes 62 are arranged along the peripheral portion of the frame 52 and penetrate the frame 52 in the thickness direction. The opening shape of these through holes 62 is a perfect circle, and the opening diameters thereof are substantially the same. Further, in each through hole 62, the diameter dimension is substantially uniform over the entire axial length. And the through hole 6
An insulating film 57 is also coated on the inner peripheral surface of 2.

Reference numeral 63 in both figures denotes a terminal made of a conductive material. Each terminal 63 has a concentric cylindrical shape and is inserted into the through hole 62. The outer diameter dimension of the terminal 63 is substantially the same as the inner diameter dimension of the through hole 62. Further, flanges 64a and 64b are formed on both ends of the terminal 63 in the axial direction so as to spread outward.
4b is locked to the peripheral portion of the through hole 62. The flange 64a on the upper surface 53 side of the frame 52 is electrically connected to the end of the wiring 58.

Next, a method of mounting the above-mentioned semiconductor device 51 will be described. As shown in FIG. 1, the semiconductor device 5
The mounting pin 71 is used for mounting 1. That is, the mounting pin 71 is formed in a concentric cylindrical shape, has a flange 72 at one end, and is sharpened at the other end. The mounting pin 71 is inserted into the terminal 63 during mounting,
It penetrates the frame 52. Further, the tips of the mounting pins 71 enter the insertion holes 74 of the mounting board 73, and the flanges 72 are locked to the flanges 64 a of the terminals 63. The diameter of the mounting pin 71 is substantially the same as the inner diameter of the terminal 62 and the inner diameter of the insertion hole 74 of the mounting board 73. And mounting pin 7
1 couples the semiconductor device 51 and the mounting substrate 73.

The terminal 63 of the semiconductor device 51 is a mounting board 73.
The wiring 75 formed in the above is contacted so that it can be energized. And
The bonding wire 60, the bump 59, the wiring 58 of the frame 52, and the terminal 63 form a signal transmitting portion 65, and the signal transmitting portion 65 electrically connects the semiconductor element 55 and the wiring 76 of the mounting substrate 74. Transmit a signal.

In the semiconductor device 51 as described above,
Since the semiconductor element 55 is bonded to the metal frame 52, the heat generated in the semiconductor element 55 is transferred to the frame 52. Further, the sealing resin 61 for sealing the semiconductor element 55 is supplied only to a part (recessed portion 54) of the frame 52, and most of the frame 52 is exposed to the outside air. In general, the thermal conductivity of metal is 10 times higher than that of resin. Therefore, compared with the case where the semiconductor element 55 is covered with the resin package or the case where a part of the heat dissipation plate is exposed from the resin package, the heat can be efficiently released and the thermal resistance can be reduced. It is possible.

Further, in the above-mentioned semiconductor device 51,
Since there is no terminal for transmitting an electronic signal, handling can be performed without considering bending of the terminal. Therefore, handling is easy. Further, it is possible to prevent the occurrence of mounting defects due to the bending of the terminals and facilitate the alignment of the semiconductor device 51.

Further, since the mounting can be performed without using a dedicated socket and the mounting pins 71 are inserted into the semiconductor device 51 and the mounting substrate 73, the thickness and mounting area of the mounting substrate 73 do not become large.

In the mounting method described above, the mounting pin 71 is inserted into the frame 52 and the mounting substrate 73 to connect them, so that the mounting strength is supplemented by the mounting pin 71. Therefore, even if the frame 52 is set thin,
Sufficient rigidity can be secured after mounting. Therefore, the semiconductor device 51 can be thinned.

The present invention can be variously modified without departing from the scope of the invention. For example, in the present embodiment, metal is used as the material of the frame 52, but the same effect can be obtained by using ceramic or the like. In this case, the insulating film 57 becomes unnecessary.

Further, in this embodiment, the semiconductor element 55 is housed in the recess 54 of the frame 52.
The upper surface 53 of the frame 52 may be flat and the semiconductor element 55 may be placed on it. Further, a protrusion may be provided on the upper surface 53 of the frame 52, and the semiconductor element 55 may be placed on this protrusion.

In this embodiment, the terminal 63 is used to electrically connect the wiring 58 of the frame 52 and the wiring 75 of the mounting board 73. For example, the mounting pin 71 is made conductive. Alternatively, the terminal 63 can be omitted by forming a conductive film on the insulating film 57 on the inner peripheral surface of the through hole 62.

Further, by making a simple modification to the semiconductor device 51 of this embodiment, it becomes possible to form a multilayer as shown in FIGS. 7 and 9. That is, in FIG. 7, the semiconductor devices 51 and 81 are concentrically stacked on each other in upper and lower two stages and mounted on the mounting substrate 83. The frame 52 of the upper semiconductor device 51 is in contact with the sealing resin 61 of the lower semiconductor device 81. Further, as shown in FIG. 8, a large number of terminals 85 and 86 are incorporated in the frame 84 of the lower semiconductor device 81, and these terminals are doubly arranged around the sealing resin 61. The wiring 58 is connected to the inner terminals 85, but the wiring 58 is not connected to the outer terminals 86. The outer terminal 86 is in a positional relationship corresponding to the terminal 63 of the upper semiconductor device 51.

As shown in FIG. 7, the lower semiconductor device 81
Mounting pin 87 is inserted into terminal 85 inside
The mounting pins 87 connect the frame 84 to the mounting board 83. In addition, the frame 52 of the upper semiconductor device 51
The mounting pin 88 inserted in the lower part of the semiconductor device 81 is also inserted in the outer terminal 86 of the lower semiconductor device 81.
4 to reach the mounting board 83. The outer mounting pins 89 integrally connect the upper and lower frames 52 and 84 to the mounting substrate 83.

In this way, by arranging the terminals 85 and 86 in the frame 84 of the lower semiconductor device 81 in a doubled manner, the semiconductor devices 51 and 81 can be stacked in two layers. Furthermore, the area occupied by the mounting board 83 can be reduced, and the mounting density can be increased.
Then, when there is a space above the mounting substrate 83, this space can be effectively used.

By increasing the number of rows of terminals, it becomes possible to stack more semiconductor devices. 9 and 10 show an example in which the semiconductor devices 51, 81 and 91 are stacked in three layers. In the semiconductor device 81 in the middle stage, the terminals 85 and 86 are arranged in double, and in the semiconductor device 91 in the lower stage, the terminals 95, 96 and 97 are arranged in triple. Furthermore, as shown in FIG. 10, the wiring 58 is connected to the innermost terminal 95, but the wiring 58 is not connected to the other terminals 96 and 97.

The mounting pin 99 inserted into the innermost terminal 95 connects the frame 52 of the semiconductor device 51 to the mounting substrate 103. Further, the mounting pin 100 inserted into the intermediate terminal 96 has the frames 52 and 8 in the middle and lower stages.
4 is connected to the mounting substrate 103. Further, the mounting pin 101 inserted into the outermost terminal 97 connects the three frames 52, 84 and 102 to the mounting substrate 103.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 11 shows a third embodiment of the present invention, in which reference numeral 111 is a semiconductor device.
This semiconductor device 111 is an LCC (Leadless Chip Carrie).
r) type, in which a semiconductor element 113 is sealed in a rectangular parallelepiped ceramic package (hereinafter referred to as a package) 112. The recess 112 is on the package 112.
14 is formed on the side surface of the recess 114.
A step is formed that narrows as it gets closer to the bottom. And
The semiconductor element 113 is bonded to the bottom of the recess 114, and the internal space of the recess 114 is closed by a lid 115 made of metal.

The package 112 includes a large number of internal electrodes 1
16 and the same number of external electrodes 117 as these are metallized. These are embedded in the package 112 and are arranged radially. Of these, one end of the internal electrode 116 is horizontally exposed in the recess 114, and is connected to the semiconductor element 113 via the bonding wire 118. Further, the internal electrode 116 extends toward a lower surface 119 as a main surface below the package 112, and the other end of the internal electrode 116 is at the other end of the package 11.
2 is exposed on the lower surface 119.

The external electrodes 117 are arranged outside the internal electrodes 116 and are exposed on the four side surfaces of the package 112. The external electrodes 117 are also exposed at the edges of the lower surface 119 and the upper surface 120 of the package 112. That is, the upper surface 1 of the package 112
Only the external electrode 117 is led out to the lower surface 20
Both the internal electrode 116 and the external electrode 117 are led out to 19. Further, the external electrode 117 is the semiconductor element 1
13 and the internal electrode 116 are not electrically connected.

The internal electrode 116 is connected to a wiring pattern (hereinafter referred to as wiring) 122 of the mounting substrate 121, and forms a signal path between the semiconductor element 113 and the wiring 122. The wiring 122 of the mounting substrate 121 is arranged so as to contact only the internal electrodes 116 and avoid the external electrodes 117. Here, as a method of joining the internal electrode 116 and the wiring 122, various joining methods for general LCC can be adopted. Further, other various joining methods can be applied as long as the conductivity can be secured.

Next, a method of mounting the above semiconductor device 111 will be described. As shown in FIG. 12, the semiconductor device 111
Are stacked in two layers. The internal electrode 116a of the lower semiconductor device 111a is connected to the wiring 122 of the mounting substrate 121. Furthermore, the external electrode 117a is mounted on the mounting substrate 121.
Is connected to the wiring for the external electrode formed on. In FIG. 12, the wiring for the external electrode is the wiring 12 for the internal electrode.
Hiding behind the shadow of 2.

Internal electrodes 11 of the upper semiconductor device 111b
6b is in contact with the external electrode 117 of the lower semiconductor device 111a, and the upper internal electrode 116b and the lower external electrode 117a are connected. As a result, as shown in FIG. 13, independent conduction paths 12 are provided for each of the lower semiconductor element 113a and the upper semiconductor device 113b.
3, 124 are configured.

According to such a semiconductor device 111 and the mounting method thereof, the semiconductor devices 111 can be stacked and mounted. Then, the area occupied by the semiconductor device 111 is reduced, and the mounting efficiency is increased. Further, when there is a space in the space above the mounting board 121, this space can be effectively used.

The present invention can be variously modified without departing from the scope of the invention. For example, in this embodiment, the internal electrode 116 and the external electrode 117 are embedded in the package 112, but the electrode material is packaged.
The inner electrode 116 and the outer electrode 11 can be covered even if they are covered with the di-112.
7 and can be obtained. Further, in this embodiment, the internal electrodes 116 and the external electrodes 117 are metallized, but the present invention is not limited to this, and the electrodes 116, 117 are formed by properly forming the lead terminals. You may use as.

In this embodiment, ceramic is used as the material of the package 112, but the same effect can be obtained by using resin for the material of the package 112, for example.

Further, in the present embodiment, the internal electrodes 116 and the external electrodes 117 are radially arranged, and these are arranged in four directions of the package 112, but the present invention is not limited to this. For example, the electrodes 116 and 117 may be arranged in two directions.

Further, in the present embodiment, the external electrode 117 is exposed on the side surface of the package 112, but the external electrode 1
Only both ends of 17 may be exposed from the package 112. In addition, as shown in FIGS.
It is also possible to stack 11 in three or more layers.

For example, in the case of stacking three layers, the internal electrodes 11 are included in the semiconductor devices 111b and 111c in the second and higher layers.
Every other 6b and 116c are wire-bonded to the semiconductor element 113, and the connected internal electrodes 116b.
₁ and 116c ₁ and internal electrodes 116b ₂ and 116 not connected to
The c ₂ and the c ₂ are alternately arranged. Furthermore, each semiconductor device 11
The directions of 1b and 111c are alternately shifted by 180 degrees.

Connected internal electrodes 116b ₁ and 116c ₁
Are both connected to the external electrodes 117a and 117b in the lower stage, and are connected to the mounting substrate 121 via the external electrodes 117a in the semiconductor device 111a in the lowest stage. On the other hand, the internal electrode 116b ₂ of the middle semiconductor device 111b
Is the internal electrode 116c ₁ of the uppermost semiconductor device 111c.
In addition, the external electrode 117a of the semiconductor device 111a at the bottom is opened so as not to hinder the conduction. The orientation of the lowermost semiconductor device 111a is arbitrary.

By alternately connecting the semiconductor device and the internal electrodes one by one in this manner, a three-stage stacking becomes possible. Further, by changing the connection between the semiconductor device and the internal electrode to two, three, and so on, it is possible to stack four or more layers.

[0064]

As described above, the invention of claim 1 is
A semiconductor element, a package encapsulating the semiconductor element, and a package electrically connected to the semiconductor element.
A plurality of lead terminals protruding from the package, and a pin terminal juxtaposed with the lead terminal, one end of which is electrically connected to the semiconductor element and the other end of which protrudes from the package.

Therefore, the invention of claim 1 is a package.
There is an effect that the number of terminals of the semiconductor device can be increased without enlarging the size and narrowing the pitch of terminals. According to a fifth aspect of the present invention, a semiconductor element having a plurality of electrodes, a heat radiation frame having a signal transmission portion mounted with the semiconductor element and connected to the electrodes, and a sealing element for sealing the semiconductor element. And a section.

Therefore, the invention of claim 5 has an effect that the semiconductor device can be made thin without impairing the heat dissipation and the rigidity. Further, the invention according to claim 8 is a heat dissipation frame having a semiconductor element having a plurality of electrodes, a signal transmitting portion to which the semiconductor element is mounted and connected to the electrodes, and a plurality of through holes being provided. In a method of mounting a semiconductor device having a tubular terminal in which a signal transmitting portion is internally fitted in a through hole, a semiconductor device is mounted, and a sealing portion for sealing a semiconductor element is provided. -Mount the semiconductor device on the mounting board by penetrating the mounting pin into the mounting board and making the mounting pin reach the mounting board.

Therefore, the invention of claim 8 has an effect that semiconductor devices can be easily laminated. According to a ninth aspect of the invention, a semiconductor element, a package encapsulating the semiconductor element, one end electrically connected to the semiconductor element, and the other end exposed from the main surface under the package. And a plurality of external electrodes provided on the package and at least both ends of which are exposed from the upper and lower main surfaces of the package and electrically insulated from the semiconductor device.

Further, according to the invention of claim 11, a semiconductor element, a package encapsulating the semiconductor element, one end electrically connected to the semiconductor element and the other end packaged.
Internal wiring exposed from the main surface under the package and external wiring for lamination, which is provided on the package and at least both ends of which are exposed from the upper and lower main surfaces of the package and is electrically separated from the semiconductor device. In the method of mounting a semiconductor device, the semiconductor device is laminated in a plurality of stages, and the internal electrodes and external electrodes of the semiconductor device at the bottom are connected to the corresponding wiring patterns of the mounting substrate, and the internal electrodes of the semiconductor device are also connected. Are sequentially connected to the external electrodes of the lower semiconductor device and guided to the external electrodes of the lowermost semiconductor device. Therefore, the inventions of claims 9 and 11 have an effect that the semiconductor devices can be easily stacked.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged view showing a connection between a semiconductor element and a pin terminal.

FIG. 3 is a sectional view showing a modified example.

FIG. 4 is a cross-sectional view showing another modification.

FIG. 5 is a sectional view showing a semiconductor device and a mounting method thereof according to a second embodiment of the present invention.

FIG. 6 is a perspective view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a side view showing an example of a two-layer stack of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a plan view showing a lower semiconductor device.

FIG. 9 is a side view showing a three-level stacked example of the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a plan view showing the lowermost semiconductor device.

FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a sectional view showing an example of a two-layer stack of a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is an explanatory diagram showing a connection state in the case of a two-layer stack.

FIG. 14 is a sectional view showing an example of a three-step stacking of a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a connection state in the case of a three-layer stack.

FIG. 16 is an explanatory diagram showing a connection between a semiconductor element and an internal electrode in the uppermost semiconductor device.

FIG. 17 is an explanatory diagram showing a connection state in the case of a three-layer stack.

FIG. 18 is an explanatory view showing the connection between the semiconductor element and the internal electrode in the semiconductor device in the middle stage.

FIG. 19 is a perspective view showing a general LCC.

FIG. 20 is a sectional view showing a general LCC.

[Explanation of symbols]

11 ... Semiconductor device, 12 ... Package, 13, 14 ... Semiconductor element, 20 ... Lead terminal, 22 ... Pin terminal support, 23 ... Pin terminal, 24 ... Wiring, 31 ... Semiconductor element,
32 ... Semiconductor element, 33 ... Semiconductor element support, 17 ... Element formation surface (front surface), 18 ... Element formation surface (back surface), 51 ...
Semiconductor element, 52 ... Heat dissipation frame, 55 ... Semiconductor element,
61 ... Sealing resin (sealing part), 62 ... Through hole, 63 ... Terminal, 65 ... Signal transmitting part, 71 ... Mounting pin, 73 ... Mounting board, 111 ... Semiconductor element, 112 ... Package, 116
... internal electrode, 117 ... external electrode, 119 ... package lower surface (lower main surface), 120 ... package upper surface (upper main surface), 121 ... mounting substrate, 122 ... wiring pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 25/065 25/07 25/18

Claims (11)

[Claims] 1. A semiconductor element, a package encapsulating the semiconductor element, a plurality of lead terminals electrically connected to the semiconductor element and protruding from the package, and the lead. -A semiconductor device having a pin terminal and one end electrically connected to the semiconductor element and the other end protruding from the package. 2. The semiconductor according to claim 1, wherein a plurality of semiconductor elements are provided in the same package, and each semiconductor element is selectively connected to a lead terminal or a pin terminal. apparatus. 3. A semiconductor element support for holding the semiconductor element by exposing a front surface and a back surface of the semiconductor element, wherein one of a lead terminal and a pin terminal is electrically connected to the surface of the semiconductor element. 2. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to the other side, and the other side is electrically connected to the back surface of the semiconductor element. 4. The pin terminal supporting body for supporting the pin terminal is provided, and the wiring electrically connected to the pin terminal is formed on the pin terminal supporting body. The semiconductor device described. 5. A semiconductor element having a plurality of electrodes, a heat radiation frame having a signal transmitting portion mounted on the semiconductor element and connected to the electrodes, and a sealing portion for sealing the semiconductor element. A semiconductor device comprising: 6. The semiconductor device according to claim 5, wherein the heat dissipation frame is provided with a plurality of through holes for inserting mounting pins for mounting. 7. The signal transmitting section has a cylindrical terminal which is fitted in the through hole and into which the mounting pin is inserted, and the mounting pin is inserted into the terminal. Semiconductor device. 8. A semiconductor element having a plurality of electrodes, a heat radiation frame having a plurality of through holes, which has a signal transmitting portion connected to the electrodes and mounted with the semiconductor element, A method for mounting a semiconductor device, comprising: a sealing part for sealing a semiconductor element, wherein the signal transmission part has a cylindrical terminal fitted in the through hole. A method of mounting a semiconductor device, comprising: mounting the semiconductor element on a mounting board by penetrating the mounting pin through a heat radiation frame and by making the mounting pin reach a mounting board. 9. A semiconductor element, a package encapsulating the semiconductor element, and a plurality of one ends of which are electrically connected to the semiconductor element and the other ends of which are exposed from a main surface under the package. A semiconductor device comprising: the internal electrode; and an external electrode for lamination, which is provided on the package and at least both ends of which are exposed from the upper and lower main surfaces of the package and electrically insulated from the semiconductor device. 10. The semiconductor device according to claim 9, wherein the internal electrode is selectively connected to the semiconductor element. 11. A semiconductor element, a package encapsulating the semiconductor element, and an interior in which one end is electrically connected to the semiconductor element and the other end is exposed from a main surface under the package. Mounting method of semiconductor device including wiring and external wiring for lamination, which is provided in the package and at least both ends of which are exposed from upper and lower main surfaces of the package and electrically separated from the semiconductor device In the above, the semiconductor devices are stacked in a plurality of layers, the inner electrodes and the outer electrodes of the lowermost semiconductor device are connected to the corresponding wiring patterns of the mounting substrate, and the inner electrodes of the upper semiconductor device are sequentially arranged in the lower layer. The method for mounting a semiconductor device, wherein the semiconductor device is connected to an external electrode of the semiconductor device and led to the external electrode of the lowermost semiconductor device.