JPH0794518A - Processing method for semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor wafer from being contaminated by impurities existing in a manufacturing apparatus by a simple method. CONSTITUTION:Silicon oxide films 21 are formed on the surfaces of a boat 19 and an inner silica tube 11 contaminated by a high-melting-point metal (tungsten). And silicon wafers 18e which neither have any tungsten silicide film nor have been contaminated are mounted on the boat 19 and heat-treated (800 deg.C) in a vacuum. The measurement of the degree of contamination on the surfaces of the silicon wafers 18e has proved that it is lower than the detection limit (1E8atom/cm<2>) of a measuring apparatus. Namely. it becomes possible to suppress the scattering of the tungsten contaminating the surfaces of the boat 19 and the inner silica tube 11 by the silicon oxide films 21 covering the surfaces. As the result, it becomes possible to prevent the surfaces of the silicon wafers 18e from being recontaminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of processing a semiconductor device, and more particularly to a method of preventing a semiconductor wafer from being contaminated by impurities existing in the manufacturing device in the manufacturing process of the semiconductor device. .

[0002]

2. Description of the Related Art Polysilicon has been widely used as an electrode wiring material in a semiconductor device. But,
Even if impurities are added to polysilicon in order to reduce the specific resistance, the effect of reducing the specific resistance is limited. for that reason,
Refractory metal silicide (WSi ₂ , MoSi ₂ , TiSi _2, etc.) whose specific resistance is one digit or more smaller than that of polysilicon
Has come to be used as an electrode wiring material.

However, when a silicon wafer having a refractory metal silicide film formed on its surface is subjected to heat treatment (including not only annealing but also general heating of the silicon wafer such as CVD method), the surface of the silicon wafer has a high melting point. Metal splashes. Then, the heat treatment apparatus (specifically, the surface of the boat or the inner wall of the electric furnace) is contaminated by the scattered high melting point metal. Then, when another silicon wafer is heat-treated using the heat treatment apparatus contaminated with the refractory metal, the silicon wafer is re-contaminated by the refractory metal scattered again from the heat treatment apparatus. further,
The refractory metal adhering to the surface of the silicon wafer is diffused inside by heat treatment.

As a result, the semiconductor device formed on the silicon wafer suffers from problems such as an increase in junction leak, a decrease in oxide film withstand voltage and carrier lifetime, and deterioration of hold characteristics in the case of DRAM. These disadvantages become more remarkable as the semiconductor device becomes finer. Therefore, in recent years, as semiconductor devices have been highly integrated and further miniaturized, the adverse effects of recontamination of these silicon wafers cannot be ignored.

Therefore, conventionally, a heat treatment apparatus for treating a silicon wafer having a refractory metal silicide film formed on its surface has been specialized. That is, a heat treatment apparatus for processing a silicon wafer having a refractory metal silicide film formed on its surface and a heat treatment apparatus for processing a silicon wafer having no refractory metal silicide film are completely separated from each other to prevent recontamination of the silicon wafer. That is why.

[0006]

However, in order to completely separate the heat treatment apparatus, not only is the electric furnace dedicated,
It is necessary to replace the boat every time it is specialized and heat treated. Also, every time the quartz tube or boat constituting the electric furnace is replaced, they must be cleaned (generally using hydrofluoric acid).

Therefore, completely separating the heat treatment apparatus in this way leads to an increase in the size and complexity of the manufacturing equipment and an increase in the manufacturing cost. The present invention has been made to solve the above problems, and an object thereof is to prevent a semiconductor wafer from being contaminated by impurities existing in a manufacturing apparatus by a simple method. Is to provide a processing method.

[0008]

According to the present invention, in a semiconductor device manufacturing process, prior to heat treatment of a semiconductor wafer by a heat treatment apparatus, a coating film is formed inside the heat treatment apparatus, and impurities adhered inside the heat treatment apparatus. The gist of the invention is to prevent a semiconductor wafer processed by the method from being contaminated.

[0009]

Therefore, according to the present invention, by forming the coating film inside the heat treatment apparatus, the impurities adhering to the inside of the heat treatment apparatus can be covered. As a result, it is possible to prevent the impurities adhering to the inside of the heat treatment apparatus from scattering and adhering to the surface of the semiconductor wafer to be processed and contaminating the semiconductor wafer.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing a cross section of a general vertical electric furnace used for manufacturing a semiconductor device.

The vertical electric furnace 10 comprises an inner quartz tube 11, an outer quartz tube 12, a heater 13, an elevator 14, a gas introduction pipe 15, an exhaust pipe 16 and a pump 17. The cylindrical inner quartz tube 11 is fitted in a tea-tube-shaped outer quartz tube 12 having a lid at the top with a predetermined gap. The outer circumference of the outer quartz tube 12 is the heater 1
It is designed to be heated by 3. Gas introduction pipe 1
5 is inserted through the bottom of the inner quartz tube 11, and the exhaust pipe 16
Is inserted into the bottom of the outer quartz tube 12. The elevator 14 that moves up and down, when moving upward,
It is designed to close the bottom of 12.

On the elevator 14, a boat 19 on which a plurality of silicon wafers 18 are mounted is placed. Therefore, the boat 19 moves in and out of the inner quartz tube 11 by the vertical movement of the elevator 14. Further, the gas sent from the outside through the gas introduction pipe 15 is guided from the bottom of the inner quartz pipe 11 to each silicon wafer 18 on the boat 19. Then, the gas is swept by the pump 17, flows from the upper part of the inner quartz tube 11 through the gap between the outer quartz tube 12 and the inner quartz tube 11 from the upper side to the lower side, and is exhausted from the exhaust pipe 16.

Among the silicon wafers 18 mounted on the boat 19, a predetermined number of silicon wafers 18 mounted on the upper and lower parts of the boat 19 (for example, the upper 3 and lower 7) are dummy. . The dummy wafers 18 are provided in order to equalize the temperature conditions and the gas flow conditions for each silicon wafer 18.

An enlarged view of the portion A in FIG. 1 is shown in FIGS. 2 and 3. Next, the method and operation of this embodiment will be described. First, I examined how much the latter silicon wafer would be contaminated when a silicon wafer with a refractory metal silicide film formed on its surface and a silicon wafer without it were mounted on the same boat and heat-treated. .

That is, as shown in FIG. 2, a silicon wafer 18a having a tungsten silicide (WSi ₂ ) film 20 formed on its surface and a silicon wafer 18b having no tungsten silicide (WSi ₂ ) film 20 are mounted on the same boat 19 in a vacuum. Heat treatment (800 ° C) is performed. Then, the silicon wafer 18a
Tungsten is scattered from the tungsten silicide film 20 on the surface of, and the surfaces of the silicon wafer 18b, the boat 19, and the vertical electric furnace 10 (specifically, the inner quartz tube 11 and the outer quartz tube 12) are contaminated by the tungsten. . Here, the degree of contamination on the surface of the silicon wafer 18b was measured and found to be 6E12 atoms / cm ² .

Next, when another silicon wafer is heat-treated by using a heat treatment apparatus contaminated with refractory metal,
I checked how much the silicon wafer was contaminated. That is, the silicon wafers 18a and 18b are taken out, and instead, the silicon wafer 18c in which the tungsten silicide film is not formed and is not contaminated.
(Not shown) is mounted on the contaminated boat 19 described above. Then, in the same contaminated vertical electric furnace 10, heat treatment (800 ° C.) is performed in vacuum. Then boat 19
Also, tungsten contaminating the surface of the inner quartz tube 11 scatters, and the surface of the silicon wafer 18c is re-contaminated by the tungsten. Here, if the contamination degree of the surface of the silicon wafer 18c is measured, it is 7E.
It was 11 atoms / cm ² . Although the surface of the outer quartz tube 12 is also contaminated, since the gas flow path is as described above, the gas touching the surface of the outer quartz tube 12 does not touch the silicon wafer 18, and Contamination of the quartz tube 12 is irrelevant to recontamination of the silicon wafer 18c.

Then, the same process was repeated once for another silicon wafer. That is, the silicon wafer 18c is taken out, and instead, the silicon wafer 18d (not shown) in which the tungsten silicide film is not formed and which is not contaminated is mounted on the contaminated boat 19. Then, in the same contaminated vertical electric furnace 10, heat treatment (800 ° C.) is performed in vacuum. Then, tungsten contaminating the surfaces of the boat 19 and the inner quartz tube 11 is scattered, and the surface of the silicon wafer 18d is re-contaminated by the tungsten. Here, the degree of contamination on the surface of the silicon wafer 18d was measured and found to be 5E11 atoms / cm ² .

As described above, refractory metal silicide (WS
i ₂ film 20) is formed on the surface of a silicon wafer (18
When a) and the unformed silicon wafer (18b) are mounted on the same boat 19 and subjected to heat treatment, the latter silicon wafer (18a) is seriously contaminated (contamination degree;
6E12 atoms / cm ² ). The recontamination caused by the common use of the boat 19 and the electric furnace 10 (specifically, the inner quartz tube 11) shows a high value although it is milder than the initial pollution (pollution degree; 7E11 atoms /
cm ² ). Also, it can be seen that recontamination is unavoidable as long as the boat 19 and the electric furnace 10 that have been once contaminated are used.

Therefore, in the present embodiment, recontamination is prevented by a simple method of forming a silicon oxide film on the surfaces of the boat 19 and the inner quartz tube 11 that have been once contaminated.

That is, on the surfaces of the boat 19 and the inner quartz tube 11 contaminated by the method shown in FIG. 2, the silicon oxide film 21 (film thickness: 20) as shown in FIG.
0 nm) is formed. The formation of the silicon oxide film 21 is
It is performed by a low pressure CVD method using monosilane (SiH ₄ ) and nitrous oxide (N ₂ O).

Then, the silicon wafer 18e in which the tungsten silicide film is not formed and is not contaminated
Is mounted on a boat 19 having a silicon oxide film 21 formed thereon, and heat treatment (800 ° C.) is performed in vacuum. When the degree of contamination on the surface of the silicon wafer 18e was measured, it was below the detection limit (1E8 atoms / cm ² ) of the measuring device. That is, compared with the case where the silicon oxide film 21 is not formed (contamination degree; 7E11 atoms / cm ² ), the contamination degree can be reduced by four digits or more in this embodiment.

As described above, in the present embodiment, the scattering of tungsten contaminating the surfaces of the boat 19 and the inner quartz tube 11 can be suppressed by the silicon oxide film 21 covering the surfaces. As a result, it is possible to prevent the surface of the silicon wafer 18e from being re-contaminated.

The present invention is limited to the above embodiment
Instead, it may be implemented as follows. 1) Not only tungsten silicide but other refractory metals
Silicide (MoSi ₂, TiSi₂Etc.)
To carry out.

2) The same applies not only to the contamination when the refractory metal silicide is formed, but also to the contamination when the refractory metal simple substance is formed. For example, it is performed when tungsten alone is formed by a CVD method instead of silicide, or when titanium nitride (TiN) is formed by a CVD method.

3) The same method is applied not only to contamination by refractory metal but also contamination by other impurities. 4) The same operation is performed not only in the vertical electric furnace 10 shown in FIG. 1 but also in other types of heat treatment apparatuses.

5) The thickness of the silicon oxide film 21 is 200 nm
However, the film thickness is not limited to the above, but is set to a necessary and sufficient film thickness in accordance with the impurities as the contamination source and the method of forming the silicon oxide film 21.

6) The silicon oxide film 21 is replaced with a silicon nitride film. The silicon nitride film may be formed by any method. For example, a low pressure CVD method using monosilane and ammonia or dichlorosilane (SiH ₂ Cl ₂ ) and ammonia, a plasma CVD method using monosilane and ammonia or monosilane and nitrogen, and the like.

7) The silicon oxide film 21 is formed not by the low pressure CVD method using monosilane but by another method. For example, a normal pressure CVD method using monosilane and oxygen, a plasma CVD method using monosilane and nitrous oxide or a monosilane and oxygen, and a low pressure CVD method using monosilane to first form polysilicon and then thermally oxidize the polysilicon. , A CVD method using TEOS (tetraethoxysilane; Si (OC ₂ H ₅ ) ₄ ), and the like.

In the CVD method using TEOS, an LP-TEOS oxide film formed by a low pressure CVD method and a plasma TEOS oxide film formed by a plasma CVD method (hereinafter referred to as NP).
It is possible to form an atmospheric pressure TEOS oxide film (hereinafter referred to as AP). In this, AP is
Since it has excellent flatness, it is widely used as an Al-Al interlayer insulating film. It has been reported that the film forming characteristics of the AP show a dependency on the underlying pattern, but a sufficient elucidation of the generation mechanism thereof has not yet been achieved.

Therefore, the present inventor examined the generation mechanism of the background pattern dependence exhibited by the AP. First, FIG.
As shown in, a single crystal silicon substrate (Si-Sub) 5
1. LP-TEOS oxide film 52, line and
Aluminum wiring 53 (thickness: 700 nm) with a space (L / S) of 0 to 10 μm, PE54 (thickness: 200 nm)
Are sequentially formed to prepare a sample having a PE / aluminum wiring step structure. The PE 54 was formed under the following conditions: deposition temperature: 390 °
C, RF output: 500 W, TEOS flow rate: 510 cc, oxygen flow rate: 600 cc, pressure: 9 torr. Further, titanium nitride (Ti) as a barrier metal is formed on the aluminum wiring 53.
N) layer (film thickness; 20 nm) is formed.

Next, AP55 is formed on PE54. The formation conditions of AP55 are as follows: deposition temperature: 400 ° C., ozone concentration: 4.6%, TEOS carrier N ₂ gas flow rate: 3
000 cc, and the deposited film thickness on the flat PE 54 (α portion in FIG. 4) is changed in the range of 140 to 810 nm. Then, the deposited film thickness and flatness of AP55 were evaluated by observation with a scanning electron microscope (SEM).

FIG. 5 shows AP55 and PE in the central portion of each aluminum wiring 53 with respect to the L / S of the aluminum wiring 53.
The total film thickness of 54 (AP55 + PE54) is shown.
Since the AP55 and PE54 cannot be distinguished by SEM observation, the total film thickness of AP55 and PE54 was measured as the oxide film thickness.

According to FIG. 5, wide aluminum wiring 53 (L / L
S; 10 μm) The central oxide film thickness (β in FIG. 4) is flat when the deposited film thickness of AP55 (γ in FIG. 4) on the flat PE 54 (α portion in FIG. 4) is 310 nm or more. Na PE
The thickness is smaller than the oxide film thickness on 54 (total value of * AP / PE in FIG. 5 = δ in FIG. 4). But flat PE5
When the deposited film thickness of AP55 on No. 4 is 140 nm, such a phenomenon is not seen.

As a result of observing the cross-sectional shape of each sample, the end of the wide aluminum wiring 53 (L / S; 10 μm) (η in FIG. 4)
Flow angle in the flat PE 54 (α in FIG. 4).
Part) has a deposited film thickness of AP55 (γ in FIG. 4) of 31
It decreases when it is 0 nm or more. But flat PE5
When the deposited film thickness of AP55 on No. 4 is 140 nm, the flow angle at the end of the wide aluminum wiring 53 is 90 °, and no self-flatness is observed.

From the above, it is considered that the phenomenon that the deposited film thickness of the AP 55 becomes thin at the central portion of the wide aluminum wiring 53 is related to the self-flatness. Therefore, not only the PE / aluminum wiring step structure, but also various step structure samples were prepared and the dependence of the AP on the underlying pattern was examined.

FIG. 6 shows the result when the L / S of the aluminum wiring 53 is increased to 500 μm with the same structure as shown in FIG. FIG. 7 shows the results when a sample was prepared in which trenches were formed on a silicon substrate and AP was directly formed on the trenches.

FIG. 8 shows the results of forming a PE / silicon step structure by forming a trench on a silicon substrate and then forming PE on the trench. FIG. 9 shows the results of forming a PE / polysilicon step structure by sequentially forming an LP-TEOS oxide film, a plurality of polysilicon layers having an L / S of 0 to 500 μm, and PE on a silicon substrate.

As described above, when the underlying wiring material is other than aluminum (silicon or polysilicon), the above-described phenomenon that the deposited film thickness of AP is thin does not occur. FIG. 10 shows the same structure as that shown in FIG.
This is the result when annealing is performed at 450 ° C. after the formation of.

FIG. 11 shows PE54 from the structure shown in FIG.
It is the result when is excluded. FIG. 12 shows the result when the structure is the same as that of FIG. 11 and annealing is performed at 450 ° C. after the aluminum wiring 53 is formed.

[0040]

As described above in detail, according to the present invention, it is possible to prevent the semiconductor wafer from being contaminated by impurities existing in the manufacturing apparatus by a simple method.

[Brief description of drawings]

FIG. 1 is a schematic view showing a cross section of a general vertical electric furnace used for manufacturing a semiconductor device.

FIG. 2 is an enlarged view of a main part of FIG.

FIG. 3 is an enlarged view of a main part of FIG.

FIG. 4 is a cross-sectional view of a substrate for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 5 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 6 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 7 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 8 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 9 is a measurement diagram for explaining the underlying pattern dependence of a normal pressure ozone TEOS oxide film.

FIG. 10 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

FIG. 11 is a measurement diagram for explaining the underlayer pattern dependency of a normal pressure ozone TEOS oxide film.

FIG. 12 is a measurement diagram for explaining the underlying pattern dependence of an atmospheric pressure TEOS oxide film.

[Explanation of symbols]

 10 Vertical Electric Furnace 18 Silicon Wafer 19 Boat 21 Silicon Oxide Film as Coating Film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Saida 2-18, Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Makoto Akizuki 2-18, Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Incorporated (72) Inventor Hiroyuki Aoe 2-18 Keihan Hon-dori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. In a semiconductor device manufacturing process, prior to heat treatment of a semiconductor wafer (18) by a heat treatment device (10, 19), a coating film (21) is formed inside the heat treatment device and deposited inside the heat treatment device. A method of treating a semiconductor device, comprising preventing the semiconductor wafer to be treated from being contaminated by the impurities.