JPH0793972A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize a high-speed semiconductor memory device which can generate the activation timing of a sense amplifier without being affected by an irregularity in a process. CONSTITUTION:When one word line is activated, a voltage VDBL for a dummy bit line DBL which is held at a prescribed potential and a preset reference voltage VBS are compared by a differential-type comparator CMP. When the voltage VDBL becomes the reference voltage VBS or higher, an activation signal SACT is generated, the signal is input to a driver for a sense amplifier S/A, and the sense amplifier is activated.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DRAM (Dynamic Ran)
The present invention relates to a semiconductor memory device such as a dom access memory), and more particularly to a device for determining the activation timing of a sense amplifier that amplifies data read from a memory cell.

[0002]

2. Description of the Related Art Timing for activating a sense amplifier for amplifying data read from a memory cell is set to be several nanoseconds (nsec) later than a signal for activating a cell transistor. The reason for setting such a delay timing is that if the data read from the memory cell is not sufficiently transmitted to the bit line, the data will be destroyed by the noise of the sense amplifier itself.

In this case, the timing at which data is read from the memory cell varies depending on the boost level of the word line, the degree of deterioration of its waveform, and the threshold voltage V _th of the access transistor, so that the sense amplifier is activated. A method of taking a predetermined margin is used for generating the timing. As a concrete method, a method of using a delay from a clock, a method of providing a dummy bit line and monitoring the potential thereof, and the like are adopted.

FIG. 4 is a waveform diagram when the former method is adopted, in which the horizontal axis represents time and the vertical axis represents voltage. In FIG. 4, V _WL is a word line waveform indicating a voltage change on a word line, V _BLa and V _{BL b} are bit line waveforms indicating a voltage change on a bit line, V _tha and V _thb are threshold voltages of cell transistors, CLK _SA indicates the absolute level of the clock signal that activates the sense amplifier. Figure 4
As shown in, the bit line waveforms V _BLa and V _BLb have a level difference (difference) in order to facilitate the sensing in the sense amplifier, but this is caused by the threshold variation of the transistors of the memory cell. The opening timing is different. For example, when the threshold value is V _tha , the broken line V
_The opening timing is as shown by _BLa , and when the threshold value is V _thb , the opening timing is as shown by the solid line V _BLb . Further, the activation timing of the cell transistor is different depending on the proximity of the memory cell to the decoder, and the timing at which the level of the bit line is different is also different. Therefore, in order to prevent malfunction, the timing of outputting the clock signal CLK _SA for activating the sense amplifier is set after the timing at which the opening of the level is the latest.

FIG. 5 is a circuit diagram showing a memory cell array adopting the latter method of providing dummy bit lines, and FIG. 6 is a waveform diagram thereof. In FIG. 5, BL is the bit line, DBL dummy bit lines, WL1 to WL3 are word lines, Q ₁ to Q ₆ are n-channel MOS (Metal Oxide Semic
onductor) transistor, C ₁ and C ₂ are capacitors, and I
NV indicates an inverter, and in FIG.
_DBL shows a dummy bit line waveform showing a voltage change of the dummy bit line DBL.

In the circuit of FIG. 5, the transistor Q₁~ Q₃
Source is the power supply voltage V_CCConnected to, the drain is a dummy
Transistor Q connected to bit line DBL₁The gate of
Is connected to the word line WL1 and the transistor Q₂The game
Connected to the word line WL2, and the transistor Q₃Ge of
Is connected to the word line WL3. Also, Tran
Dista Q_FourSource is grounded and drain is dummy bit
To the chip activation signal T.
_ACT Connected to the input line of. Dummy bit line
One end of DBL is connected to the input of the inverter INV,
The output of the inverter INV is connected to a sense amplifier (not shown).
Has been continued. That is, sense from the inverter INV
Clock signal (activation signal) CLK that activates the amplifier
_SAIs output. Transistor Q_FiveThe drain is a bit
Connected to line BL and the gate connected to word line WL1.
And the source is the capacitor C₁Memory cells connected to
It is configured. Similarly, transistor Q₆Drain of
Is connected to the bit line BL, and the gate is connected to the word line WL3.
Connected, source is capacitor C₂Connected to memory
The cell is configured.

In such a configuration, the dummy bit line
DBL keeps the chip activation signal until the chip is activated.
Issue T _ACT Is high level and transistor Q_FourAt the gate of
The potential of the dummy bit line DBL is supplied to the ground level.
Retained. Here, in order to activate the chip,
Sexualized signal T _ACT Is low level and transistor Q_FourThe
Input to transistor Q_FourIs off
As a result, the dummy bit line DBL floats.
It becomes a state. Here, for example, the word line WL1 is selected
And its potential rises, the transistor Q₁Is active
Is turned on and turned on, and the potential of the dummy bit line DBL
Is V _CCAscend toward the level. And the dummy bit
The line DBL is the threshold voltage V of the inverter INV._thDTo
When it reaches the low level clock signal CLK_SAIs sensea
Is output to the amplifier and the sense amplifier is activated.

[0008]

In the former method, the timing at which the clock signal CLK _SA for activating the sense amplifier is output is set after the timing at which the opening is the slowest. It is necessary to take the timing margin into consideration,
It becomes an obstacle to speeding up.

In the latter method, the dummy bit line D
Since BL is input to the inverter INV which is a logic gate, the output timing of the clock signal is the dummy bit line D
It is determined by the time when the threshold voltage V _{thD of} BL is reached, the output timing of the clock signal fluctuates due to fluctuations in the threshold value, etc., and it is not suitable for speeding up. Also,
Since the potential changes with a gradient similar to that of the bit line, when the threshold voltage shifts to V _thDS as shown in FIG. 6, the timing is greatly affected.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of generating an activation timing of a sense amplifier without being affected by process variations and the like, and achieving high speed. To do.

[0011]

To achieve the above object, a semiconductor memory device in which a sense amplifier for amplifying data read from a memory cell of the present invention is activated at a predetermined timing after activation of a cell transistor. Compares the dummy bit line, which is held at a predetermined potential when one word line is activated, with the potential of the dummy bit line and a preset reference voltage. And an activation signal generation circuit that detects that the sense amplifier is held by and generates an activation signal for activating the sense amplifier.

[0012]

According to the present invention, when one word line is activated, the dummy bit line is held at a predetermined potential. The potential of the dummy bit line is compared with the reference voltage in the activation signal generating circuit. Then, as a result of the comparison, when the potential of the dummy bit line becomes equal to or higher than the reference voltage or equal to or lower than the reference voltage, it is determined that the potential of the dummy bit line is held at a predetermined potential due to activation of the word line, and the activation is performed. The activation signal is generated and output to the drive unit of the sense amplifier, which activates the sense amplifier.

[0013]

1 is a system configuration diagram showing an outline of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a main part of the semiconductor memory device according to the present invention. FIG. The same components are denoted by the same reference numerals. That is, DCD
X decoder, S / A sense amplifier, DRV sense amplifier driver, MCA memory cell array, BL is the bit line, DBL dummy bit lines, WL1 to WL3 are word lines, Q ₁ to Q ₆ are n-channel MOS transistor ,
C ₁ and C ₂ are capacitors, ASG is an activation signal generation circuit, CMP is a comparator forming the activation signal generation circuit ASG, V _BS is a reference voltage, and S _ACT is a sense amplifier activation signal.

The sources of the transistors Q _{1 to} Q ₃ are connected to the power supply voltage V _CC , the drains are connected to the dummy bit line DBL, and the gate of the transistor Q ₁ is the word line WL1.
And the gate of the transistor Q ₂ is connected to the word line WL.
2 and the gate of transistor Q ₃ is word line W
It is connected to L3. The source of the transistor Q ₄ is grounded, the drain is connected to the dummy bit line DBL, and the gate is connected to the input line of the chip activation signal T _ACT .

One end of the dummy bit line DBL has a differential type comparator CMP forming an activation signal generating circuit ASG.
Connected to the inverting input (-) of the comparator CMP, the non-inverting input (+) of the comparator CMP is connected to the input line of the reference voltage V _BS generated by the reference voltage generating circuit (not shown), and the output of the activation signal generating circuit ASG is Sense amplifier driver DR
Connected to V.

The drain of the transistor Q ₅ is the bit line B
A memory cell is formed by being connected to L, the gate being connected to the word line WL1, and the source being connected to the capacitor C ₁ . Similarly, the drain of the transistor Q ₆ is connected to the bit line BL, and the gate is connected to word line WL3, the source memory cell is constituted by connecting the capacitor C _2.

The activation signal generation circuit ASG sets the activation signal S _ACT to a high level and outputs it to the sense amplifier driver DRV when the potential of the dummy bit line DBL becomes equal to or higher than the reference voltage V _BS . The sense amplifier driver DRV activates the sense amplifier S / A when the activation signal S _ACT is input at a high level.

Next, the activation signal generating circuit ASG is used.
Reference voltage V_BSThe setting standard of is explained using Fig. 3.
Reveal In FIG. 3, the horizontal axis represents time and the vertical axis represents voltage.
They are shown respectively, and V in the figure _DBL1Is a dummy bit line D
Dummy bit line waveform showing the voltage change of BL, V_BLIs bit
7 shows a bit line waveform indicating a voltage change of the output line. Well
V_DBL2Is the length of the dummy bit line DBL is V_DBL1Place
Dummy bit showing voltage change when set to 1/2 of
Shows a line waveform, V_DBL4Is the length of the dummy bit line DBL
V_DBL1Of the voltage change when set to 1/4 of
The mebit line waveform is shown.

As shown in FIG. 3, when setting the reference voltage to the V _BS1, the voltage V _BS1 and the dummy bit line waveform V _DBL1
The time t _x1 corresponding to the intersection x ₁ with the sense amplifier S / A
Drive timing. For example, if the reference voltage is V _BS1
From V _{BS2 to} V _BS3 , the intersection x of the voltages V _BS2 , V _BS3 and the dummy bit line waveform V _DBL1
The times t _x2 and t _x3 corresponding to ₂ and x ₃ are the sense amplifier S /
It becomes the drive timing of A. In this way, since the reference voltage can be set over a wide range, unlike the case of the logic gate, the drive timing of the sense amplifier can be arbitrarily set, and the timing can be increased.

Further, the length of the dummy bit line DBL is 1 /
By shortening to 2 or 1/4, the slope becomes large like the dummy bit line waveforms V _BL2 and V _BL4 , and the driving timing becomes short to t _y1 and t _z1 even with the same reference voltage V _BS1 . It will be faster. Note that, for example, even if the reference voltage changes between V _BS1 and V _BS4 , when the length of the dummy bit line DBL is set to 1/4, the timing shift is about the difference between t _z1 and t _z2. However, in the case of the normal dummy bit line length, the timing shift becomes a difference between t _x1 and t _x4 and becomes large. That is, the dummy bit line DBL
By shortening the length of, the amount of change in timing due to the fluctuation of the reference voltage is reduced and the timing can be speeded up.

Next, the operation of the above configuration will be described. Dummy bit line DBL until the chip is activated, the transistor Q chip enable signal T _{AC T} is at a high level
_It is supplied to the gate of ₄ and the potential of the dummy bit line DBL is held at the ground level. Here, when the chip activation signal T _ACT is input to the base of the transistor Q _{4 at} a low level to activate the chip, the transistor Q ₄ is turned off, and as a result, the dummy bit line DBL is brought into a floating state. .

For example, when word line WL1 is selected by the X address and its potential rises, transistor Q ₁ is activated and turned on, and the potential of dummy bit line DBL rises toward the V _CC level. The voltage V _DBL of the dummy bit line DBL at this time is compared with the reference voltage V _BS in the comparator CMP of the activation signal generation circuit ASG. Then, the voltage V _DBL of the dummy bit line _DBL
Becomes higher than the reference voltage V _BS , the activation signal S _ACT is set to the high level and is output to the sense amplifier driver DRV. In the sense amplifier driver DRV, the sense amplifier S / A is activated in response to the input of the high level activation signal S _ACT . As a result, in the sense amplifier S / A, the data read from the predetermined memory cell of the memory cell array MCA is amplified.

In this case, the variation in the timing of activating the sense amplifier S / A depends on the reference voltage generating circuit (not shown) because the activation signal S _ACT is generated using the reference voltage V _BS .

As described above, according to this embodiment,
It compares the reference voltage V _BS which is previously set to the voltage V _DBL of the dummy bit line DBL, the voltage V _DBL reference voltage V _BS
In the case of the above, the activation signal S _ACT is generated and input to the sense amplifier driver DRV, and the sense amplifier S /
Since A is activated, there is no change in the threshold value that occurs when a logic gate is used as in the conventional case.
The sense amplifier S / A can be driven at stable timing. In addition, since the timing for activating the sense amplifier S / A can be arbitrarily set depending on the level of the voltage used for comparison, there is an advantage that the speed can be increased.

[0025]

As described above, according to the present invention,
There is an advantage that the activation timing of the sense amplifier can be generated without being affected by the process variation and the threshold variation, and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an outline of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a main part of a semiconductor memory device according to the present invention.

FIG. 3 is a diagram for explaining a reference voltage according to the present invention.

FIG. 4 is an explanatory diagram of a conventional method of generating activation timing of a sense amplifier using a delay from a clock.

FIG. 5 is a diagram showing an example of a circuit that adopts a conventional method of providing a dummy bit line and monitoring the potential thereof to generate the activation timing of a sense amplifier.

FIG. 6 is an explanatory diagram of a conventional method of providing a dummy bit line and monitoring its potential to generate activation timing of a sense amplifier.

[Explanation of symbols]

DCD ... X decoder S / A ... sense amplifier DRV ... sense amplifier driver MCA ... memory cell array BL ... bit line DBL ... dummy bit lines WL1 to WL3 ... word line Q ₁ ~Q ₆ ... n-channel MOS transistor C _1, C ₂ ... Capacitor ASG ... Activation signal generation circuit CMP ... Comparator _VBS ... Reference voltage _SACT ... Activation signal

Claims (1)

[Claims] 1. A semiconductor memory device in which a sense amplifier for amplifying data read from a memory cell is activated at a predetermined timing after activation of a cell transistor, and when one word line is activated. The dummy bit line held at a predetermined potential is compared with the potential of the dummy bit line and a preset reference voltage, and it is detected that the potential of the dummy bit line is held at the predetermined potential to detect the sense amplifier. And an activation signal generating circuit for generating an activation signal for activating the semiconductor memory device.