JPH0792970A - Interval variation adding device - Google Patents

Abstract

PURPOSE:To add interval variation to a sound signal of a instrument sound, etc., without cutting off the high frequency range. CONSTITUTION:This device is provided with an interval control circuit 201 which determines the number of delay stages for internal control data. A write address and a read address having an address difference corresponding to the output int(M) of the integer part of the internal control circuit 201 is generated by an address generating circuit 202. According to the addresses, input data are delayed by a data storage circuit 101 and the delayed data are supplied to an all-pass filter 204. Then when the int(M) varies, the transfer data are supplied as delay data which are 0 or 1 clock precedent to the all-pass filter 204 and the interval variation can be added without a noise or variation in frequency characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pitch variation adding device which uses a digital electronic circuit, and in particular adds a variation amount to a pitch by giving a time delay to waveform data.

[0002]

2. Description of the Related Art Heretofore, there has been proposed a device capable of realizing an effect such as vibrato used in an electronic musical instrument or the like by adding a pitch variation to input acoustic signal data. As such a device, a device has been proposed in which the input acoustic signal data is written in a temporary memory or the like and read by a sampling time different from the writing to add a pitch change. However, such a device is difficult to perform time division multiplexing, and the hardware becomes complicated. A method has also been proposed in which the sampling times for writing and reading are made the same, and in particular, in order to realize a continuous and smooth pitch variation, the variation amount of the pitch variation does not always follow the sampling time Ts. There has been proposed a pitch variation adding device capable of realizing pitch variation by changing the phase of the generated acoustic signal data. Hereinafter, such a device will be described with reference to the drawings.

FIG. 10 is a block diagram of a conventional pitch variation adding device. In FIG. 10, a data storage circuit 101 is a storage circuit that writes the value of the input waveform data to the address indicated by the write address, reads the data at the address indicated by the read address, and outputs it as delay data. It is provided to the circuit 102. The interpolation calculation circuit 102 delays the delay data output from the data storage circuit 101 for a predetermined time and then outputs the delayed data as output data. The pitch control data K, which is a ratio indicating how much the sound of the input waveform data is changed, is input to the delay control circuit 103. Based on this pitch control data K, the delay control circuit 103 uses the data storage circuit 101.
Int (M) for determining the delay time DM of the interpolating circuit 102 and at the same time generating frac (M) for determining the delay time DA of the interpolation calculation circuit 102, where int (M) is the address generating circuit. It is input to 104. Where int (M) is the number of delay stages M
, And frac (M) represent the fractional part of the number of delay stages M. The address generation circuit 104 resets the write address to the value 0 when the processing start flag is input, and the difference between the write address and the read address is delayed by the delay control circuit 10.
This is an address generation circuit that sets the read address so that it becomes the value int (M) determined in 3, and then increments the write address and the read address at the generation timing of the system clock ψ.

The relationship between the frequency f ₀ of the input waveform data, the frequency f ₁ of the output waveform data, and the pitch control data K is shown in the following equation (1). K = f ₁ / f ₀ = 1−ΔM (1) where ΔM is the variation amount of the delay stage number. The number of delay stages M and the delay time D are expressed by the following equation (2). Note that Ts is the cycle of the system clock ψ. D = M × Ts (2) The relationship between int (M) and the delay time DM of the data storage circuit 101 is expressed by the following equation (3). DM = int (M) × Ts (3) The relationship between frac (M) and the delay time DA of the interpolation calculation circuit 102 is expressed by the following equation (4). DA = frac (M) × Ts (4)

Next, the detailed configuration of each block will be described. FIG. 11 is a block diagram of the interpolation calculation circuit 102. The register 11 is a register for holding the delay data stored in the address immediately before the address indicated by the read address in the data storage circuit 101, and the register 12 is a register for holding the delay data stored in the address indicated by the read address. Is. The subtractor 13 is a subtractor that subtracts the fractional part frac (M) generated from the delay control circuit 103 from the value 1. The multiplier 14 is a multiplier that multiplies the fractional part frac (M) generated from the delay control circuit 103 and the delay data held in the register 11. The multiplier 15 is the subtractor 1
3 is a multiplier that multiplies the subtraction data (1-frac (M)) output from 3 and the delay data held in the register 12, and the adder 16 calculates the multiplication result output from the multipliers 14 and 15. This is an adder that adds and outputs the output data.

FIG. 12 is a block diagram of the address generation circuit 104. In the figure, the address generation circuit 104 is reset by the processing start flag, and the system clock ψ
Has a counter 21 that is incremented according to the generation timing of, and the count value of this counter is input to the data storage circuit 101 as a write address. The subtractor 22 is a subtractor that subtracts the value of the integer part int (M) output from the delay control circuit 103 from MAXadr, which is the entire word length of the address of the data storage circuit 101, and the output thereof is sent to the adder 23. Given. The adder 23 is an adder that adds the write address counted by the counter 21 and the subtracted data of the subtractor 22. The output of the adder 23 serves as the read address Radr ₀ and is also provided to the adder 24. The adder 24 adds a value (−) to the addition data output from the adder 23.
1) is added, and the read address R of the data storage circuit 101 is added.
It is an adder that outputs as adr _-1 .

FIG. 13 is a block diagram of the delay control circuit 103. In the figure, the pitch control data K is first input to the first converter 31. The conversion unit 31 uses the following formula ΔM = 1-K obtained by modifying the formula (1) to calculate an integer part that is the number of delay stages of the data storage circuit 101.
int (M) and the fractional part fr which is the number of delay stages of the interpolation calculation circuit 102
This is a conversion unit for obtaining the variation amount ΔM of M, which is the sum of the number of delay stages of ac (M), and the output thereof is given to the adder 34. Further, the selector 32 selects a value of 1/2 of MAXadr, which is the entire word length of the address of the data storage circuit 101, at the time of initialization,
At other times, it is a selector that selects the output of the adder 34, and its output is given to the register 33. The register 33 is a register that holds the data output from the selector 32, and its output is input to the adder 34. The adder 34 is an adder that determines the delay stage number M by adding the data held in the register 33 and the variation amount ΔM output from the conversion unit 31. By the operation of the selector 32, the adder 34 performs either operation of the following equations (5) and (6). M = ΔM + MAX adr / 2 (5) M ← ΔM + M (6)

FIG. 14 shows the variation ΔM from the value 0 to (−0.03).
It is an explanatory view of the operation when changed to. FIG. 15 is an operation explanatory diagram when the variation amount ΔM is changed from the value 0 to 0.03. FIG. 16 is a time waveform chart of the input waveform data and the output waveform data when the variation amount ΔM is changed from the value 0 to (−0.03). FIG. 17 is a time waveform chart of the input waveform data and the output waveform data when the variation amount ΔM is changed from 0 to 0.03. 16 and 17, the input waveform data has a peak value of ± 10000 and one cycle of 480 points (the pitch is 100 when the sampling frequency Fs is 48.0 kHz).
Hz) sine wave. Further, in FIGS. 14 and 15, the double circles conceptually show the storage area of the data storage circuit 101 which is cyclically configured, and the decimal points of the stored contents are omitted.

The operation of the conventional pitch variation adding device configured as described above will be described. When the pitch control data K is designated, in the delay control circuit 103, the conversion unit 31 converts the pitch control data K into the variation amount ΔM. Furthermore, at the time of initial input of the input waveform data (ie,
Selector 3 when the processing start flag is instructed)
In 2, the half value of the entire word length MAXadr of the data storage circuit 101 is selected, and thereafter, the delay stage number M is selected. The register 33 holds the data selected by the selector 32, and the adder 34 adds the data held in the register 33 and the variation amount ΔM output from the conversion unit 31 to calculate the delay stage number M, Output the integer part of M as int (M) and the decimal part as frac (M).

The address generation circuit 104 resets the write address, which is the count value of the counter 21, to the value 0 at the time when the processing start flag is instructed, and increments the address every sampling cycle Ts while incrementing the address. It is output as the write address Wadr. The subtracter 22 adds the result obtained by subtracting the integer part int (M) from MAXadr, which is the entire word length of the data storage circuit 101, and the write address, and the adder 24 adds the value (-1). Are output as read addresses Radr ₀ and Radr _-1 . The integer part int (M) corresponds to the word length width in which the write address precedes the read address Radr ₀ .
As a result, the number of delay stages of the data storage circuit 101 is obtained. or,
The fractional part frac (M) is the number of delay stages of the interpolation calculation circuit 102.

In the data storage circuit 101, when the processing start flag is instructed, first, all the values stored in the data storage circuit 101 are reset to the value 0, and the input waveform data is set to the write address indicated by the address generation circuit 104. W
The data stored in the address indicated by the read address Radr ₀ (hereinafter referred to as X ₀ ) and the value indicated by the read address Radr _-1 (hereinafter referred to as X _-1 ) are read out. The delay data is output to the interpolation calculation circuit 102.

In the interpolation calculation circuit 102, the delay data X _-1 is held in the register 11 and the delay data X ₀ is held in the register 12. The multiplier 14 multiplies the data X ₋₁ held in the register 11 by the fractional part frac (M). The multiplier 15 multiplies the data X ₀ held in the register 12 by the subtraction result (1-frac (M)) of the subtractor 13 and outputs the result. The adder 15 adds the multiplication results output from the multipliers 14 and 15 and outputs the result as output waveform data.

Among the above operations, the operations of the data storage circuit 101 and the interpolation calculation circuit 102 will be described in detail with reference to actual input waveform data (see FIGS. 16A and 17A). Here, the data storage circuit 10
The maximum word length MAXadr of 1 is 2048, and the variation Δ
A case in which M is changed from the value 0 to (−0.03) will be described. However, in order to simplify the description, 1025 from the processing start time.
With respect to the Ts sampling (1025 Ts), the operation when the variation amount ΔM is set to 0 and then the pitch is raised with the variation amount ΔM being a value (−0.03) will be described with reference to FIG. 14 and Table 1.

First, as shown in FIG. 14, when the pitch control data K is designated, all the stored values in the data storage circuit 101 are reset, and the value 0 of the input waveform data is written at the address indicated by the write address. X ₀ (that is, the value 0) stored at the address indicated by the read address Radr ₀ , and Radr ₋₁
X _-1 (that is, the value 0) stored in the address indicated by is read and output. In the interpolation calculation circuit 102, the register 11
Holds X _-1 (value 0). The multiplier 14 multiplies X ₋₁ by the fractional part frac (M). X in register 12
₀ (i.e., the value 0) holds, multiplied with X ₀ at the multiplier 15, subtractor 13 fractional part 1 at frac (M) and result of subtracting the (value 1). The adder 16 adds the multiplication result (value 0) output from the multiplier 14 and the multiplication result (value 0) output from the multiplier 15, and outputs a value 0 as output waveform data.
Is output. Then, the value of the write address is incremented by 1. After that, since the variation ΔM has a value of 0 for the time of 1024 Ts, the value 0 is output as the output waveform data by repeating the same operation.

[Table 1]

Next, the operation after 1024 Ts has elapsed will be described with reference to FIG. Time 1024
In ts, the above operation as well as variation ΔM is equal to 0, the value X ₀ of RADR ₀ points to (value 0), the value X _-1 (value 0) that RADR _-1 is pointed read rare output waveform data Is output and is incremented by one sampling time. At time 1025Ts, the fluctuation amount ΔM becomes a value (−0.03), and the sum M of the delay stages becomes a value 1023.97.
Since t (M) changes from the value 1024 to the value 1023 and the output of the subtractor 22 changes from 1024 to 1025, the Radr _{0 of} (c) in FIG. 14B is the value incremented by two stages. Become. The fractional part frac (M) has a value of 0.97, and the interpolation calculation as shown in FIG.
4.82 is output. By performing such operation for 2048 Ts time, output waveform data as shown in FIG. 16B is obtained. Compared with the cycle of the input waveform data, the cycle of the output waveform data is slightly shorter and the pitch is higher.

Next, with reference to FIG. 15 and Table 2, the operation when the variation amount ΔM is set to 0.03 after the 1025 Ts sampling time is set to 0, that is, the pitch is lowered will be described.
FIG. 15A shows the operation from time 0 to time 1023Ts,
FIG. 15B shows the operation at time 1024Ts. Since these operations are similar to the above-described operations for raising the pitch, the description thereof will be omitted and the operation at time 1025Ts will be described with reference to FIG.
This will be described with reference to (c) and Table 2.

[Table 2]

At the time of 1025 Ts, the variation amount ΔM is switched from the value 0 to the value 0.03. The value X indicated by Radr _0
0 (value 130.89) and the value X _-1 (value 0) indicated by Radr _-1
Is read and 126.96 is output as output waveform data. By executing such operation for 2048 Ts time, output waveform data as shown in FIG. 17B is obtained. Compared with the cycle of the input waveform data, the cycle of the output waveform data is slightly longer and the pitch is lowered.

[0018]

However, the above configuration has a problem that the high frequency components are mainly cut off from the input waveform data. For example, the variation Δ
When M is a value (0.5), the interpolation calculation circuit 102 executes the calculation of the following expression (7).

[Equation 2] In Expression (7), H (z) is generally called a first-order FIR filter, and acts as a filter that blocks high-frequency components with respect to the input X ₀ . When the variation ΔM takes a value other than 0, the interpolation calculation circuit 102 acts as a filter that passes only the low frequency component. Therefore, the conventional pitch variation adding device has a problem that the tone color changes because the high frequency component is cut off from the input waveform data. When the phase of the input waveform data is controlled only by the data storage circuit 101 without using the interpolation calculation circuit 102,
In particular, when the sampling frequency is lowered to operate the memory for reducing the memory capacity of the data storage circuit 101, there is a problem that the pitch variation becomes coarse.

The present invention has been made in order to solve such a conventional problem, and is a pitch variation adding device capable of smoothly changing the pitch without interrupting the high frequency component of the input waveform data. The purpose is to realize.

[0020]

According to a first aspect of the present invention, there is provided data storage means for delaying input waveform data for a predetermined time and outputting it as first delay data and second delay data of an address immediately before it. The delay control means using the integer part of the delay stage number M calculated based on the pitch control data as the delay time of the data storage means, and the first stored in the data storage means when the value of the integer part of the delay stage number is decreased by the delay control means. Two
Of the delay data, the transfer data generating means which uses the value 0 as the transfer data when the value of the integer part of the number of delay stages by the delay control means, and the first delay data of the data storing means if there is no transfer data from the transfer data generating means. If there is transfer data from the transfer data generating means, the transfer data is delayed by a time corresponding to the fractional part of the delay stage number M output from the delay control means, and is output as output waveform data. It is characterized by that.

According to a second aspect of the present invention, the write address and the first read address having an address difference corresponding to the integer part of the delay stage number M output from the delay control means, and the read address immediately preceding the read address. 2 read addresses and
And address generating means for outputting to the data storage means.

In the invention of claim 3 of the present application, the delay control means receives the voice control data K defined as the frequency ratio of the input / output waveform data, and changes in the voice control data K from 1 are changed in the number of delay stages. A new conversion stage number M is obtained by adding a first conversion unit that converts the amount ΔM and an initial value at the time of initial operation, and the delay stage number M immediately before that to the fluctuation amount ΔM output from the first conversion unit. Output first adder and fractional part of delay stage number M output from the first adder
a second conversion unit for converting frac (M) into a filter coefficient C according to equation (8), and the address generation means is the number of delay stages output from the maximum address of the data storage circuit by the delay control means. A subtracter that subtracts the integer part int (M) of M, a counter that is incremented by the system clock and uses the count value as a write address, and the output of the subtractor is added to the count value of the counter to obtain a first read address. And a third adder that adds -1 to the read address obtained from the second adder to make the address immediately before the first read address the second read address. The transfer data generating means includes a second data storage means read by the second read address when the value of the integer part of the delay stage number M obtained from the delay control means decreases. The delay data is selected, and when it increases, the value 0 is selected and output as transfer data. The all-pass filter is input from the transfer data generating circuit to the first input terminal every time the number of delay stages changes. A selector for selecting the transfer data and selecting the data input to the second input terminal when there is no change, a delay device for delaying the output of the selector by one system clock, and a first read address from the data storage means. A first multiplier that multiplies the first delay data read from the filter coefficient C obtained from the delay control means, and a fourth multiplier that adds the outputs of the delay device and the first multiplier as output data. An adder, and a second multiplying the output of the fourth adder and the sign inversion value -C of the filter coefficient
And a fifth adder for adding the output of the second multiplier and the first delay data read from the first read address of the data storage means and giving it to the selector as the second input. It is characterized by having.

[0023]

According to the present invention having such characteristics, the delay control means calculates the delay stage number M based on the pitch control data K, and the integer part thereof is used as the delay time of the data storage means. The data storage means outputs the first delay data obtained by delaying the input waveform data by this delay time and the second delay data of the address immediately before that. If the integer part of the number of delay stages by the delay control means does not decrease, the first delay data is used as the input of the all-pass filter, and if the value of the integer part of the delay stage decreases, the second delay data, the integer part of the delay stage number. If the value increases, the value 0 is output from the transfer data generating means to the all-pass filter as transfer data. The all-pass filter delays one of these inputs by a time corresponding to the fractional part of the delay stage number M output from the delay control means, and outputs it as output waveform data. With such a configuration, the all-pass filter controls only the phase characteristic, that is, the delay time without changing the amplitude characteristic of the delay data. This makes it possible to add a smooth pitch change to the input waveform data without blocking high frequency components. When the all-pass filter is used without using the transfer data generating means, noise occurs in the output waveform data when the integer part of the number of delay stages changes. In order to prevent this noise, the transfer data generating means removes the noise from the output waveform data by transferring the delay data to the delay device in the all-pass filter or resetting it to the value 0.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the pitch variation adding apparatus according to this embodiment. In FIG. 1, the delay control circuit 201 is supplied with pitch control data K, calculates the delay stage number M and outputs the integer part int (M), and generates a filter coefficient C determined by the decimal part frac (M). It is what makes me. The address generation circuit 202 generates a write address Wadr and read addresses Radr, Radr _-1 according to the input of the integer part int (M). These addresses are input to the data storage circuit 101. The data storage circuit 101 has a write address Wad as in the conventional example.
Write the input waveform data to the address determined by r,
Read address RADR, is to the data is read out and the delay data D _1, D ₂ from RADR _-1. The integer part int (M) of the delay control circuit 201 is the transfer data generation circuit 203.
Given to. The transfer data generating circuit 203 outputs transfer data and a transfer instruction flag to control the operation of the all-pass filter 204.

Next, the detailed structure of each block will be described with reference to FIGS. In the following blocks, the same parts as those in the conventional example described above are designated by the same reference numerals, and detailed description thereof will be omitted. The delay control circuit 201 in this embodiment has a first conversion unit 31, a selector 32, a register 33, and a first adder 34, as shown in FIG. 2, similarly to the conventional example and the delay control circuit 103. , The integer part of the number of delay stages M in
t (M) and the fractional part frac (M) are output. The delay control circuit 201 according to this embodiment has the second conversion unit 35 to which the decimal fraction frac (M) is input. The conversion unit 35 is a conversion unit that converts into the filter coefficient C of the all-pass filter 204 by the equation (8), and the filter coefficient C is given to the all-pass filter 204.

Next, the address generation circuit 202 is the same as the address generation circuit of the conventional example, and the counter 21 and the subtractor 2 are used.
2, the second adder 23, and the third adder 24. This write address Wadr and read address R
adr and Radr _-1 are input to the data storage circuit 101, and the input waveform data is written at this write address. The delay data D ₁ read from the read address Radr is input to the all-pass filter 03, and the delay data D ₂ read from the read address Radr ₋₁ is input to the transfer data generating circuit 203.

Next, as shown in FIG. 3, in the transfer data generating circuit 203, the integer part int (M) is input to the delay device 41. The delay unit 41 is an integer part int output from the delay control circuit 201.
The delay unit delays (M) by a time corresponding to one system clock ψ, that is, one sampling time Ts, and its output is given to the subtractor 42. The subtractor 42 calculates the delay unit 41 from the integer part int (M) output from the delay control circuit 201.
Of the comparator 4 and the output of the comparator 4
3 is applied to the input terminal A. Numerical values of 1.0 are input to the input terminal B and -1.0 to the input terminal C of the comparator 43.
If the numerical values at the input terminals A to C are denoted by A, B, and C, respectively, the comparator 43 compares the values at A, B, and C. When A ≧ B or A ≦ C, the selector 4
4 outputs selection signals SA and SB for selecting inputs A and B, respectively. A value of 0.0 is input to the input terminal A of the selector 44, and the delay data D ₂ read from the data storage circuit 101 is input to the input terminal B. One of them is selected based on the selection signal and is output as transfer data. . Further, these comparison outputs are given to the OR circuit 45. The OR circuit 45 uses the logical sum as a transfer instruction flag and the all-pass filter 20.
4 to the selector 51.

On the other hand, in the all-pass filter 204, as shown in FIG. 3, the transfer data selected by the selector 44 is input to the input terminal A, and the addition data from the adder 56 described later is input to the input terminal B. The selector 51 selects the transfer data of the input A when the transfer instruction flag is H level, and selects the output of the adder 56 when the transfer instruction flag is L level. The output of the selector 51 is input to the delay device 52. The delay device 52 is a delay device that delays the data selected by the selector 51 by a time corresponding to one system clock ψ, that is, one sampling time Ts, and its output is input to the fourth adder 54. The multiplier 53 is a multiplier for multiplying the filter coefficient C and the delay data D _1, and the output thereof is input to the adder 54. The adder 54 adds the data output from the delay unit 52 and the multiplication result output from the multiplier 53, outputs the addition result as output waveform data, and inputs it to the multiplier 55. The multiplier 55 is a multiplier that multiplies the output waveform data and the inverted value (−C) of the filter coefficient C, and the output thereof is input to the adder 56. The fifth adder 56 outputs the delay data D
_{1 and} this multiplication result are added and output to the input terminal B of the selector 51.

Next, the operation of this embodiment will be described. FIG. 4 is an operation explanatory diagram when the variation amount ΔM is changed from the value 0 to (−0.03). FIG. 5 shows the variation amount ΔM from the value 0 to 0.03.
It is an explanatory view of the operation when changed to. FIG. 6 shows a transfer data generating circuit 2 in the pitch variation adding apparatus of this embodiment.
FIG. 13 is a time waveform chart of the input waveform data and the output waveform data when 03 is removed and the variation amount ΔM is changed from the value 0 to (−0.03). FIG. 7 shows that in the pitch variation adding apparatus of this embodiment, the transfer data generating circuit 203 is removed and the variation amount Δ
FIG. 9 is a time waveform chart of input waveform data and output waveform data when M is changed from 0 to a value of 0.03. FIG. 8 is a time waveform chart of the input waveform data and the output waveform data when the variation amount ΔM is changed from the value 0 to (−0.03) in the pitch variation adding device of the present embodiment. FIG. 9 is a time waveform chart of the input waveform data and the output waveform data when the variation amount ΔM is changed from the value 0 to 0.03 in the pitch variation adding device of the present embodiment.

The operation of the pitch variation adding device configured as described above will be described. Since the basic operation is the same as that of the conventional pitch variation adding device, only the differences will be described. The difference is that the all-pass filter 204 is used as a circuit that delays the fractional part frac (M) stages of the number of delay stages M, so that the entire input waveform data is passed. However, when the all-pass filter 204 is used,
When M, which is the sum of the number of delay stages, is changed, noise occurs in the output waveform data when the integer part int (M) is switched. This noise is noise that is intermittently generated in FIGS. 6B and 7B. It is understood that the transfer data generating circuit 203 prevents this noise, and as shown in FIGS. 8 and 9, the noise is removed at the time of switching the integer part int (M).

The noise prevention operation will be described below by actually using the input waveform data (see FIGS. 6A and 7A). The data storage circuit 101 is similar to the conventional example.
The case where the total word length MAXadr is changed to a value of 2048 and the variation ΔM is changed from a value of 0 to (-0.03) will be described. To simplify the explanation, 1025 sampling time (1025Ts) from the processing start time is explained. The value of the fluctuation amount ΔM is 0
Then, the case where the variation amount ΔM is set to a value (−0.03) will be described.

First, the case of increasing the pitch will be described. If the transfer data generating circuit 203 is not provided, the process shown in FIG.
The operations of (a), (b) and (c) are performed, and values of various data are shown in Table 3.

[Table 3] When the pitch control data K is designated, the data storage circuit 101
The stored values of are all reset to the value 0, and the value 0 of the input waveform data is written to the address indicated by the write address.
The delay data (value 0) stored at the address indicated by the read address is multiplied by the filter coefficient C (value 1) in the multiplier 54 of the all-pass filter 204, and the multiplication result (value 0) is stored in the delay device 52. The data (value 0) is added by the adder 54 and output as output waveform data. The result (value 0) obtained by multiplying the sign inversion value (value (−1)) of the filter coefficient C in the multiplier 55 is added to the delay data value 0 in the adder 56 and added to the delay device 52. The result (value 0) is substituted, and the value of the write address is incremented by 1 (see FIG. 4A, Table 3). In this way, FIG.
By performing the operation shown in FIG.
An output waveform data value as shown in is obtained. However, when the integer part int (M) is switched from the value 1024 to the value 1023, that is, at time 1025Ts in Table 3, the value of the output waveform data in FIG. 4 (c) is 3.99, which is the expected value 13
It deviates greatly from 4.82.

The expected value in the right column of Table 3 is obtained by calculating the amplitude value of input waveform data which is a sine wave having a peak amplitude value of ± 10000 and one period of 480 points. For example, expected value 134.82 at time 1025Ts
Corresponds to the amplitude value at the 1.03th point. The expected values in Tables 4 to 6 described later were also obtained in the same manner.

In the present embodiment, in order to prevent noise generated when the integer part int (M) is switched, the transfer data generating circuit 203 of FIG. 3 uses the all-pass filter delay device 52 of FIG.
The delay data D ₂ (value 130.89) is transferred as the transfer data. This operation will be described with reference to FIGS. 3, 4D and Table 4.

[Table 4] In Table 4, the integer point int (M) is switched at time 1024T.
It is a time point when the time is switched from s to 1025 Ts. At this time,
The delay unit 41 of FIG. 3 stores the value 1024 of the integer part int (M) at time 1024 Ts, and the newly input integer part
Subtraction with the value 1023 of int (M) is executed in the subtractor 42. In this case, the subtraction result of the subtractor 42 becomes the value (−1), and the A input and the C input of the comparator 43 match. Therefore, the comparison flag (A ≦ C) of the comparator 43 becomes active, and the selector 44 selects the B input (delay data D ₂ ). At this time, the integer part int (M) becomes 1023, so 1025T
In s, Radr is 1 from 1024Ts as shown in FIG.
Address-separated data, that is, 261.76 is read. At the same time, Radr _-1 reads the data at the address one less than that address, that is, the value 130.89. Therefore, this delay data (value 130.89) is selected by the selector 44 and output as transfer data. Further, the OR gate 45 generates a transfer instruction flag according to the comparison flag (A ≦ C). In FIG. 3, the transfer instruction flag is input to the selector 51 to select the A input. Since the delay data (value 130.89) is input to the A input as transfer data, the value 130.89 is temporarily stored in the delay unit 52. Then, the filter processing as shown in FIG. 4D is performed, the value 134.82 is output as the output waveform data, and a new data value (259.71) is stored in the delay device 52. By this operation, as shown in (Table 4), the value of the output waveform data at time 1025Ts becomes the same data value as its expected value, and as a result, noise is prevented.

Next, the case of lowering the pitch will be described with reference to FIG. 5 and Tables 5 and 6. As in the case of raising the pitch, MAXad which is the entire word length of the data storage circuit 101.
The case where the value of r is changed to 2048 and the fluctuation amount ΔM is changed from the value 0 to 0.03 will be described. However, in order to simplify the explanation, the value of the fluctuation amount ΔM from the processing start time to 1025 sampling time (1025Ts). The operation in the case where the variation amount ΔM is set to the value 0.03 after setting 0 is described.

First, when the transfer data generating circuit 202 is not provided, the operation shown in FIGS. 5A, 5B and 5C is performed, and various data values are shown in Table 5.

[Table 5] When the pitch control data K is designated, the data storage circuit 101
All the stored values of are reset, the value 0 of the input waveform data is written to the address indicated by the write address, and the delay data (value 0) stored at the address indicated by the read address.
Is multiplied by the filter coefficient C (value 1) in the multiplier 53 of the all-pass filter 204, and the multiplication result (value 0) is added to the delay unit 5
The data (value 0) stored in 2 is added by the adder 54 and output as output waveform data. Further, the result (value 0) obtained by multiplying the sign inversion value (−1) of the filter coefficient C by the multiplier 55 is added to the delay data (value 0) by the adder 56, and the addition result ( The value 0) is substituted, and the value of the write address is incremented by 1 (see FIG. 5).
(A), see Table 5). By thus performing the operation as shown in FIG. 5B, output waveform data values as shown in Table 5 are obtained. However, the integer part int (M) is a value
At the time of switching from 1057 to the value 1058, that is, Table 5
At time 1058Ts, the value of the output waveform data deviates greatly from the expected value 4184.20.
(The value is 8188.86) (see FIG. 5 (c)).

As described above, in order to prevent noise generated when the integer part int (M) is switched, the transfer data generating circuit 203 of FIG. 3 sets the data stored in the delay unit 52 of the all-pass filter 204 to a value. Reset to 0. That is, the transfer data having the value 0 is transferred. This operation will be described with reference to FIGS. 3 and 5D and Table 6.

[Table 6] In Table 6, the integer part int (M) is switched at time 1057T.
It is the time when the time changes from 10s to 1058Ts. At this time, the delay unit 41 in FIG. 3 stores the value 1024 of the integer part int (M) at time 1057 Ts, and the newly input integer part
Subtraction with the value 1025 of int (M) is performed in the subtractor 42. In this case, the subtraction result of the subtractor 42 has a value of 1, and the A input and the B input of the comparator 43 match. Therefore, the comparison flag (A ≧ B) of the comparator 43 becomes active,
The selector 44 selects the A input (value 0), and the value 0 is output as the transfer data. Further, in the OR gate 45,
A transfer instruction flag is generated according to the comparison flag (A ≧ B). In FIG. 3, the transfer instruction flag is input to the selector 51 to select the A input. Since the value 0 is input as the transfer data to the A input, the value 0 is temporarily stored in the delay device 52. Then, the filter processing as shown in FIG. 5D is performed, the value 4019.04 is output as the output waveform data, and a new data value 32 is output to the delay unit 52.
1.92 is stored. By this operation, as shown in Table 6, the value of the output waveform data at time 1058Ts becomes almost the same as its expected value, and as a result, noise is prevented.

As described above, according to the present embodiment, the delay device is divided into the data storage circuit 101 and the delay device 52 of the all-pass filter 204 to cope with the pitch change (the switching point of the integer part int (M)). Then, the data transfer circuit 203 transfers the data in the data storage circuit 101 to the delay unit 5 in the all-pass filter 204.
Transferred to 2 or reset to 0. Therefore, it is possible to add variation to the pitch of the input waveform data without interrupting high frequency components with a simple circuit configuration without generating unnecessary noise.

In this embodiment, the bilinear first-order all-pass filter is used, but the same effect can be obtained by using a second-order, third-order, or other high-order all-pass filter. However, when a high-order all-pass filter is used, it is necessary to transfer the delay data by the number of delay devices in the filter or reset the value to zero.

[0040]

As described above, according to the first to third aspects of the present invention, when the input waveform data is designated, the delay time of the data storage means and the all-pass filter is determined, and the data transfer means determines the delay time. Depending on the pitch, the delay device data in the all-pass filter is transferred, or the value is reset to zero. Therefore, it is possible to add a smooth pitch change to the pitch of the output waveform data without generating unnecessary noise and without blocking the high frequency component. Therefore, even if the sampling frequency is lowered, there is an effect that it is possible to realize pitch change with little change in timbre.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a pitch variation adding device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a delay control circuit, an address generation circuit, and a data storage circuit in this embodiment.

FIG. 3 is a block diagram showing a configuration of a transfer data generation circuit and an all-pass filter according to the present embodiment.

FIG. 4 is an operation explanatory diagram of the present embodiment when the variation amount ΔM is changed from a value 0 to (−0.03), in which (a) is time 0T.
s th operation explanation diagram, (b) operation explanation diagram at time 1024 Ts, (c) operation explanation diagram when there is no transfer data generation circuit at time 1025 Ts, (d) generation of transfer data at time 1025 Ts It is an operation explanatory view when it has a circuit.

5A and 5B are operation explanatory diagrams of the present embodiment when the variation amount ΔM is changed from a value 0 to 0.03. FIG. 5A is an operation explanatory diagram at time 0Ts, and FIG. 5B is an operation explanation at time 1057Ts. Figure,
(C) is an operation explanatory diagram when there is no transfer data generation circuit at time 1058Ts, and (d) is an operation explanatory diagram when the transfer data generation circuit at time 1058Ts is provided.

FIG. 6A is a time waveform diagram of input waveform data,
FIG. 6B is a time waveform chart of output waveform data when the pitch is raised without the transfer data generating circuit of this embodiment.

FIG. 7A is a time waveform diagram of input waveform data,
FIG. 7B is a time waveform chart of output waveform data when the pitch is lowered in the case where the transfer data generating circuit of this embodiment is not provided.

FIG. 8A is a time waveform diagram of input waveform data,
FIG. 6B is a time waveform chart of output waveform data when the pitch of the present embodiment provided with the transfer data generating circuit of the present embodiment is raised.

9A is a time waveform diagram of input waveform data, FIG.
FIG. 6B is a time waveform chart of output waveform data when the pitch of the present embodiment provided with the transfer data generating circuit of the present embodiment is raised.

FIG. 10 is a block diagram of a pitch variation adding device in a conventional example.

FIG. 11 is an interpolation calculation circuit in a conventional example.

FIG. 12 is a diagram of an address generation circuit in a conventional example.

FIG. 13 is a delay control circuit in a conventional example.

FIG. 14 is an operation explanatory diagram of a conventional example when the variation amount ΔM is changed from a value 0 to (−0.03), in which (a) is time 0T.
In the s-th operation explanatory diagram, (b) is an operation explanatory diagram of a time 1024 Ts, and (c) is an operation explanatory diagram of a time 1025 Ts.

FIG. 15 is an operation explanatory diagram of a conventional example when the variation amount ΔM is changed from a value 0 to 0.03, (a) is an operation explanatory diagram at time 0Ts, and (b) is an operation explanation at time 1024Ts. Figure,
(C) is an operation explanatory view at time 1025Ts.

16A is a time waveform diagram of input data, FIG.
FIG. 9B is a time waveform chart of output waveform data when the pitch is raised according to the conventional example.

17A is a time waveform diagram of input waveform data, and FIG. 17B is a time waveform diagram of output waveform data when the pitch is lowered according to the conventional example.

[Explanation of symbols]

 11, 12, 33 Register 13, 22, 42 Subtractor 14, 15, 53, 55 Multiplier 16, 23, 24, 34, 54, 56 Adder 21 Counter 31, 35 Converter 32, 44, 51 Selector 41, 52 delay device 43, 51 comparator 45 OR gate 101 data storage circuit 201 delay control circuit 202 address generation circuit 203 transfer data generation circuit 204 all-pass filter

Front page continuation (72) Inventor Koji Watanabe 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kenji Muraki, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A first delaying input waveform data for a predetermined time.
Data storage means for outputting as the second delay data and the second delay data of the address immediately before the delay data, and a delay control means for setting the integer part of the delay stage number M calculated based on the pitch control data as the delay time of the data storage means. The second delay data stored in the data storage means when the value of the integer part of the number of delay stages is decreased by the delay control means, and the value 0 is transferred data when the value of the integer part of the number of delay steps is increased by the delay control means. Transfer data generating means for transmitting the first delay data of the data storing means if there is no transfer data from the transfer data generating means, and the transfer data if there is transfer data from the transfer data generating means from the delay control means. An all-pass filter that delays the time corresponding to the fractional part of the output delay stage number M and outputs as output waveform data. Pitch fluctuation additional device to. 2. A write address and a first read address having an address difference corresponding to an integer part of the number M of delay stages output from the delay control means, and a second read address immediately preceding the read address. The pitch variation adding device according to claim 1, further comprising: address generating means for generating and outputting to the data storing means. 3. The delay control means receives voice control data K defined as a frequency ratio of input / output waveform data, and converts a change amount of the voice control data K from 1 as a variation amount ΔM of the number of delay stages. The first conversion unit outputs a new delay stage number M by adding an initial value during the initial operation and the delay stage number M immediately before that to the fluctuation amount ΔM output from the first conversion unit. An adder and a fractional part fr of the delay stage number M output from the first adder
Ac (M) is calculated by the following equation [Formula 1] And a second conversion unit for converting into a filter coefficient C by the address generation unit, and the address generation unit outputs an integer part int (int ( A subtractor for subtracting M), a counter incremented by the system clock and having the count value as a write address, and an output of the subtractor for addition to the count value of the counter
Second read address, and a third read address obtained by the second adder by adding -1 to the address immediately before the first read address as the second read address. The transfer data generating means is configured to add the data read by the second read address when the value of the integer part of the delay stage number M obtained by the delay control means decreases. The second delay data of the storage means is selected, and when the second delay data is increased, a value of 0 is selected and output as transfer data. The all-pass filter is provided by the transfer data generating circuit every time the number of delay stages changes. A selector that selects the transfer data input to the first input terminal and selects the data input to the second input terminal when there is no change, and the output of the selector is one system clock. A delay unit for delaying by a minute, a first multiplier for multiplying the first delay data read from the first read address by the data storage unit and a filter coefficient C obtained by the delay control unit, A fourth adder for adding the outputs of the delay device and the first multiplier to obtain output data; an output of the fourth adder and a sign inversion value of the filter coefficient−
A second multiplier for multiplying C, an output of the second multiplier and the first delay data read from the first read address of the data storage means are added, and the second selector is added to the selector. The pitch variation adding device according to claim 2, further comprising a fifth adder provided as an input.