JPH0792769B2 - Logic simulator - Google Patents

Description

The present invention relates to a logic simulator, and more particularly to a logic simulator that performs a functional level logic simulation by hardware.

[Conventional technology]

Conventionally, logic simulators that perform function-level logic simulations are, for example, “Sasaki T etol,“ A Mixed Leve
l Simulator for Large Digital System Logic Verific
ation "17th DA Conf.pp626-633 (1980)", it was realized by software.

[Problems to be Solved by the Invention]

Since the above-described conventional functional level logic simulator is realized by software, the simulation process becomes a sequence process of each functional operator, and it takes a long time to execute, especially the simulation time of a large-scale circuit becomes huge. There is.

The present invention has been made in view of such circumstances,
It is an object of the present invention to provide a logic simulator capable of high-speed processing that can perform a functional level logic simulation with hardware.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, the logic simulator of the present invention has a storage means for storing a description and an execution result of a functional level simulation model, a first register having an output of the storage means as an input, 2 registers, an arithmetic circuit for executing an operation and the like related to a functional operator, and an output of this arithmetic circuit as inputs, each of which is an input of the outputs of the second register, the first register and the storage means, An intermediate register that adds an output to the second register, a stack storage unit that receives the output of the second register and the storage unit as an input, and each unit based on the description related to the simulation model stored in the storage unit. And control means for controlling.

[Action]

In the logic simulator of the present invention, the storage unit holds the description relating to the functional level simulation model, and the control unit controls each unit based on the description, so that the first register inputs the output of the storage unit. ，
The arithmetic circuit inputs the output of the first register, the second register or the storage means to execute the operation related to the functional operator, the intermediate register inputs the output of the arithmetic circuit, the second
The hardware operation is performed such that the register of (1) receives the output of the intermediate register and the stack storage means receives the output of the second register or the storage means and stacks, and as a whole corresponds to the description stored in the storage means. A functional level logic simulation is performed, and the execution result is stored in the storage means.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of a logic simulator of the present invention is a functional level simulation model including functional operators and simulation initial values (initial values of registers, memories, etc., input patterns, etc.). A memory (hereinafter referred to as FMEM) 10 in which the description and the simulation result are stored, and a first register which receives an output of a second register (hereinafter referred to as SDREG) 50 and a stack storage unit (hereinafter referred to as STUCK) 60 (Hereinafter referred to as FTREG) 20 and FMEM1
0, FTREG20 and SDREG50 outputs as input, arithmetic circuit 30 that performs shift processing, mask processing, and arithmetic processing related to functional operators, and an intermediate register (hereinafter referred to as IMREG) 40 that inputs the output of arithmetic circuit 30 , SDREG50 whose input is the output of IMREG40, STUCK60 on which input variables and intermediate states of simulation are stacked, and stack pointer (hereinafter referred to as STRR) 70 which indicates the address of STUCK60,
The control circuit 80 controls each part based on the description of the simulation model stored in the FMEM 10 and in synchronization with the clock. In addition, reference numerals 100 to 800 in the figure
Is a signal line connecting each part.

Referring to FIG. 2, an example of the arithmetic circuit 30 is a high-speed arithmetic unit (hereinafter, referred to as a FOP arithmetic unit) that executes a plurality of arithmetic operations performed by simple logical elements (AND, OR, etc.) at high speed in a data flow manner. ) 31, an arithmetic unit (hereinafter referred to as a 1OP arithmetic unit) 32 that executes an arithmetic operation performed by a multi-input / single-output logic element (multi-input 1-output AND, etc.), and an ordinary arithmetic operation of two different inputs. An arithmetic unit to perform (hereinafter referred to as 2OP arithmetic unit) 33, a shift circuit (hereinafter referred to as an SFT circuit) 34 that shifts to the left and right to extract a data portion required for calculation from a plurality of inputs, and each of the above elements A mask circuit (hereinafter referred to as MSK circuit) 35 that performs mask processing of a specified bit with an output as an input. The output of FTREG20 in Fig. 1 is 2OP by the signal line 300.
The output of SDREG50 is connected to the input of calculator 33 and SFT circuit 34, and the output of SDREG50 is connected to the input of the following FOP calculator 31, 1OP calculator 32 and 2OP calculator 33 by signal line 600, and the output of FMEM10 is 1OP calculation by signal line 100. 32, 2OP calculator 33, the control input of the SFT circuit 34 and the MSK circuit 35, and the input of the SFT circuit 34.

Next, the operation of the logic simulator of the present embodiment configured as described above will be described with some examples.

In Fig. 3 i), ~ is in the simulation model, D = A * B + C (1) where * is a logical AND, and + is a logical OR. Describes the contents of the code stored in FMEM10. The logic simulation related to the function (1) is performed as shown in the time chart of FIG. 4 by the control circuit 80 reading the corresponding codes from the FMEM 10 in order from the number and controlling the respective units. Hereinafter, the operation will be described separately for each cycle of the clock (CLK) in FIG.

1) Clock cycle = 1 From the FMEM10, the variable A is first read and stored in the FTREG20.

2) Clock cycle = 2 This variable A is stored in the IMREG 40 via an appropriate place in the arithmetic circuit 30. At this time, if the variable A has multiple bits,
If you want to execute only a certain bit among them, the SFT circuit 34 in the arithmetic circuit 30 shifts to the left or right to perform bit alignment of the logical operation and then store it in IMREG 40. To be done.

At the same time, the variable B is read from the FMEM10 into the FTREG20.

3) Clock cycle = 3 Next, the variable B of FTREG20 is passed through the arithmetic circuit 30 to IMREG40.
The variable A of IMREG40 is transferred to SDREG50.

4) Clock cycle = 4 Next, the variable A of SDREG50 is transferred to FTREG20 and STUCK60, and the variable B is transferred from IMREG40 to SDREG50. In this state, the variable A is stored in the FTREG 20 and the variable B is stored in the SDREG 50 in a form in which the bits are combined, and the operation of A * B is performed by the 2OP operation unit 33 of the operation circuit 30, for example.

5) Clock cycle = 5 The result of A * B is sent to IMREG40. At the same time, the variable B of SDREG50 is transferred to STUCK60, and the next variable C is FM in FTREG20.
Imported from EM10. At this time, the value of STPR70 is increased.

6) Clock cycle = 6 Next, the data C of FTREG20 is sent to IMREG40 and A * B of IMREG40.
The result of is transferred to SDREG50.

7) Clock cycle = 7 Next, the variable C of IMREG40 is transferred to SDREG50, and the result of A * B of SDREG50 is transferred to FTREG20. At the same time, the result of A * B is STP
Decrease the value of R70 and transfer to STUCK60. At this time, the arithmetic circuit 30 performs the calculation of A * B + C.

8) Clock cycle = 8 Next, the calculation result of A * B + C is transferred to IMREG40, and the variable C of SDREG50 is transferred to STUCK60 after increasing the value of STPR70.

9) Clock cycle = 9 Next, the calculation result of A * B + C of IMREG40 is transferred to SDREG50.

10) Clock cycle = 10 The calculation result of A * B + C of SDREG50 is transferred to STUCK60 after decrementing the value of STPR70, and at the same time transferred to FMEM10, which completes the logic simulation according to the equation (1).

3 to ii) in FIG. 3 is a code stored in advance in the FMEM10 when logically simulating the function related to the arithmetic expression H = A * B + C * D + E * F + G (2) in the simulation model. It explains the contents of. The logic simulation related to the function of (2) is performed by the control circuit 80 by reading the corresponding code from the FMEM 10 in the order from the number and controlling each part, in the same manner as the above-mentioned expression (1).

FIG. 5 i) is a code stored in the FMEM 10 in advance when the above-mentioned arithmetic expression (2) shown in FIG. 3 ii) is logically simulated using the FOP arithmetic unit 31 of the arithmetic circuit 30. The contents of Figure 5 and ii) at that time
The execution example of the calculation performed by the FOP calculator 31 is shown. In this case, the control circuit 80 controls the respective units by reading the corresponding codes from the FMEM 10 in order from the number. As a result, the variables A, B, C, D, E, F, G are first fetched from the FMEM10 and transferred to the SDREG50 via the arithmetic circuit 30 and IMREG40, and the FOP arithmetic unit in the arithmetic circuit 30 of FIG. 31 at A * B, C
* D and E * F calculations are performed simultaneously. The variable G is left as it is. The result is S via IMREG40
Transferred to DREG50, then A * B + C * D + E * F + G
Is performed by the FOP calculator 31. And the result is FMEM10
And the simulation ends.

Comparing the number of instructions in the case of FIG. 5 with that of FIG. 3ii),
In Fig. 3, ii) is 14, whereas in Fig. 5 it is 4, which is about 1 /
It is 3.6. By using the FOP calculator 31 in this manner, it becomes possible to perform a logic simulation at a higher speed. When using the FOP calculator 31, it is necessary to extract the conditions that can be used and optimize them when creating the model. Usually, the logic of the control system has many 1-bit operations, so it is effective to apply to these.

〔The invention's effect〕

As described above, according to the logic simulator of the present invention, since the logic simulation of the function level can be realized by the hardware operation, it becomes possible to execute this kind of logic simulation at high speed. It is very effective to apply the present invention to functional level simulation.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of an arithmetic circuit 30, and FIG. 3 is an arithmetic expression to be a logic simulation object and an FMEM10 when executing the arithmetic expression. FIG. 4 is a diagram for explaining the contents of the code stored in advance in FIG. 4, FIG. 4 is a time chart of FIG. 1 when the logical simulation of the arithmetic expression shown in FIG. 3 i) is performed, and FIG. The contents of the code stored in advance in the FMEM10 when the logic simulation of the arithmetic expression shown in FIG.
It is a figure which shows the example of execution of the calculation performed by. In the figure, 10 ... storage means (FMEM) 20 ... first register (FTREG) 30 ... arithmetic circuit 40 ... intermediate register (IMREG) 50 ... second register (SDREG) 60 ... stack storage means (STUCK) 70 …… Stack pointer (STPR) 80 …… Control circuit

Claims (1)

[Claims] 1. A storage means for storing a description and an execution result according to a functional level simulation model, a first register which receives an output of the storage means as an input, a second register, and the second register. An arithmetic circuit that receives the outputs of the first register and the storage means and executes operations related to a functional operator, and an intermediate circuit that inputs the output of the arithmetic circuit and adds the output to the second register. A register, a stack storage unit that receives the output of the second register and the storage unit as an input, and a control unit that controls each unit based on the description of the simulation model stored in the storage unit. A logic simulator characterized by.