JPH0789556B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device such as a bipolar transistor using a III-V semiconductor and a method for manufacturing the same.

[Technical background of the invention and its problems]

Bipolar transistors using III-V semiconductors, especially heterojunction bipolar transistors, have a high cutoff frequency and operate at higher speed than conventional silicon bipolar transistors. In the heterojunction bipolar transistor, in order to accurately control the position of the heterojunction and the position of the Pn junction, an n / P / n three-layer structure wafer is usually formed by one crystal growth, and this three-layer structure wafer is used. Transistor is manufactured. In particular, the second P-type layer, which is the base layer, is extremely thin, around 100 nm, so many techniques and methods are known for forming the base electrode. FIG. 10 shows the base electrode structure by the simplest mesa etching. In such a structure, it is necessary to expose the thin base layer by etching, which requires extremely high precision in etching, which leads to deterioration in yield. FIG. 11 shows a structure in which a P-type external base region is formed by ion implantation or diffusion. In this structure, the base electrode is formed on a relatively thick P-type layer, so problems such as when using mesa etching can be avoided, but high temperature heat treatment is essential when forming the external base. Due to the diffusion of impurities, the heterojunction and the P / n junction are misaligned, resulting in deterioration of transistor characteristics.

[Object of the Invention]

An object of the present invention is to show a structure of a heterojunction bipolar transistor which can be manufactured at a lower temperature than that of a conventional method, and a method of manufacturing a transistor having a small parasitic capacitance suitable for high speed operation.

[Outline of Invention]

The present invention relates to platinum (Pt) or nickel (Ni) and III-V
A III-V compound semiconductor bipolar transistor in which an intermetallic compound with a group compound semiconductor is in contact with a base layer and a method for manufacturing the same are featured.

Example of Invention

Embodiments will be described below with reference to the drawings. FIG. 3 shows the structure of an epitaxial wafer formed on a semi-insulating GaAs substrate by the MBE method. n ⁺ GaAs layer 500 nm (1), nGaAs layer 50
0nm (2), P ⁺ GaAs layer 100nm (3), nAlGaAs layer 100nm
(4), n ⁺ GaAs layer 50 nm (5) is grown in this order. n ⁺ GaAs
(1) and nGaAs (2) are collectors, P ⁺ GaAs layer (3) is a base, and nAlGaAs (4) and n ⁺ GaAs (5) are emitters. Next, a SiO ₂ film with a thickness of 1 μm is deposited on the entire surface, and the Si 2
A platinum electrode pattern is formed by a lift-off method using the O ₂ film as a spacer. Platinum was deposited to 80 nm by electron beam evaporation. This is shown in FIG. 6 is platinum
7 of SiO ₂ spacer layer, the side etching of the SiO _2, the interval of the platinum and SiO ₂ has a 0.3 [mu] m. Next, this wafer is heat-treated at 400 ° C. for 10 minutes. At this time, platinum reacts with GaAs and AlGaAs in a solid state. This reaction becomes remarkable at 350 ° C. or higher, and is completed at about 400 ° C. in about 10 minutes. As a result of this reaction, platinum was exchanged with PtAs ₂ and PtGa and PtA.
l reactants are generated and penetrate into GaAs and AlGaAs. It is known that this penetration depth is about twice the deposited film thickness of platinum, and in the case of the present embodiment, it penetrates to 160 nm and reaches the base layer (3). This is shown in FIG. PtAs ₂ and PtGa form a Schottky contact with n-type GaAs and AlGaAs, and an ohmic contact with the high-concentration P-type GaAs layer. Therefore, platinum and GaAs and AlGa
The reaction layer (8) with As is in ohmic contact with the base layer (3). Next, as shown in FIG. 6, a photoresist is applied on the entire surface. The resist is etched by RIE using oxygen to expose SiO ₂ (7) as shown in FIG. SiO ₂ is dissolved with hydrofluoric acid, and AuGeNi alloy which is an ohmic electrode is vapor-deposited on the n-type GaAs layer. By dissolving the resist and lifting off AuGeNi on the resist, a structure as shown in FIG. 8 is obtained. Here, the emitter electrode (9)
The base electrode (8) and the base electrode (8) are positioned apart from each other by the side etch amount of the spacer SiO ₂ and can be easily positioned as in the present embodiment.
It can be about 3 μm, and the parasitic base resistance and parasitic collector / base capacitance can be reduced. Next, using the emitter electrode and the base electrode as a mask, boron is ion-implanted at an acceleration voltage of 20 KeV. As a result, the n-type GaAs and AlGaAs between the base electrode and the emitter electrode have high resistance, and the Schottky diode associated with the side wall of the base electrode is inactivated. In this way, the fine emitter shown in FIG.
The base structure was easily realized. Although not described because it is not within the scope of the present invention, H ⁺ ion implantation is used for the separation of the base / collector layer and the element separation, and the collector electrode is formed by the mesa etching for the buried n + GaAs layer (1 ) Was exposed and formed. According to this embodiment, the emitter area is 1.5 μm × 5 μm, the base / collector area is 3.5 μm × 5
An ECL ring oscillator was prototyped by making a μm transistor, and it was possible to obtain excellent characteristics with a delay time of 25 PS per gate.

[Other Embodiments of the Invention]

In the above embodiment, platinum is used as the metal that undergoes solid-phase reaction with GaAs, but the same effect can be expected when other metals such as nickel are used.

In the above embodiment, the patterning of the emitter electrode was performed after the formation of the base electrode, but conversely, if the emitter electrode is formed first, the effect of the invention is not impaired. In the above embodiment, the reaction layers of platinum, GaAs, and AlGaAs are located in the base layer (3), but the platinum deposition film thickness is increased so that the reaction layer reaches the collector layer (2). Is also good. This state is shown in FIG. In this case, since the platinum reaction layer makes a Schottky contact with the collector, as shown in FIG.
It is possible to realize the state where the transistor is provided with a sail key clamp without increasing the area of the element. Such a transistor is suitable for high-speed operation of saturation logic such as a TTL circuit.

〔The invention's effect〕

According to the present invention, a heterojunction bipolar transistor can be manufactured at a low temperature of 400 ° C. or less, and the influence of thermal diffusion of impurities in the conventional method can be eliminated. According to the present invention, the base contact can be formed without mesa etching,
It is easy to miniaturize the device.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view for explaining an embodiment of the present invention,
FIG. 2 is a sectional view of a structure for explaining another embodiment of the present invention, FIGS. 3 to 8 are sectional views of steps for explaining an embodiment of the manufacturing method of the present invention, and FIG. FIG. 10 and FIG. 11 which are diagrams showing an equivalent circuit of a transistor according to the present invention are configuration cross-sectional views showing a conventional example. 10 …… Boron-injected high resistance layer 11 …… Proton-injected high resistance layer 12 …… Proton-injected high resistance layer 13 …… Collector electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/20 29/43 29/73 8932-4M H01L 29/46 H 29/20

Claims (7)

[Claims] 1. A semiconductor device comprising a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having a first conductivity type from the front side. 2. A semiconductor device, comprising: an electrode in which an intermetallic compound is selectively formed to a depth of at least the second semiconductor layer from the surface, and which forms an ohmic contact with the second semiconductor layer. 2. The first semiconductor layer is an n-type III-V compound, the second semiconductor layer is a P-type III-V compound, and the third semiconductor layer is an n-type III-V compound. A family compound,
The semiconductor device according to claim 1, wherein the intermetallic compound extending from the first semiconductor layer to the second semiconductor layer is a compound of platinum and a III-V group element. 3. The semiconductor according to claim 1, wherein the intermetallic compound extending from the first semiconductor layer to the second semiconductor layer is a compound of nickel and a III-V group element. apparatus. 4. The semiconductor device according to claim 1, wherein the intermetallic compound extending from the first semiconductor layer to the second semiconductor layer reaches at least the third semiconductor layer. 5. The first semiconductor layer is an n-type III-V group compound, the second semiconductor layer is a P-type III-V group compound, and the third semiconductor layer is an n-type III-V compound. An intermetallic compound which is a group V compound and extends from the first semiconductor layer to the third semiconductor layer is selectively formed, and the intermetallic compound forms an ohmic contact with the second semiconductor layer, The semiconductor device according to claim 4, wherein a Schottky contact is formed with said semiconductor layer. 6. A semiconductor substrate in which a third semiconductor layer having a first conductor, a second semiconductor layer having a second conductor, and a first semiconductor layer having a first conductor type are stacked. A step of preparing, a step of forming a first electrode connected to the first semiconductor layer on the first semiconductor layer by a spacer lift-off method, and an entire surface of the substrate on which the first electrode is formed A step of applying an organic substance to the substrate, a step of etching the organic substance from the surface until the spacer used during the formation of the first electrode is exposed, and a step of etching and removing the spacer using the etched organic substance as a master, Depositing an electrode material on the entire surface using the organic material used as the mask as a mask; and dissolving the organic material and patterning the electrode material by a lift-off method to form a second electrode. And heating the substrate having the first electrode and the second electrode formed thereon to form an intermetallic compound with the second electrode, the second semiconductor layer, and the second electrode. And a step of forming an ohmic contact between the electrode and the second semiconductor layer. 7. A semiconductor substrate in which a third semiconductor layer having a first conductor, a second semiconductor layer having a second conductor, and a first semiconductor layer having a first conductor type are stacked. A step of preparing, (1) a step of forming a second electrode on the first semiconductor layer by a spacer lift-off method, and (2) an organic substance on the entire surface of the substrate on which the second electrode is formed. A step of applying, (3) a step of etching the organic matter from the surface until the spacer used in forming the second electrode is exposed, and (4) a step of etching and removing the spacer using the etched organic matter as a mask And (5) depositing an electrode material on the entire surface by using the organic material used as the mask as a mask, and (6) dissolving the organic material and patterning the electrode material by a lift-off method. The semiconductor layer and to and forming a first electrode connected, after step (1), wherein (2), (3), (4),
Before or after the step (5) or (6), at least the substrate on which the second electrode is formed is heated to remove the second electrode, the second semiconductor layer, and the intermetallic compound. And a step of forming an ohmic contact between the second electrode and the second semiconductor layer, the method for manufacturing a semiconductor device.