JPH0786869B2 - Information transmission method of multiprocessor system - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to an information transmission system of a multiprocessor system including a plurality of processor boards connected by a system bus.

[Prior art]

FIG. 7 is a block diagram showing an information transmission system of a conventional multiprocessor system disclosed in, for example, Japanese Patent Application Laid-Open No. 61-264467, in which 1a to 1c are processor boards and 2
Is a system bus connecting the processor boards 1a to 1c, 3 is an interrupt request circuit provided in the processor boards 1a to 1c, 4 is a shared memory connected to the system bus 2, Reference numerals 4a to 4c are information exchange areas of the shared memory 4 for the processor boards 1a to 1c. Next, the operation will be described. For example processor board 1a
When it is necessary to transfer information from the processor board 1b to the processor board 1b, the processor board 1a writes the information to be transferred to the information exchange area 4b of the shared memory 4 and executes the interrupt instruction to the processor board 1b. This interrupt instruction uses a normal input / output instruction (OUT instruction). By executing this instruction, the interrupt request circuit 3 of the processor board 1b
As a result, the interrupt signal (INT) is given to the central processing unit (hereinafter referred to as CPU) (not shown) of the processor board 1b, and the interrupt processing of the processor board 1b is executed. By this processing, the processor board 1b knows that the information for itself has been written and transmitted to the information exchange area 4b of the shared memory 4.

[Problems to be Solved by the Invention]

Since the information transmission method of the conventional multiprocessor system is configured as described above, it is not possible to receive information transmission from two or more processor boards 1a to 1c at the same time and receive an interrupt signal. Processor board 1a
˜1c has to determine which of the other processor boards is the information transmitted from the processor board by reading the contents of its own information exchange areas 4a to 4c of the shared memory 4, and System bus 2 for processing
Therefore, there is a problem that the utilization rate of the system bus 2 increases due to the operation of the determination process, system bus contention frequently occurs, and the performance of the entire system deteriorates. The present invention has been made to solve the above problems, and it is possible to receive information from a plurality of processor boards at the same time, and to simultaneously receive the information of the processor board ID of the information sending side and the information. By doing so, it is not necessary to acquire the right to use the system bus for checking the information content, and it is an object to obtain an information transmission method of a multiprocessor system that can improve the performance of the entire system.

[Means for solving problems]

An information transmission method of a multiprocessor system according to the present invention is provided with a memory unit for storing transmission information transmitted from another processor unit via a system bus, and when transmission information is written to the memory unit, An interrupt request signal indicating that information has been transmitted from another processor unit to its own central processing unit is generated.

[Action]

The information transmission method of the multiprocessor system according to the present invention is provided with a memory section for storing the transmission information transmitted from another processor unit via the system bus, and when the transmission information is written to the memory section, Even if an interrupt request signal indicating that information has been transmitted from another processor unit is transmitted to its own central processing unit,
You will be able to receive that information.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 1a to 1d are processor boards, 2 is a system bus for connecting the processor boards 1a to 1d and transmitting information, 5 is a CPU of the processor boards 1a to 1d, 6
Is memory used by CPU5, 7 is each processor board 1a-
1d is a local bus, 8 is a bus controller for controlling connection between the local bus 7 and the system bus 2, and 9 is arranged in each of the processor boards 1a to 1d, and both the system bus 2 and the local bus 7 are arranged. A multiprocessor communication controller (hereinafter referred to as MCC) connected to the bus, 10 is a memory circuit for exchanging information arranged in this MCC9, 11 is also arranged in MCC9, and the memory circuit 10 stores information An interrupt request generation circuit for detecting completion of writing and generating an interrupt request signal, and 12 is an interrupt request line for transmitting an interrupt request signal from the interrupt request generation circuit 11 to the CPU 5. 13 is the system bus 2
Is a shared input / output device (hereinafter referred to as shared IO), and 14 is a shared memory also connected to the system bus 2. FIG. 2 is a functional block diagram of the MCC 9, where 15 is a bus control unit for controlling the interface with the local bus 7.
Reference numeral 16 is an arbiter that arbitrates the internal access right of the MCC 9 by the local bus 7 and the system bus 2, and 17 is a bus control unit that controls the interface with the system bus 2. In addition, 18 is a memory unit divided into a plurality of memory blocks,
Reference numeral 19 is a board selection unit for recognizing its own board based on address information on the local bus 7 and the system bus 20,
Is a control register section corresponding to each of the memory blocks of the memory section 18 and comprising a first control register for setting a use-permitted memory block and a second control register for indicating the use state of the memory block, and 21 is a processor board 1a
~ Memory section based on the board ID information to identify 1d
The memory circuit 10 is composed of the memory unit 18, the board selecting unit 19, the control register unit 20, the ID identifying unit 21, and the like, which is an ID identifying unit that controls access to the corresponding memory block of 18. Further, 22 is a data buffer for interfacing the data line in the MCC 9 with the data line of the local bus 7, and 23 is a data buffer for interfacing the data line in the MCC 9 with the data line of the system bus 2. FIG. 3 is a block diagram showing the details of the main part of the memory circuit 10. In the figure, 18 is a memory section divided into eight memory blocks, first block to eighth block, and 20a is on the local bus 7. Since the CPU 5 sets the use-permitted memory blocks of the eight memory blocks of the memory unit 18, the first control register 20b provided corresponding to each memory block, 20b corresponds to each memory block, It is a second control register showing the usage state of them, and the control register unit 20 is constituted by both of them. Further, 21a is an ID storage register that stores the board ID information of the processor boards 1a to 1d using each memory block, 21b is an ID output signal line of this ID storage register 21a, and 21c is this ID output signal line. An ID comparison unit for comparing the board ID information on 21b with the board ID information sent together with the write information when writing on the data line of the system bus 2, 21d is an ID match output line of this ID comparison unit 21c, 21e is this I
A memory access control unit that generates an access signal to the memory unit 18 based on the match information of the D match output line 21d and the information of the read / write control signal line for the memory unit 18, 21f is output from this memory access control unit 21e An access permission signal, 21g, is an access prohibition signal output from the memory access control unit 21e. Fig. 4 shows the memory / register address transferred from the system bus 2 via the address line, the address data format of the transfer destination board ID number that specifies the transfer optical processor board, and the data transferred from the system bus 2 via the data line. Information that is the incoming memory / register write information
The data format of DATA and the transfer source board ID number that sets the processor board of the transfer light is shown. FIG. 5 is a block diagram showing a more detailed structure of the ID identifying section 21, and each reference numeral indicates the same part as that of FIG. Next, the operation will be described. Here, FIG. 6 is a flowchart showing an operation procedure of the information exchange process. Now, for example, when transmitting information from the processor board 1b to the processor board 1a, the board ID information of the processor board 1a is "1" and the board ID information of the processor board 1b is "2" on each of the processor boards 1a to 1d. It is assumed that they are recognized as the board ID information “4” of the processor board 1d. First, the processor board 1b sets "1" as the transfer destination board ID information to the address line on the system bus 2, register / register
The address information of the first control register 20a is output as a memory address, the content of the first control register 20a of the processor board 1a is read, and the use-permitted memory block of the memory unit 18 is recognized. Next, of the address information,
The register / memory address is changed to the address information of the second control register 20b, the content of the second control register 20b of the processor board 1a is read, and a usable memory block of the memory unit 18 is searched. When there is a usable memory block, the own board ID information, that is, “2” is written in the ID storage register 21a of the corresponding memory block. After that, the ID storage register 21a is read, and after confirming that the own board ID information “2” is written, the information is written in the corresponding memory block of the memory unit 18. This write operation is constantly monitored by the interrupt request generation circuit 11, and when the interrupt request generation circuit 11 confirms that the operation of writing information to the final address of the corresponding memory block is completed, the CPU 5 on the local bus 7 An interrupt request signal is sent to. As a result, the processor board 1a executes interrupt processing, and retrieves information from the corresponding memory block of the memory unit 18 in the own processor board 1a and processes it. As shown in FIG. 6, such a process is performed by a processor board 1b while another processor board 1b is transferring information.
It is also possible to transfer information from 1d to the same processor board 1a. In this case, processor board 1b
Needless to say, the processor board 1d transfers information to memory blocks of different memory units 18 of the processor board 1a. Next, the operation of the second control register 20b will be described. In FIG. 3, in the first control register 20a, the use permission flags of the memory blocks that are to be permitted to be used correspond to the memory blocks of the first block to the eighth block and correspond to the bit blocks of bit 1 to bit 8 respectively. A total of 8 bits are set. In this case, the first control register
The content of each bit of 20a is "1" to enable, and "0" to disable. When the operation of writing the board ID information from the data line to the ID storage register 21a corresponding to the permitted memory block is executed, the corresponding bit of the second control register 20b is also set to the busy flag state "1". Is set. When the operation of writing the board ID information of the data line to the ID storage register 21a corresponding to the memory block in which the bit corresponding to the memory block of the second control register 20b is in use is "1", the ID storage register The content of 20a does not change, and the write operation is not executed. As a result, the simultaneous write operations of the same memory blocks of the plurality of processor boards 1a to 1d connected on the system bus 2 can be restricted, contention can be prevented, and exclusive processing can be executed. Next, the ID comparison unit 21c will be described. In FIG. 5, the output signal from the ID output signal line 21b of the ID storage register 21a is selected based on the address information of the address line input from the system bus 2 at the same time when the corresponding memory block of the memory unit 18 is selected. The output gate of the ID storage register 21a corresponding to is selected and added to the ID comparison unit 21c. On the other hand, the board of the transfer source processor board included in the data information of the data line input from the system bus 2.
The ID information is added to the ID comparison unit 21c. Board ID information from the ID storage register 21a and board ID from the data line
When the information is compared and they match, an ID match signal is sent out from the ID match output line 21d of the ID comparison section 21c, and the memory access control section 21e outputs an access permission signal 21f to the memory section 18. Also, when the board ID information from the ID storage register 21a and the board ID information from the data line do not match, that is, the processor board that is permitted to use the corresponding memory block, for example, a processor board other than 1b, for example,
If 1d accesses the same memory block, ID comparison unit
A non-coincidence signal is sent from the ID coincidence output line 21d of 21c, and an access prohibition signal 21g is returned to the system bus 2 from the memory access control unit 21e. This prohibits other processor boards from accessing the same memory block. Next, the interrupt request generation circuit 11 will be described. The interrupt request generation circuit 11 constantly monitors the address signal of the address line from the system bus 2 and the access permission signal 21f of the memory access control unit 21e, and the access permission signal is sent to the final address of the corresponding memory block. Check and set the interrupt flag of the corresponding memory block. When all the interrupt flags corresponding to each memory block are combined and even one interrupt flag is set, when the interrupt flag is set, an interrupt request signal is sent to the CPU 5 via the interrupt signal line 12. In the above embodiment, the memory block of the memory unit 18 is divided into eight blocks. However, more memory blocks and sizes of each memory block may be provided. In addition, an example in which write / read access to the ID storage register 21a is restricted by the state of corresponding bits of the first control register 20a and the second control register 20b to prevent conflicting access from a plurality of processor boards 1a to 1d The first control register 20a and the second control register 20b have been described above.
The above-mentioned embodiment may be a composite of the above, or may not be a bit-compatible one, and the same effect as that of the above-described embodiment can be obtained as long as it is a system having another similar function. Further, when the MCC 9 of the present invention is provided on the shared I / 0 13 and the shared memory 14 shown in FIG. 1 and shared among the processor boards 1a to 1d as the intelligent I / 0 and the intelligent memory, the efficiency of the entire system is improved. Can be improved, and the same effect as that of the above-described embodiment can be obtained.

【The invention's effect】

As described above, according to the present invention, the memory unit for storing the transmission information transmitted from another processor unit via the system bus is provided, and when the transmission information is written to the memory unit, the self Since the central processing unit is configured to generate an interrupt request signal indicating that information has been transmitted from another processor unit, even if information is transmitted from multiple processor units at the same time, that information is received. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing an information transmission system of a multiprocessor system according to an embodiment of the present invention, and FIG.
Functional block diagram of MCC, FIG. 3 is a block diagram showing details of essential parts of the memory circuit, FIG. 4 is an explanatory diagram showing address format and data format, and FIG. 5 is a block diagram showing details of ID identifying section, FIG. 6 is a flowchart showing a data transfer procedure between processor boards, and FIG. 7 is a block diagram showing an information transmission system of a conventional multiprocessor system. 1a to 1d are processor boards, 2 is system bus, 5 is CP
U, 10 are memory circuits, 11 is an interrupt request generation circuit, 18 is a memory section, 19 is a board selection section, 20a is a first control register, 2
0b is the second control register, 21a is the ID storage register, and 21c is
ID comparison unit, 21e is a memory access control unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. In an information transmission system of a multiprocessor system in which a plurality of processor units having a central processing unit are coupled to each other via a system bus and information is exchanged between the processor units, the plurality of processor units are different from each other. A memory unit for storing transmission information transmitted from the processor unit of the system via the system bus;
A memory circuit having an interrupt request generation circuit for generating an interrupt request signal indicating that information has been transmitted from another processor unit to its own central processing unit in response to writing of transmission information to the memory section. An information transmission system for a multiprocessor system characterized by being provided. 2. An information transmission system for a multiprocessor system according to claim 1, wherein information exchange between the processor units is performed between central processing units provided in the processor units. 3. The memory control of the processor unit stores the ID information of the processor unit and the transmission information from the processor unit specified by the ID information among the transmission information transmitted via the system bus. An information transmission system for a multiprocessor system according to claim 1. 4. The memory circuit has a memory section having a memory block in which transmission information is written from another processor unit of an information transmission source, and ID information indicating an information transmission destination output from the other processor unit is its own ID. A unit selection unit that permits access to the memory unit when the information matches, a control register unit having information indicating whether the memory block is usable, and ID information of another processor unit that secures the memory block. Is stored in association with the memory block, and when the self ID information of the other processor unit output by the other processor unit when writing the transmission information to the memory block is different from the stored ID information, A patent contract characterized by having an ID identification section for prohibiting access to the memory block. Multiprocessor system information transmission method in the range preceding claim.