JPH0786797B2 - Electronics - Google Patents

Description

The present invention relates to an electronic device to which at least two keyboards can be connected.

(B) Conventional Technology In recent years, application software for computers, especially personal computers for general use, has been enriched and the contents thereof have become more sophisticated. As a result, as in the conventional case, only one keyboard cannot sufficiently exhibit the software capability, and therefore it is desired to connect a separate keyboard.

However, when two or more keyboards are connected, a large number of data may be input at the same time, and a countermeasure against this is necessary.

As such measures, there are methods disclosed in, for example, JP-A-62-187924 or JP-A-62-229419.

The method disclosed in the former publication has a switching key for each keyboard and selects a keyboard that can be input by operating such a key. On the other hand, the method disclosed in the latter publication is provided with a data input means for collectively managing a plurality of keyboards, and such means reads the input from each keyboard by sequentially polling each keyboard.

(C) Problems to be Solved by the Invention However, the former method has a problem that the input speed is reduced due to the need for a human operation of switching the keyboard, while the latter method does not poll. There is a problem that what is input on the keyboard cannot be read.

(D) Means for Solving the Problems The present invention has been made in view of the above point, and its structural feature is to respond to key inputs on the first and second keyboards and the first keyboard. Connected to and output from a first encoder that outputs a signal, a second encoder that outputs a signal in response to a key input on the second keyboard, and the first and second encoders. A control means for controlling the signal based on a signal; and a switch means for controlling the connection between the second encoder and the control means. Further, the first and second encoders receive signals from the other encoder. When being output, the output of the signal in response to the key input is stopped, and the first encoder controls the opening / closing of the switch means based on the presence or absence of the signal output from the second encoder. Lies in the fact.

(E) Operation In such a configuration, each keyboard controls the output of a signal in response to a key input according to the input state of the other keyboard.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.

Both the first and second keyboards (1) and (2) in the figure have key switches (not shown) arranged in a matrix.
The keyboards (1) and (2) are scanned based on the scan signals sent from the first and second encoders (3) and (4) via the scan lines SL1 and SL2, respectively. Also,
When the key switch is pressed at this time, the return line RL
The return signal corresponding to the pressed key is sent back to the first and second encoders (3) and (4) via 1 and RL2.

Each of the first and second encoders (3) and (4) is composed of a one-chip microcomputer, and each has a CPU (3a) (4).
a), ROM (3b) (4b) and RAM (3c) (4c).
And each encoder (3) (4) is ROM (3b) (4b)
Based on the control program stored in, the keyboard is scanned as described above and the return signal returned in response to the scanning is converted into corresponding code data. Under the control, the clock signal is output from the clock line (KBCLK) and the code data is serially output to the data line (KBDATA) in synchronization with the signal. Since such data transfer is so-called synchronous, a start bit and a stop bit are added before and after each output key code. The control operation of each encoder (3) (4) will be described in detail later.

The signals sent to the clock line (KBCLK) and the data line (KBDATA) are input to the sub-control unit (5) including, for example, a microcomputer. The sub control unit (5) is
Under the control of the main control unit (6) composed of a microcomputer, the code data input via the data line (KBDATA) is directly sent to the main control unit (6) or the storage means (7).
Or store it in. Also, the sub-control unit (5) outputs a data transfer end signal (SCPRTS) to the first encoder (3) via the first control line (CL1) every time a stop bit is input from the data line (KBDATA). .

On the other hand, the first and second analog switches (8a) and (8b) are arranged on the clock line (KBCLK) and the data line (KBDATA) that connect the second encoder (4) and the sub control unit (5). The opening and closing are controlled by the first encoder (3). In addition, the clock line of the second encoder (4) (KBCL
The clock signal output terminal connected to K) is also connected to the first encoder (3) and further to the state buffer (9) controlled by the first encoder (3). The other end of the buffer (9) is grounded.

Next, the operation based on the control program of the first encoder (3) will be described, but basically, the first encoder (3)
Processes the following two operations in a time division manner or in parallel.

(I) Reading the pressed key on the first keyboard (1) (ii) Detecting the state of the second encoder (4) and the sub-control unit (corresponding to the key read by the above process (i) ( Output to 5) FIG. 2 (a) is a flowchart showing the processing of (i). First, when the power is turned on, the contents of RAM (3c) are cleared in step S101.

Then, in step S102, a scan signal is sent to the first keyboard (1), and when a return signal is sent back from the first keyboard (1) in response to the signal, this is detected in step S103, and the subsequent S104 The return signal is stored in the RAM (3c) in step. When no return signal is detected in step S103, or when step S104 ends, the process returns to step S102.

Therefore, by repeating steps S102 to S104,
A return signal corresponding to a key pressed on the first keyboard (1) is sequentially stored in the RAM (3c).

FIG. 2 (b) is a flowchart showing the process of (ii) above. First, when the power is turned on, initialization processing is performed in step S105. Specifically, by opening the first and second analog switches (8a) and (8b) and outputting the "H" signal to the state buffer (9), the state is set to the open state and the variable Flag is set to "0". To Such Flag is RA
It is held in a predetermined area in M (3c).

Next, in step S106, it is determined whether the clock signal is output from the second encoder (4). If it is determined that the output is made in such determination, the process proceeds to S107.
Go to step.

In step S107, it is determined whether Flag is "1",
If it is determined to be "1", the process returns to step S106. On the other hand, when it is determined that the flag is not "1", the first and second analog switches (8a) and (8b) are closed in step S108 and the flag is changed to "1" in step S109, and then the process is step S106. Return to.

Returning to step S106, if it is determined that the clock signal is not output in such step, the process proceeds to step S110. In step S110, it is determined whether Flag is "0".

In such a determination, if it is determined to be “0”, the process is S1.
Go to step 14. On the other hand, if it is determined that it is not “0”, S1
After sequentially processing steps 11 to S113, the process proceeds to step S114.

In step S111, the output of the data transfer end signal (SCPRTS) from the sub-control unit (5) is waited, and when such a signal is output, Flag is set to "0" in step S112, and in step S113, The first and second analog switches (8a) and (8b) are opened.

In step S114, it is determined whether the return signal is stored in the RAM (3c). If it is determined that the return signal is not stored in the RAM (3c), the process returns to step S106.

Therefore, when there is no input from the first keyboard (1) at all and only the key input from the second keyboard (2) occurs, the first encoder (3) basically operates in S106-
It is only necessary to control the opening and closing of the first and second analog switches (8a) and (8b) based on the presence or absence of the clock signal output from the second encoder while repeatedly performing the step S114.

On the other hand, when it is determined that the return signal is stored in step S114, steps S115 to S117 are sequentially processed.

In step S117, the clock signal output terminal of the second encoder (4) connected to the buffer (9) is set to the ground state by outputting the "L" signal to the state buffer (9). Next, in step S116, RAM (3c)
The return signals stored therein are read out in the order of storage, the return signals are converted into corresponding code data, and the data are serially sent to the sub control unit (5) via the data line (KBDATA). To do. At the time of such transmission, a start bit and a stop bit are added before and after each data transmitted as described above, and a clock line (KBCL
A clock signal is sent on K). Also, the returned return signal is erased from the RAM (3c).

When the transmission of the code data in step S116 is completed, the "H" signal is output to the state buffer (9) in step S117 to release the code. Thereafter, the processing returns to step S106.

Therefore, the first encoder (3) uses the RAM (3
If it is determined that the return signal is stored in c), S
By processing steps 115 to S117, the code data corresponding to the return signal is output to the sub control unit (5), and the clock signal output end of the second encoder (4) is set to the grounded state during this period.

FIG. 3 is a flowchart showing the control operation based on the control program stored in the ROM (4b) of the second encoder (4), and the operation of the second encoder (4) will be described below according to such a flow. To do.

First, when the power is turned on, the RAM is
Clear the contents of (4c). Next, in steps S203 and S204, a return signal is awaited while sending a scan signal to the second keyboard (2) as in steps S102 and S103 described above. When the return signal is returned, the process proceeds from step S203 to step S204.

In step S204, the return signal returned from the second keyboard (2) is stored in the RAM (4c). Next, in step S205, it is determined whether the clock signal output terminal is in the grounded state.

When it is determined in this determination that the vehicle is in the ground contact state, steps S206 and S207 are processed. Specifically, in step S206, a scan signal is sent to the second keyboard (2), and in step S207, it is determined whether or not a return signal has been sent back from the second keyboard (2) in response to the scan signal.

In such a determination, if it is determined that the return signal is returned, the process returns to step S204. If it is determined that the return signal has not been returned, the process returns to step S205.

Returning to step S205, if it is determined in this step that the vehicle is not in the grounded state, the process proceeds to step S208. In such a step, the code data corresponding to the return signal in the RAM (4c) is transferred to the sub control unit (5) as in the step S116 described above.
To output sequentially. Thereafter, the processing returns to step S202.

Therefore, the second encoder (4) is the second keyboard (1).
RAM (4
In addition, the code data corresponding to the return signal is sent to the sub control unit (5) when the clock signal output end is not in the grounded state.

As is apparent from the above description, in the device of this embodiment, the first
While the encoder (3) is sending the code data to the sub-control unit (5), the clock signal output end of the second encoder (4) is grounded. Therefore, the second encoder (4)
The return signal in response to the key input on the second keyboard (2) read by the
It is only sequentially stored in c) and is not output to the sub control unit (5). After that, when the output of the code data from the first encoder (3) ends, the encoder (3)
Cancels the grounded state of the clock signal output terminal of the second encoder (4). As a result, the second encoder (4) detects this and outputs the code data corresponding to the return signal in the RAM (4c). In response to the data output, the first encoder (4) outputs the code data.
The encoder (3) has first and second analog switches (8
Since a) and (8b) are closed, the above data is stored in the sub controller (5)
Will be sent to.

On the other hand, when the code data is transmitted from the second encoder (4), the first encoder (3) detects it and closes the first and second analog switches (8a) (8b). At the same time, the return signal in response to the key input on the first keyboard (1) is stored in the RAM (3c) but is not output to the sub control unit (5). After that, when the output of the code data from the second encoder (4) ends, the first encoder (3) detects this and waits for the output of the data transfer end signal (SCPRTS) from the sub-control unit (5). The first and second analog switches (8a) and (8b) are opened. Next, when the return signal is stored in the RAM (3c), after sending the "L" signal to the state buffer (9) to ground the clock signal output end of the second encoder (4), The code data corresponding to the return signal in (3c) is output to the sub control unit (5).

In this embodiment, the device having the two control units, the main control unit (6) and the sub control unit (5), has been described, but the main control unit (6) functions as the sub control unit (5). It is extremely easy for a person skilled in the art to have one control unit by having it, and it does not depart from the gist of the present invention.

Further, the return signal itself is stored in the RAM (3c) (4c) of each encoder (3) (4), but it is also possible to store the code data corresponding to the above-mentioned return signal from the gist of the present invention. It does not deviate.

Further, in the second encoder (4) of this embodiment, the key scan and the output of the code data are sequentially performed as shown in FIG. It may be divided.

According to the present invention, the first and second encoders monitor the output of the other encoder, buffer the signal input from the keyboard when the other encoder is in the output state, and Outputs buffered signal when output is stopped. Therefore, it is possible to simultaneously input from the two keyboards and there is no problem that the inputs are not read.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 (a) (b) and 3 are flow charts for explaining the operation of this embodiment. (1) (2) ... First and second keyboards, (3) (4)
...... First and second encoders, (5) ...... Sub control unit (control means), (8a) (8b) ...... First and second analog switches (switch means)

Claims (1)

[Claims] 1. A first and second keyboard, and a first keyboard for outputting a signal in response to a key input on the first keyboard.
A first encoder having one CPU means and a first RAM means; a second encoder having a second CPU means and a second RAM means for outputting a signal in response to a key input on the second keyboard; Control means connected to the second encoder for controlling the signals based on signals output from these encoders; switch means for controlling the connection between the second encoder and the control means under the control of the first encoder; A state buffer controlled by the first encoder so as to be in a first state when there is a signal output from the first encoder and to be in a second state when there is no signal output, the first CPU of the first encoder Stores the input from the first keyboard in the first RAM means in sequence and determines the presence or absence of the signal output of the second encoder to generate the signal output. If not, the data stored in the first RAM means is output to the control means, the switch means is opened only during this signal output period, and the state buffer is controlled to be in the first state. The second CPU of the second encoder sequentially stores the input from the second keyboard in the second RAM means, and when it detects that the state of the state buffer is in the second state, it stores the data in the second RAM. An electronic device which controls to output to the control means.